Fluid Growth From Gaseous State Combined With Subsequent Diverse Operation Patents (Class 438/507)
  • Patent number: 10727226
    Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a gate structure and a source/drain feature. The gate structure is positioned over a fin structure. The source/drain feature is positioned adjacent to the gate structure. A portion of the source/drain feature embedded in the fin structure has an upper sidewall portion adjacent to a top surface of the fin structure and a lower sidewall portion below the upper sidewall portion. A first curve radius of the upper sidewall portion is different from a second curve radius of the lower sidewall portion in a cross-sectional view substantially along the longitudinal direction of the fin structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chen, Chia-Ling Chan, Liang-Yin Chen, Huicheng Chang
  • Patent number: 10624213
    Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Amruthavalli Pallavi Alur, Wei-Lun Kane Jen, Sriram Srinivasan
  • Patent number: 10128357
    Abstract: A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same material—graphene.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: November 13, 2018
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Adam L. Friedman, Olaf M. J. van't Erve, Jeremy T. Robinson, Berend T. Jonker, Keith E. Whitener
  • Patent number: 9929096
    Abstract: An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 27, 2018
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Ming Zhou
  • Patent number: 9882004
    Abstract: A semiconductor device includes a substrate, an active fin protruding from the substrate, and an asymmetric diamond-shaped source/drain disposed on an upper surface of the active fin. The source/drain includes a first crystal growth portion and a second crystal growth portion sharing a plane with the first crystal growth portion and having a lower surface disposed at a lower level than a lower surface of the first crystal growth portion.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 30, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jongki Jung, Myungil Kang, Yoonhae Kim, Kwanheum Lee
  • Patent number: 9552958
    Abstract: A method for using a Focused Ion Beam and/or Scanning Electron Microscope (FIB/SEM) for etching one or more alignment markers on a rock sample, the one or more alignment markers being etched on the rock sample using the FIB/SEM. The one or more alignment markers may further be deposited with a platinum alloy or other suitable compositions for increasing alignment marker visibility.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: January 24, 2017
    Assignee: Weatherford Technology Holdings, LLC
    Inventor: Kultaransingh N. Hooghan
  • Patent number: 9496396
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a gate structure on the substrate; (c) performing a first deposition process to form a first epitaxial layer adjacent to the gate structure and performing a first etching process to remove part of the first epitaxial layer at the same time; and (d) performing a second etching process to remove part of the first epitaxial layer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 15, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Chun-Liang Kuo, Tsang-Hsuan Wang, Sheng-Hsu Liu, Chieh-Lung Wu, Chung-Min Tsai, Yi-Wei Chen
  • Patent number: 9312129
    Abstract: A method of forming a semiconductor substrate including providing a base substrate including a semiconductor material, and forming a first semiconductor layer overlying the base substrate having a Group 13-15 material via hydride vapor phase epitaxy (HVPE), the first semiconductor layer having an upper surface having a N-face orientation.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: April 12, 2016
    Assignee: SAINT-GOBAIN CRISTAUX ET DETECTEURS
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Patent number: 9299812
    Abstract: Provided are methods of forming a semiconductor device having an embedded stressor. The method includes forming a fin active area on a substrate. A gate structure configured to cross the fin active area and cover a side surface of the fin active area, and a gate spacer on a sidewall of the gate structure are formed. Preliminary trenches are formed in the fin active area adjacent to both sides of the gate structure using an anisotropic etching process. An etching select area is formed by oxidizing the fin active area exposed to the preliminary trenches. Trenches are formed by removing the etching select area. A stressor is formed in each of the trenches.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: March 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jun-Suk Kim
  • Patent number: 9061912
    Abstract: Methods of fabricating graphene nanoribbons include depositing a catalyst layer on a substrate. A masking layer is deposited on the catalyst layer. The masking layer and the catalyst layer are etched to form a structure on the substrate, the structure comprising a portion of the catalyst layer and a portion of the masking layer disposed on the catalyst layer, with sidewalls of the catalyst layer being exposed. A graphene layer is formed on a sidewall of the catalyst layer with a carbon-containing gas.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: June 23, 2015
    Assignee: The Regents of the University of California
    Inventor: Yuegang Zhang
  • Patent number: 9048244
    Abstract: A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the single-crystalline substrate having a surface area; forming a marking structure on the surface area of the single-crystalline substrate, wherein the marking structure comprises a first semiconductor material; and depositing a semiconductor layer on the marking structure and at least partially on the surface area of the single-crystalline substrate, wherein the semiconductor layer comprises the second semiconductor material, and wherein the marking structure is buried under the second semiconductor material.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: June 2, 2015
    Assignee: Infineon Technologies AG
    Inventor: Thomas Popp
  • Patent number: 9034739
    Abstract: A method of making a semiconductor device comprises: providing a semiconductor wafer having a semiconductor layer; forming a first mask layer over the semiconductor layer; forming a second mask layer over the first mask layer; annealing the second mask layer to form islands; etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars; and growing semiconductor material between the pillars and then over the tops of the pillars.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: May 19, 2015
    Assignee: Seren Photonics Limited
    Inventor: Tao Wang
  • Patent number: 9029873
    Abstract: The semiconductor device includes a SiC substrate; an aluminum nitride layer provided on the substrate and having an island-shaped pattern consisting of plural islands: a channel layer provided on the AlN layer and comprising a nitride semiconductor; an electron supplying layer provided on the channel layer and having a band gap larger than that of the channel layer; and a gate, source and drain electrodes on the electron supply layer. The AlN layer has an area-averaged circularity Y/X of greater than 0.2. Y is a sum of values obtained by multiplying circularities of the plural islands by areas of the plural islands respectively, X is a sum of the areas of the plural islands. The circularity are calculated by a formula of (4?×area)/(length of periphery)2 where the area and the length of periphery are an area and a length of periphery of each island.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: May 12, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ken Nakata, Keiichi Yui, Tsuyoshi Kouchi, Isao Makabe, Hiroyuki Ichikawa
  • Patent number: 9023718
    Abstract: A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Do, Ha-Jin Lim, Weon-Hong Kim, Hoi-Sung Chung, Moon-Kyun Song, Dae-Kwon Joo
  • Publication number: 20150118831
    Abstract: A method of forming a free-standing silicon film that includes providing a Si substrate, depositing a layered structure on the Si substrate, where the layered structure includes a Si device layer and a SiGe sacrificial layer, and removing the SiGe sacrificial layer with a spin etch process, where the Si device layer is released from the layered structure.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 30, 2015
    Inventors: Andrei T. Iancu, Friedrich B. Prinz
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8986464
    Abstract: A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 105 Pa·S or more and 1014.5 Pa·S or less in a temperature range of 950 to 1400° C.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Yukimune Watanabe
  • Patent number: 8980730
    Abstract: Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: March 17, 2015
    Assignee: STC.UNM
    Inventors: Seung-Chang Lee, Steven R. J. Brueck
  • Patent number: 8975168
    Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: March 10, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Qing Liu, Nicolas Loubet
  • Patent number: 8969185
    Abstract: A manufacturing apparatus and a manufacturing method for a quantum dot material. The manufacturing apparatus adds an optical device capable of generating an interference pattern in an existing epitaxial apparatus, so that a substrate applies an interference pattern on an epitaxial layer while performing epitaxial growth. By means of the interference pattern, a regularly distributed temperature field is formed on the epitaxial layer, so that on the epitaxial layer, an atom aggregation phenomenon is formed at dot positions with higher temperature, but no atoms are aggregated on areas having relatively lower temperature. Therefore, according to the temperature distribution on the surface of the epitaxial layer, positions where quantum dots generate can be controlled manually without introducing defects, thereby achieving a defect-free and long-range ordered quantum dot manufacturing.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: March 3, 2015
    Assignee: Soochow University
    Inventor: Changsi Peng
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8945302
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Mosaic Crystals Ltd.
    Inventor: Moshe Einav
  • Publication number: 20150014631
    Abstract: GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.
    Type: Application
    Filed: February 12, 2013
    Publication date: January 15, 2015
    Inventors: Jonas Ohlsson, Mikael Bjork
  • Publication number: 20150017790
    Abstract: A method for manufacturing a semiconductor device includes: preparing a Si substrate having a flat portion with flat front and back surfaces and a bevel portion located at a periphery of the flat portion; forming a III-V nitride semiconductor film on the front surface of the Si substrate by epitaxial growth; and after forming the III-V nitride semiconductor film, grinding the Si substrate from the back surface. Amounts of working at the bevel portion on the front surface and the back surface of an outermost end portion of the bevel portion are asymmetrical. A first thickness measured from the front surface of the flat portion to the outermost end portion is smaller than a second thickness measured from the back surface of the flat portion to the outermost end portion.
    Type: Application
    Filed: March 26, 2014
    Publication date: January 15, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventor: Takahiro Yamamoto
  • Patent number: 8921210
    Abstract: A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: December 30, 2014
    Assignee: Saint-Gobain Cristaux et Detecteurs
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Patent number: 8916458
    Abstract: An III-nitride quantum well structure includes a GaN base, an InGaN layer and an InGaN covering layer. The GaN base includes a GaN buffering layer, a GaN post extending from the GaN buffering layer, and a GaN pyramid gradually expanding from the GaN post to form a mounting surface. The InGaN layer includes first and second coupling faces. The first coupling face is coupled with the mounting surface. The GaN covering layer includes first and second coupling faces. The first coupling face of the GaN covering layer is coupled with the second coupling face of the InGaN layer. A method for manufacturing the III-nitride quantum well structure and a light-emitting unit having a plurality of III-nitride quantum well structures are also proposed.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: December 23, 2014
    Assignee: National Sun Yat-Sen University
    Inventors: I-Kai Lo, Yu-Chi Hsu, Cheng-Hung Shih, Wen-Yuan Pang, Ming-Chi Chou
  • Patent number: 8912079
    Abstract: Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: December 16, 2014
    Assignees: The University of Tokyo, V Technology Co., Ltd.
    Inventors: Motoichi Ohtsu, Takashi Yatsui, Tadashi Kawazoe, Shunsuke Yamazaki, Koichi Kajiyama, Michinobu Mizumura, Keiichi Ito
  • Patent number: 8912070
    Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stack structure on a substrate; forming a drain region in the substrate on one side of the gate stack structure; and forming a source region made of GeSn in the substrate on the other side of the gate stack structure; wherein the forming the source region made of GeSn comprises: implanting precursors in the substrate on the other side of the gate stack structure; and performing a laser rapid annealing such that the precursors react to produce GeSn alloy, thereby to constitute a source region; and wherein the step of implanting precursors further comprises: performing a pre-amorphization ion implantation, so as to form an amorphized region in the substrate; and implanting Sn in the amorphized region.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: December 16, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Xiaolong Ma, Huaxiang Yin, Zuozhen Fu
  • Publication number: 20140357067
    Abstract: A method of manufacturing a nitride substrate includes the following steps. Firstly, a nitride crystal is grown. Then, the nitride substrate including a front surface is cut from the nitride crystal. In the step of cutting, the nitride substrate is cut such that an off angle formed between an axis orthogonal to the front surface and an m-axis or an a-axis is greater than zero. When the nitride crystal is grown in a c-axis direction, in the step of cutting, the nitride substrate is cut from the nitride crystal along a flat plane which passes through a front surface and a rear surface of the nitride crystal and does not pass through a line segment connecting a center of a radius of curvature of the front surface with a center of a radius of curvature of the rear surface of the nitride crystal.
    Type: Application
    Filed: August 18, 2014
    Publication date: December 4, 2014
    Inventors: Satoshi ARAKAWA, Michimasa MIYANAGA, Takashi SAKURADA, Yoshiyuki YAMAMOTO, Hideaki NAKAHATA
  • Patent number: 8895415
    Abstract: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: November 25, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Keith Fox, Dong Niu, Joseph L. Womack
  • Publication number: 20140339505
    Abstract: Virtual substrates made by hydride vapor phase epitaxy are provided comprising a semiconductor growth substrate and a substantially strain-relaxed metamorphic buffer layer (MBL) structure comprising one or more layers of a semiconductor alloy on the growth substrate. The MBL structure is compositionally graded such that its lattice constant transitions from a lattice constant at the interface with the growth substrate that is substantially the same as the lattice constant of the growth substrate to a lattice constant at a surface opposite the interface that is different from the lattice constant of the growth substrate. The virtual substrates comprise relatively thick MBL structures (e.g., >20 ?m) and relatively thick growth substrates (e.g., >0.
    Type: Application
    Filed: May 15, 2013
    Publication date: November 20, 2014
    Applicant: Wisconsin Alumni Research Foundation
    Inventors: Thomas F. Kuech, Kevin L. Schulte, Luke J. Mawst, Tae Wan Kim, Brian T. Zutter
  • Patent number: 8883598
    Abstract: Semiconductor devices and methods of forming the same. The method includes providing a semiconductor substrate having a channel layer over the substrate. A capping layer including silicon and having a first thickness is formed over the channel layer. The capping layer is partially oxidized to form an oxidized portion of the capping layer. The oxidized portion of the capping layer is removed to form a thinned capping layer having a second thickness less than the first thickness.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Ting Chu, Shih-Hsun Chang, Pang-Yen Tsai
  • Patent number: 8846496
    Abstract: To provide a method of obtaining a single crystal semiconductor film by a method that is simple and low-cost. A single crystal semiconductor film 11 having compression stress is formed over a surface of a single crystal semiconductor substrate 10 by a vapor phase epitaxial growth method, a film having tensile stress (for example, a thermo-setting resin film 12) is formed over a surface of the single crystal semiconductor film 11, and the single crystal semiconductor substrate 10 and the single crystal semiconductor film 11 are separated from each other by a separation step in which force is applied to the single crystal semiconductor film 11, thereby obtaining a single crystal semiconductor film. Note that as the thermo-setting resin film 12, an epoxy resin film can be used, for example.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Sho Kato, Kazutaka Kuriki
  • Patent number: 8842710
    Abstract: There are provided a process for producing a semiconductor device and a semiconductor device which allow conductivity distribution to be formed without making refractive index distributed even in a material system of a semiconductor difficult to be subjected to ion implantation. The process for producing a semiconductor device includes the steps of forming a semiconductor layer containing a dopant; forming a concave and convex structure on the semiconductor layer by partially removing the semiconductor layer; and forming a conductivity distribution reflecting the concave and convex structure in the semiconductor layer by performing heat treatment on the semiconductor layer in which the concave and convex structure has been formed at a temperature at which a material forming the semiconductor layer causes mass transport and filling up a hole of a concave portion of the concave and convex structure with the material forming the semiconductor layer.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: September 23, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Nagatomo, Takeshi Kawashima, Katsuyuki Hoshino, Shoichi Kawashima
  • Publication number: 20140273419
    Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a vacuum chamber having a dome and a floor. A substrate support is disposed inside the vacuum chamber. A plurality of thermal lamps are arranged in a lamphead and positioned proximate the floor of the vacuum chamber. A reflector is disposed proximate the dome, where the reflector and the dome together define a thermal control space. The substrate processing apparatus further includes a plurality of power supplies coupled to the thermal lamps and a controller for adjusting the power supplies to control a temperature in the vacuum chamber.
    Type: Application
    Filed: May 30, 2014
    Publication date: September 18, 2014
    Inventors: Joseph M. RANISH, Paul BRILLHART, Jose Antonio MARIN, Satheesh KUPPURAO, Balasubramanian RAMACHANDRAN, Swaminathan T. SRINIVASAN, Mehmet Tugrul SAMIR
  • Publication number: 20140264384
    Abstract: A method of forming an epitaxial SiC film on SiC substrates in a warm wall CVD system, wherein the susceptor is actively heated and the ceiling and sidewall are not actively heated, but are allowed to be indirectly heated by the susceptor. The method includes a first process of reaction cell preparation and a second process of epitaxial film growth. The epitaxial growth is performed by flowing parallel to the surface of the wafers a gas mixture of hydrogen, silicon and carbon gases, at total gas velocity in a range 120 to 250 cm/sec.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: DOW CORNING CORPORATION
    Inventors: Mark J. Loboda, Jie Zhang
  • Publication number: 20140256120
    Abstract: A method for preparing graphene by reaction with Cl2 based on annealing with assistant metal film is provided, comprising the following steps: applying normal wash to a Si-substrate, then putting the Si-substrate into a reaction chamber of a CVD system and evacuating, rising the temperature to 950° C. -1150° C. gradually, supplying C3H8 and carbonizing the Si-substrate for 3-10 min; rising the temperature to 1150° C.-1350° C. rapidly, supplying C3H8 and SiH4, growing a 3C—SiC hetero-epitaxial film on the carbonized layer, and then reducing the temperature to ambient temperature under the protection of H2 gradually, introducing the grown sample wafer of 3C—SiC into a quartz tube, heating to 700-1100° C., supplying mixed gas of Ar and Cl2, and reacting Cl2 with 3C—SiC to generate a carbon film, applying the sample wafer of carbon film on a metal film, annealing at 900° C.-1100° C.
    Type: Application
    Filed: September 3, 2012
    Publication date: September 11, 2014
    Applicant: Xidian University
    Inventors: Hui Guo, Keji Zhang, Yuming Zhang, Penfgei Deng, Tianmin Lei
  • Publication number: 20140252376
    Abstract: A method for manufacturing a silicon carbide substrate includes the following steps. A silicon carbide single-crystal substrate is prepared. A silicon carbide epitaxial layer is formed in contact with the silicon carbide single-crystal substrate. A silicon layer is formed in contact with a second surface of the silicon carbide epitaxial layer opposite to a first surface thereof that makes contact with the silicon carbide single-crystal substrate. Accordingly, there are provided a silicon carbide substrate, a method for manufacturing the silicon carbide substrate, and a method for manufacturing a silicon carbide semiconductor device so as to achieve prevention of contamination of a silicon carbide epitaxial layer in a simple manner.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 11, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Satomi ITOH
  • Publication number: 20140256119
    Abstract: A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung TSAI, Meng-Yueh LIU, Chien-Chang SU, Yuan-Feng CHAO, Yuh-Da FAN
  • Patent number: 8821635
    Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: September 2, 2014
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
  • Patent number: 8816366
    Abstract: An object of the present invention is to provide a nitride semiconductor device which shifts a luminescence wavelength toward a longer wavelength side without decreasing luminescence efficiency, and the nitride semiconductor device according to an implementation of the present invention includes: a GaN layer having a (0001) plane and a plane other than the (0001) plane; and an InGaN layer which contacts the GaN layer and includes indium, and the InGaN layer has a higher indium composition ratio in a portion that contacts the plane other than the (0001) plane than in a portion that contacts the (0001) plane.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: August 26, 2014
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Takizawa, Tetsuzo Ueda
  • Patent number: 8815621
    Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: August 26, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaki Ueno, Yusuke Yoshizumi, Takao Nakamura
  • Patent number: 8815717
    Abstract: According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Harada, Koichi Tachibana, Toshiki Hikosaka, Hajime Nago, Shinya Nunoue
  • Patent number: 8809867
    Abstract: Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar III-nitride films initially grow vertically through openings in the dielectric mask before laterally overgrowing the mask in directions perpendicular to the vertical growth direction. Threading dislocations are reduced in the overgrown regions by (1) the mask blocking the propagation of dislocations vertically into the growing film and (2) the bending of dislocations through the transition from vertical to lateral growth.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: August 19, 2014
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, Steven P. Denbaars, James S. Speck, Shuji Nakamura
  • Patent number: 8809170
    Abstract: Methods of selective formation leave high quality epitaxial material using a repeated deposition and selective etch process. During the deposition process, an inert carrier gas is provided with a silicon-containing source without hydrogen carrier gas. After depositing silicon-containing material, an inert carrier gas is provided with an etchant to selectively etch deposited material without hydrogen. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is achieved. Using the processes described within, it is possible to maintain temperature and pressure conditions, as well as inert carrier gas flow rates, to provide for increased throughput. The inert flow can be constant, or etch rates can be increased by reducing inert flow for the etch phases of the cycles.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: August 19, 2014
    Assignee: ASM America Inc.
    Inventor: Matthias Bauer
  • Patent number: 8802546
    Abstract: Gas containing Si, gas containing C and gas containing Cl are introduced into a reacting furnace. SiC epitaxial film is grown on the surface of a 4H—SiC substrate by CVD in a gas atmosphere including raw material gas, additive gas, doping gas and carrier gas. The amount of the gas containing Cl relative to the gas containing Si in the gas atmosphere is reduced gradually. At the start of growth, the number of Cl atoms in the gas containing Cl is three times as large as the number of Si atoms in the gas containing Si. The number of Cl atoms in the gas containing Cl relative to the number of Si atoms in the gas containing Si in the gas atmosphere is reduced at a rate of 0.5%/min to 1.0%/min. The method grows silicon carbide semiconductor film at a high rate.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: August 12, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuyuki Kawada, Yoshiyuki Yonezawa
  • Patent number: 8785976
    Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gas is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 22, 2014
    Assignees: The University of Sheffield, Powdec K.K.
    Inventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil, Yasunobu Sumida, Hiroji Kawai
  • Patent number: 8765500
    Abstract: The present disclosure involves a method of packaging a light-emitting diode (LED). According to the method, a group of metal pads and a group of LEDs are provided. The group of LEDs is attached to the group of metal pads, for example through a bonding process. After the LEDs are attached to the metal pads, each LED is spaced apart from adjacent LEDs. Also according to the method, a phosphor film is coated around the group of LEDs collectively. The phosphor film is coated on top and side surfaces of each LED and between adjacent LEDs. A dicing process is then performed to slice through portions of the phosphor film located between adjacent LEDs. The dicing process divides the group of LEDs into a plurality of individual phosphor-coated LEDs.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 1, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chi-Xiang Tseng, Hsiao-Wen Lee, Min-Sheng Wu, Tien-Ming Lin
  • Patent number: 8765507
    Abstract: A method for manufacturing a Group III nitride semiconductor of the present invention includes a sputtering step of forming a single-crystalline Group III nitride semiconductor on a substrate by a reactive sputtering method in a chamber in which a substrate and a Ga element-containing target are disposed, wherein said sputtering step includes respective substeps of: a first sputtering step of performing a film formation of the Group III nitride semiconductor while setting the temperature of the substrate to a temperature T1; and a second sputtering step of continuing the film formation of the Group III nitride semiconductor while lowering the temperature of the substrate to a temperature T2 which is lower than the temperature T1.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: July 1, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yasunori Yokoyama, Hisayuki Miki
  • Publication number: 20140179088
    Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.
    Type: Application
    Filed: May 20, 2013
    Publication date: June 26, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung-Bum BAE, Sung Bock Kim, Jae Kyoung Mun, Eun Soo Nam