Abstract: A relaxed InGaN template is formed by growing a GaN or InGaN nucleation layer at low temperatures on a conventional base layer (e.g., sapphire). The nucleation layer is typically very rough and multi-crystalline. A single-crystal InGaN buffer layer is then grown at normal temperatures on the nucleation layer. Although not necessary, the buffer layer is typically undoped, and is usually grown at high pressures to encourage planarization and to improve surface smoothness. A subsequent n-doped cap layer can then be grown at low pressures to form the n-contact of a photonic or electronic device. In some cases, a wetting layer—typically low temperature AlN—is grown prior to the nucleation layer. Other templates, such as AlGaN on Si or SiC, are also produced using the method of the present invention.

Abstract: An imaging system is presented for imaging objects within a field of view of the system. The imaging system comprises an imaging lens arrangement, a light detector unit at a certain distance from the imaging lens arrangement, and a control unit connectable to the output of the detection unit. The imaging lens arrangement comprises an imaging lens and an optical element located in the vicinity of the lens aperture, said optical element introducing aperture coding by an array of regions differently affecting a phase of light incident thereon which are randomly distributed within the lens aperture, thereby generating an axially-dependent randomized phase distribution in the Optical Transfer Function (OTF) of the imaging system resulting in an extended depth of focus of the imaging system. The control unit is configured to decode the sampled output of the detection unit by using the random aperture coding to thereby extract 3D information of the objects in the field of view of the light detector unit.

Abstract: In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.

Abstract: In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming disposable dielectric stack overlying a substrate. The method also includes forming the trench regions adjacent to the disposable dielectric stack. After the insulated gate electrodes are formed, the method includes removing the disposable dielectric stack, and then forming spacers adjacent the insulated gate electrodes. The method further includes using the spacers to form recessed regions in the insulated gate electrodes and the substrate, and then forming enhancement regions in the first and second recessed regions.

Abstract: Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. Oxygen-doped {20-21}, {1-101}, {1-100}, {11-20} or {20-22} surface n-type gallium nitride crystals are obtained.

Abstract: Example methods and apparatus for Antimonide-based backward diode millimeter-wave detectors are disclosed. A disclosed example backward diode includes a cathode layer adjacent to a first side of a non-uniform doping profile, and an Antimonide tunnel barrier layer adjacent to a second side of the spacer layer.

Abstract: A method for making high purity GeS and related compounds such as Germanium Silicon Sulfide (GeSiS); Copper Sulfide (CuS); Silicon Sulfide (SiS); Zinc Sulfide (ZnS) and Iron Sulfide (FeS) at low temperatures and pressures in a Chemical Vapor Deposition (CVD) process for solid electrolyte memory elements and other applications. Disclosed is a method of generating a proper chemical and energy environment for the formation of GeS and related compounds on a specific surface. The produced films have utility in memory and other devices. The technology offers cost savings and the advantage of low temperature film creation through the use of plasma assisted deposition—increasing its compatibility for use not only on silicon (or ceramic or glass) non metal substrates as well as polymer or thin metal foil substrates which would be damaged by higher temperature processes.

Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.

Abstract: Aspects of the invention include methods for depositing silicon on a substrate. In certain embodiments, the methods include exposing a substrate containing silicon to a halogenated silane in a manner sufficient to deposit the silicon on the substrate. In certain embodiments, the method includes providing a substrate, one or more sources of gas, and a reaction vessel that is in fluid communication with the substrate and the one or more sources of gas. In certain embodiments, the substrate is a low or metallurgical grade silicon which may be subjected to a purification process. In certain embodiments, the reaction vessel is a particle bed reaction vessel that includes a moving bed, such as a fluidized bed which contains silicon and the gas includes a halide.

Abstract: A method of manufacturing a nitride semiconductor structure includes disposing a semiconductor substrate in a molecular beam epitaxy reactor; growing a wetting layer comprising AlxInyGa(1?(x+y))As(0?x+y?1) or AlxInyGa(1?(x+y))P(0?x+y?1) on the substrate; in-situ annealing the wetting layer; growing a first AlGaInN layer on the wetting layer using plasma activated nitrogen as the source of nitrogen with an additional flux of phosphorous or arsenic; and growing a second AlGaInN layer on the first AlGaInN layer using ammonia as a source of nitrogen.

Abstract: A method includes forming elongate structures (5) on a first substrate (3), such that the material composition of each elongate structure (7) varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices (1, 2) are then defined in the elongate structures. Alternatively, the first and second physically different sections may be defined in the elongate structures after they have been fabricated. The elongate structures may be encapsulated and transferred to a second substrate (7). The invention provides an improved method for the formation of a circuit structure that requires first and second physically different devices (1,2) to be provided on a common substrate. In particular, only one transfer step is necessary.

Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

Abstract: A method for the production of a contact structure of a solar cell allows p-contacts and n-contacts to be produced simultaneously.

Abstract: Embodiments described herein generally relate to methods for forming Group III-V materials by metal-organic chemical vapor deposition (MOCVD) processes and/or hydride vapor phase epitaxial (HVPE) processes. In one embodiment, deposition of a group III1-N layer on a substrate is performed in a first chamber, deposition of a group III2-N layer on the substrate is performed in a second chamber, and deposition of a group III3-N layer on the substrate is performed in a chamber different from the chamber where the group III2-N layer is deposited. Between the group III2-N layer deposition and the group III3-N layer deposition, one or more surface treatment processes are performed on the substrate to reduce non-radiative recombination at the interface and improve overall electroluminescence of the produced structure.

Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

Abstract: Methods for formation of epitaxial layers containing silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the epitaxial layer involves exposing a substrate in a process chamber to deposition gases including two or more silicon source such as silane and a higher order silane. Embodiments include flowing dopant source such as a phosphorus dopant, during formation of the epitaxial layer, and continuing the deposition with the silicon source gas without the phosphorus dopant.

Abstract: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including doped epitaxial layers (e.g., P-doped silicon carbide epitaxial layers), by supplying sources of silicon and carbon with sequential emphasis. In some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source and a dopant, and purging other gaseous materials. In some embodiments, the presence of the silicon source can be independent of the presence of the carbon source and/or the dopant.

Abstract: A complementary metal-oxide-semiconductor (CMOS) optical sensor structure includes a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.

Abstract: A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.

Abstract: A solar cell having an improved structure of rear surface includes a p-type doped region, a dense metal layer, a loose metal layer, at least one bus bar opening, and solderable material on or within the bus bar opening. The solderable material contacts with the dense aluminum layer. The improved structure in rear surface increases the light converting efficiency, and provides a good adhesion between copper ribbon and solar cell layer thereby providing cost advantages and reducing the complexity in manufacturing. A solar module and solar system composed of such solar cell are also disclosed.

Abstract: The invention relates to a method for fabricating a semiconductor substrate by providing a silicon on insulator type substrate that includes a base, an insulating layer and a first semiconductor layer, doping the first semiconductor layer to thereby obtain a modified first semiconductor layer, and providing a second semiconductor layer with a different dopant concentration than the modified first semiconductor layer over or on the modified first semiconductor layer. With this method, an improved dopant concentration profile can be achieved through the various layers which makes the substrates in particular more suitable for various optoelectronic applications.

Abstract: An apparatus and process for plasma enhanced chemical vapor deposition with an inductively coupled plasma with ion densities above 1010 cm?3 and energies below 20 eV at the substrate enables epitaxial deposition of group IV and compound semiconductor layers at high rates and low substrate temperatures. The epitaxial reactor allows for in-situ plasma cleaning by chlorine and fluorine containing gaseous species.

Abstract: Carbon-containing sp3-bonded solid refractory nanocrystalline particles that are each sized no larger than about 100 nanometers have a metal of choice disposed thereabout. A variable potential junction is formed between the metallic coatings and the particles that enables carrier entropy to be efficiently transported from the variable potential junction to the coating.

Abstract: A method of forming a doped Group IBIIIAVIA absorber layer for solar cells by reacting a partially reacted precursor layer with a dopant structure. The precursor layer including Group IB, Group IIIA and Group VIA materials such as Cu, Ga, In and Se are deposited on a base and partially reacted. After the dopant structure is formed on the partially reacted precursor layer, the dopant structure and partially reacted precursor layer is fully reacted. The dopant structure includes a dopant material such as Na.

Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.

Abstract: A method of manufacturing a solar cell is provided. One surface of a semiconductor substrate is doped with a n-type dopant. The substrate is then subjected to a thermal oxidation process to form an oxide layer on one or both surfaces of the substrate. The thermal process also diffuses the dopant into the substrate, smoothing the concentration profile. The smoothed concentration gradient enables the oxide layer to act as a passivating layer. Anti-reflective coatings may be applied over the oxide layers, and a reflective layer may be applied on the surface opposite the doped surface to complete the solar cell.

Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.

Abstract: A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.

Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.

Abstract: A hybrid beam deposition (HBD) system and methods according to the present invention utilizes a unique combination of pulsed laser deposition (PLD) technique and equipment with equipment and techniques that provide a radical oxygen rf-plasma stream to effectively increase the flux density of available reactive oxygen at a deposition substrate for the effective synthesis of metal oxide thin films. The HBD system and methods of the present invention further integrate molecular beam epitaxy (MBE) and/or chemical vapor deposition (CVD) techniques and equipment in combination with the PLD equipment and technique and the radical oxygen rf-plasma stream to provide elemental source materials for the synthesis of undoped and/or doped metal oxide thin films as well as the synthesis of undoped and/or doped metal-based oxide alloy thin films.

Abstract: The structure presented herein provides a base structure for semiconductor devices, in particular for III-V semiconductor devices or for a combination of III-V and Group IV semiconductor devices. The fabrication method for a base substrate comprises a buffer layer, a nucleation layer, a Group IV substrate and possibly a dopant layer. There are, in a general aspect, two growth steps: firstly the growth of a lattice-matched III-V material on a Group IV substrate, followed by secondly the growth of a lattice-mismatched III-V layer. The first layer, called the nucleation layer, is lattice-matched or closely lattice-matched to the Group IV substrate while the following layer, the buffer layer, deposited on top of the nucleation layer, is lattice-mismatched to the nucleation layer. The nucleation layer can further be used as a dopant source to the Group IV substrate, creating a p-n junction in the substrate through diffusion. Alternatively a separate dopant layer may be introduced.

Abstract: A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopant into a first part of the first silicon region, the first part of the first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon region defined by the first mask and the second silicon region. A device comprises a semiconductor layer (6); a first doped region (5) within the semiconductor layer; a second doped region (7) within the first doped region (5); and a silicon layer (9) disposed over a part of the semiconductor layer; wherein the silicon layer is disposed over a part of the first doped region (5) but not over the second doped region (7).

Abstract: A heterojunction is provided for spin electronics applications. The heterojunction includes an n-type silicon semiconductor and a hydrogenated diamond-like carbon film deposited on the n-type silicon semiconductor. The hydrogenated diamond-like carbon film is doped with chromium. The concentration of the chromium dopant in the chromium doped diamond-like carbon film may be configured such that the heterojunction has an increase in forward bias current ranging from about 50% to about 150% in a small magnetic field at about room temperature. The heterojunction has spin electronics properties at about room temperature.

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor that may prevent a photoresist pattern from remaining on gates by forming a floating diffusion area faster than the gates. According to embodiments, since the gates may not be influenced by an ion implantation process, current characteristics and operation reliability may be enhanced. According to embodiments, the method may include forming dummy ion implantation mask patterns for forming a floating diffusion area over an epitaxial layer and forming an ion implantation mask pattern over the epitaxial layer and at least a portion of the dummy ion implantation mask patterns, so as to form the floating diffusion area by performing an ion implantation process.

Abstract: The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

Abstract: A process for realizing TFT devices on a substrate comprises the steps of: forming on the substrate, in cascade, an amorphous silicon layer and a heavily doped amorphous silicon layer, forming a photolithographic mask on the heavily doped amorphous silicon layer provided with an opening, removing the heavily doped amorphous silicon layer through the opening for realizing opposite portions of the heavily doped amorphous silicon layer whose cross dimensions decrease as long as they depart from the amorphous silicon layer, removing the photolithographic mask, carrying out a diffusion and activation step of the dopant contained in the portions of the heavily doped amorphous silicon layer inside the amorphous silicon layer, for realizing source/drain regions of said TFT device.

Abstract: Germanium on insulator (GOI) semiconductor substrates are generally described. In one example, a GOI semiconductor substrate comprises a semiconductor substrate comprising an insulative surface region wherein a concentration of dopant in the insulative surface region is less than a concentration of dopant in the semiconductor substrate outside of the insulative surface region and a thin film of germanium coupled to the insulative surface region of the semiconductor substrate wherein the thin film of germanium and the insulative surface region are simultaneously formed by oxidation anneal of a thin film of silicon germanium (Si1-xGex) deposited to the semiconductor substrate wherein x is a value between 0 and 1 that provides a relative amount of silicon and germanium in the thin film of Si1-xGex.

Abstract: A method of growing a p-type nitride semiconductor material by molecular beam epitaxy (MBE) uses bis(cyclopentadienyl)magnesium (Cp2Mg) as the source of magnesium dopant atoms. Ammonia gas is used as the nitrogen precursor for the MBE growth process. To grow p-type GaN, for example, by the method of the invention, gallium, ammonia and Cp2Mg are supplied to an MBE growth chamber; to grow p-type AlGaN, aluminum is additionally supplied to the growth chamber. The growth process of the invention produces a p-type carrier concentration, as measured by room temperature Hall effect measurements, of up to 2 1017 cm?3, without the need for any post-growth step of activating the dopant atoms.

Abstract: A vertical CVD apparatus is arranged to process a plurality of target substrates all together to form a silicon germanium film. The apparatus includes a reaction container having a process field configured to accommodate the target substrates, and a common supply system configured to supply a mixture gas into the process field. The mixture gas includes a first process gas of a silane family and a second process gas of a germane family. The common supply system includes a plurality of supply ports disposed at different heights.

Abstract: An imaging system is presented for imaging objects within a field of view of the system. The imaging system comprises an imaging lens arrangement, a light detector unit at a certain distance from the imaging lens arrangement, and a control unit connectable to the output of the detection unit. The imaging lens arrangement comprises an imaging lens and an optical element located in the vicinity of the lens aperture, said optical element introducing aperture coding by an array of regions differently affecting a phase of light incident thereon which are randomly distributed within the lens aperture, thereby generating an axially-dependent randomized phase distribution in the Optical Transfer Function (OTF) of the imaging system resulting in an extended depth of focus of the imaging system. The control unit is configured to decode the sampled output of the detection unit by using the random aperture coding to thereby extract 3D information of the objects in the field of view of the light detector unit.

Abstract: The invention relates to the manufacture of an epitaxial layer, with the following steps: providing a semiconductor substrate; providing a Si—Ge layer on the semiconductor substrate, having a first depth; —providing the semiconductor substrate with a doped layer with an n-type dopant material and having a second depth substantially greater than said first depth; performing an oxidation step to form a silicon dioxide layer such that Ge atoms and n-type atoms are pushed into the semiconductor substrate by the silicon dioxide layer at the silicon dioxide/silicon interface, wherein the n-type atoms are pushed deeper into the semiconductor substrate than the Ge atoms, resulting in a top layer with a reduced concentration of n-type atoms; removing the silicon dioxide layer; growing an epitaxial layer of silicon on the semiconductor substrate with a reduced outdiffusion or autodoping.

Abstract: Methods for forming carbon silicon alloy (CSA) and structures thereof are disclosed. The method provides improvement in substitutionality and deposition rate of carbon in epitaxially grown carbon silicon alloy layers (i.e., substituted carbon in Si lattice). In one embodiment of the disclosed method, a carbon silicon alloy layer is epitaxially grown on a substrate at an intermediate temperature with a silicon precursor, a carbon (C) precursor in the presence of an etchant and a trace amount of germanium material (e.g., germane (GeH4)). The intermediate temperature increases the percentage of substitutional carbon in epitaxially grown CSA layer and avoids any tendency for silicon carbide to form. The presence of the trace amount of germanium material, of approximately less than 1% to approximately 5%, in the resulting epitaxial layer, has an effect of stabilizing and enhancing deposition/growth rate without compromising the tensile stress of CSA layer formed thereby.

Abstract: Aspects of the invention include methods for depositing silicon on a substrate. In certain embodiments, the methods include exposing a substrate containing silicon to a halogenated silane in a manner sufficient to deposit the silicon on the substrate. In certain embodiments, the method includes providing a substrate, one or more sources of gas, and a reaction vessel that is in fluid communication with the substrate and the one or more sources of gas. In certain embodiments, the substrate is a low or metallurgical grade silicon which may be subjected to a purification process. In certain embodiments, the reaction vessel is a particle bed reaction vessel that includes a moving bed, such as a fluidized bed which contains silicon and the gas includes a halide.

Abstract: A semiconductor device with a semiconductor body and method for its production is provided. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.

Abstract: The invention proposes a method for producing a semiconductor component, such as a thin-layer solar cell. The method involves providing a doped semiconductor carrier substrate (1), producing a separating layer (2), for example a porous layer, on one surface of the semiconductor carrier substrate, depositing a doped semiconductor layer (3) over the separating layer and detaching the deposited semiconductor layer from the semiconductor carrier substrate. In line with the invention, process parameters such as the process temperature and time are chosen during the manufacturing process such that dopants can diffuse from the separation layer into the deposited semiconductor layer in order to form a specifically doped surface area (4). Specific use of solid-state diffusion makes it possible to simplify the manufacturing process over conventional fabrication methods in this manner.

Abstract: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench (14), which reaches down to the insulator (11) and surrounds a region (13?) of the monocrystalline silicon (13) of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region (17?) on a portion of the monocrystalline silicon region, forming a doped silicon layer region (18) on the insulating layer region (17?), and forming an insulating outside sidewall spacer (61) on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region (13?), the insulating layer region (17?), and the doped silicon layer region (18) constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

Abstract: A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.

Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal.