Plasma (e.g., Glow Discharge, Etc.) Patents (Class 438/513)
  • Patent number: 10395937
    Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Dian-Hau Chen, Han-Ting Tsai, Tsung-Lin Lee, Chia-Cheng Ho, Ming-Shiang Lin
  • Patent number: 10325818
    Abstract: The present disclosure provides a method for fabricating a fin field-effect transistor (fin-FET), including: providing a substrate having a plurality of discrete fin structures thereon; forming a chemical oxide layer on at least a sidewall of a fin structure; forming a doped layer containing doping ions on the chemical oxide layer; and annealing the doped layer such that the doping ions diffuse into the fin structure to form a doped region.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 18, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10276384
    Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken, Mahmoud Khojasteh, George G. Totir, Hongwen Yan, Masahiro Yamazaki
  • Patent number: 9685304
    Abstract: An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B2F4. Synthesis methods for such compounds, and ion implantation methods using such compounds, are described, as well as storage and dispensing vessels in which the isotopically-enriched, boron-containing compound is advantageously contained for subsequent dispensing use.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: June 20, 2017
    Assignee: Entegris, Inc.
    Inventors: Robert Kaim, Joseph D. Sweeney, Oleg Byl, Sharad N. Yedave, Edward E. Jones, Peng Zou, Ying Tang, Barry Lewis Chambers, Richard S. Ray
  • Patent number: 9385219
    Abstract: Methods for forming fin structures with desired materials formed on different locations of the fin structure using a selective deposition process for fin field effect transistors (FinFETs) are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes depositing a first material on a substrate having a three-dimensional (3D) structure formed thereon while performing an implantation process to dope a first region of the 3D structure. The first material may be removed and a second material may be deposited on the 3D structure. The second material may selectively grow on a second region of the 3D structure.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 5, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ellie Y. Yieh, Srinivas D. Nemani, Ludovic Godet, Yin Fan, Tristan Ma
  • Patent number: 9373509
    Abstract: A method to implant dopants onto fin-type field-effect-transistor (FINFET) fin surfaces with uniform concentration and depth levels of the dopants and the resulting device are disclosed. Embodiments include a method for pulsing a dopant perpendicular to an upper surface of a substrate, forming an implantation beam pulse; applying an electric or a magnetic field to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse; and implanting the dopant onto a sidewall surface of a target FINFET fin on the upper surface of the substrate via the curvilinear trajectory path of the implantation beam pulse.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: June 21, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ralf Richter, Stefan Flachowsky, Peter Javorka, Jan Hoentschel
  • Patent number: 9343291
    Abstract: Techniques include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric. Such techniques include using a hydrogen-based plasma formed using a slotted-plane antenna plasma processing system. Such a plasma treatment can be executed with substrate temperatures less than 380 degrees Celsius, and even down to about 200 degrees Celsius or below.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: May 17, 2016
    Assignees: Tokyo Electron Limited, The Board of Trustees of the Leland Stanford Junior University
    Inventors: Toru Ito, Paul C. McIntyre
  • Patent number: 9153441
    Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: October 6, 2015
    Assignee: ASM International, N.V.
    Inventors: Noboru Takamure, Atsuki Fukazawa, Hideaki Fukuda, Antti Niskanen, Suvi Haukka, Ryu Nakano, Kunitoshi Namba
  • Patent number: 9099495
    Abstract: The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a semiconductor material. A first implantation process is performed to a region of the fin structure to form a fin seed within the region of the fin structure. The fin seed has a crystal structure. The first implantation process is performed at a process temperature above about 100 degrees Celsius. A second implantation process is performed to the region of the fin structure to cause the region of the fin structure outside the fin seed to become amorphous. The second implantation process is performed at a process temperature below about 0 degrees Celsius. Thereafter, an annealing process is performed to recrystallize the region of the fin structure via the fin seed.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: August 4, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Feng Nieh, Hsin-Wei Wu, Tsun-Jen Chan, Yu-Chang Lin
  • Patent number: 9054128
    Abstract: A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: June 9, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Jae-Geun Oh, Young-Ho Lee, Mi-Ri Lee, Seung-Beom Baek
  • Patent number: 9048181
    Abstract: A method of making a semiconductor device includes forming a fin structure over a substrate. The method further includes performing a plasma doping process on the fin structure. Performing the plasma doping process includes implanting plasma ions into the fin structures at a plurality of implant angles, and the plurality of implant angles has an angular distribution and at least one highest angle frequency value.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: June 2, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chii-Ming Wu, Yu Lien Huang, Chun Hsiung Tsai
  • Publication number: 20150132929
    Abstract: Provided is a method for injecting a dopant into a substrate to be processed. A method in one embodiment of the present invention includes: (a) a step for preparing, in a processing container, a substrate to be processed; and (b) a step for injecting a dopant into the substrate by supplying a doping gas containing AsH3, an inert gas, and H2 gas to the inside of the processing container, and applying plasma excitation energy to the inside of the processing container. In the step of injecting the dopant, the ratio of hydrogen partial pressure to the gas total pressure in the processing container is set within the range of 0.0015-0.003.
    Type: Application
    Filed: April 5, 2013
    Publication date: May 14, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Horigome, Hirokazu Ueda, Masahiro Oka, Masahiro Yamazaki, Takenao Nemoto
  • Patent number: 9029249
    Abstract: Disclosed is a plasma doping apparatus provided with a plasma generating mechanism. The plasma generating mechanism includes a microwave generator that generates microwave for plasma excitation, a dielectric window that transmits the microwave generated by the microwave generator into a processing container, and a radial line slot antenna formed with a plurality of slots. The radial line slot antenna radiates the microwave to the dielectric window. A control unit controls the plasma doping apparatus such that a doping gas and a gas for plasma excitation are supplied into the processing container by a gas supply unit in a state where the substrate is placed on a holding unit, and then plasma is generated by the plasma generating mechanism to perform doping on the substrate such that the concentration of the dopant implanted into the substrate is less than 1×1013 atoms/cm2.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hirokazu Ueda, Masahiro Oka, Masahiro Horigome, Yuuki Kobayashi
  • Publication number: 20150126022
    Abstract: According to an example embodiment, a method includes forming a nitrogen vacancy surface layer by treating a surface of an n-type nitride semiconductor with inert gas plasma, and forming an oxygen-added nitride film by treating a surface of the nitrogen vacancy surface layer with oxygen-containing gas plasma, and forming an electrode on the oxygen-added nitride film. The nitrogen vacancy surface layer lacks a nitrogen element.
    Type: Application
    Filed: July 21, 2014
    Publication date: May 7, 2015
    Inventors: Tae Hun KIM, Sung Joon KIM, Young Kyu SUNG, Wan Ho LEE, Tae Sung JANG, Tae Young PARK, Wan Tae LIM
  • Patent number: 9018050
    Abstract: A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 28, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Wen Huang
  • Patent number: 9006802
    Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gin-Chen Huang, Tsai-Fu Hsiao, Ching-Hong Jiang, Neng-Kuo Chen, Hongfa Luan, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8993422
    Abstract: In accordance with an embodiment of the present invention, a process tool includes a chuck configured to hold a substrate. The chuck is disposed in a chamber. The process tool further includes a shielding unit with a central opening. The shielding unit is disposed in the chamber over the chuck.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventor: Manfred Engelhardt
  • Patent number: 8989888
    Abstract: A method for automatically detecting fault conditions and classifying the fault conditions during substrate processing is provided. The method includes collecting processing data by a set of sensors during the substrate processing. The method also includes sending the processing data to a fault detection/classification component. The method further includes performing data manipulation of the processing data by the fault detection/classification component. The method yet also includes executing a comparison between the processing data and a plurality of fault models stored within a fault library. Each fault model of the plurality of fault models represents a set of data characterizing a specific fault condition. Each fault model includes at least a fault signature, a fault boundary, and a set of principal component analysis (PCA) parameters.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: March 24, 2015
    Assignee: Lam Research Corporation
    Inventors: Gunsu Yun, Vijayakumar C. Venugopal
  • Patent number: 8975603
    Abstract: Systems and methods for plasma doping microfeature workpieces are disclosed herein. In one embodiment, a method of implanting boron ions into a region of a workpiece includes generating a plasma in a chamber, selectively applying a pulsed electrical potential to the workpiece with a duty cycle of between approximately 20 percent and approximately 50 percent, and implanting an ion specie into the region of the workpiece.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Allen McTeer
  • Publication number: 20150053983
    Abstract: Systems and methods are provided for dopant activation in a semiconductor structure for fabricating semiconductor devices. For example, a substrate is provided. A semiconductor structure is formed on the substrate. Pre-amorphization implantation is performed on the semiconductor structure. Microwave radiation is applied to the semiconductor structure to activate dopants in the semiconductor structure for fabricating semiconductor devices. Microwave-radiation absorption of the semiconductor structure is increased after the pre-amorphization implantation.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHUN-HSIUNG TSAI, CHEN-FENG HSU, YI-TANG LIN, Clement HSINGJEN WANN
  • Publication number: 20150041962
    Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 12, 2015
    Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer
  • Patent number: 8946035
    Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Ming-Huan Tsai, Clement Hsingjen Wann
  • Patent number: 8940639
    Abstract: A MEMS device with movable MEMS structure and electrodes is produced by fabricating electrodes and shielding the electrodes with diamond buttons during subsequent fabrication steps, such as the etching of sacrificial oxide using vapor HF. In some embodiments, the diamond buttons are removed after the movable MEMS structure is released.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 27, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Fang Liu, Kuang L. Yang
  • Patent number: 8937004
    Abstract: A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: January 20, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Anthony Renau, Ludovic Godet, Timothy J. Miller, Joseph C. Olson, Vikram Singh, James Buonodono, Deepak A. Ramappa, Russell J. Low, Atul Gupta, Kevin M. Daniels
  • Patent number: 8937000
    Abstract: A chemical vapor deposition reactor and method. Reactive gases, such as gases including a Group III metal source and a Group V metal source, are introduced into the chamber (10) of a rotating-disc reactor and directed downwardly onto a wafer carrier (32) and substrates (40) which are maintained at an elevated substrate temperature, typically above about 400° C. and normally about 700-1100° C. to deposit a compound such as a III-V semiconductor. The gases are introduced into the reactor at an inlet temperature desirably above about 75° C. and most preferably about 100°-350° C. The walls of the reactor may be at a temperature close to the inlet temperature. Use of an elevated inlet temperature allows the use of a lower rate of rotation of the wafer carrier, a higher operating pressure, lower flow rate, or some combination of these.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: January 20, 2015
    Assignee: Veeco Instruments Inc.
    Inventors: Alex Gurary, Mikhail Belousov, Bojan Mitrovic
  • Patent number: 8937003
    Abstract: A technique for ion implanting a target is disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for ion implanting a target, the method comprising: providing a predetermined amount of processing gas in an arc chamber of an ion source, the processing gas containing implant species and implant species carrier, where the implant species carrier may be one of O and H; providing a predetermined amount of dilutant into the arc chamber, wherein the dilutant may comprise a noble species containing material; and ionizing the processing gas and the dilutant.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: January 20, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Alexander S. Perel, Craig R. Chaney, Wayne D. LeBlanc, Robert Lindberg, Antonella Cucchetti, Neil J. Bassom, David Sporleder, James Young
  • Patent number: 8921214
    Abstract: A method for fabricating a variable resistance memory device includes forming an oxygen-deficient first metal oxide layer over a first electrode, forming an oxygen-rich second metal oxide layer over the first metal oxide layer, treating the first and second metal oxide layers with hydrogen-containing plasma, forming an oxygen-rich third metal oxide layer, and forming a second electrode over the third metal oxide layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Kee-Jeung Lee, Beom-Yong Kim, Wan-Gee Kim, Woo-Young Park
  • Publication number: 20140356984
    Abstract: A method of doping a non-planar surface or a surface of a substrate subject to poor view factors is provided. The processing chamber comprises a window, walls, and a bottom of the processing chamber with oxygen-containing material, the processing chamber configured to supply oxygen radicals as an additive to doping materials. One or more quartz pieces are placed inside the processing chamber, where a magnet proximate to the processing chamber is configured to create a local magnetron plasma inside the processing chamber. Process gas containing an inert gas, sublimated doping materials, and optionally oxygen gas is flowed into the processing chamber; energy is applied to the process gas, generating a doping plasma used to expose a portion of the substrate surface while controlling operating variables to achieve target uniformity of dopant concentration, sheet resistance, degree of dopant clustering, and erosion of features on the substrate.
    Type: Application
    Filed: November 8, 2013
    Publication date: December 4, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Peter L. G. Ventzek, Yuuki Kobayashi
  • Publication number: 20140357068
    Abstract: A plasma doping apparatus which performs doping by injecting dopants into a substrate to be processed. The apparatus includes a processing container, a gas supplying unit configured to supply a doping gas and an inert gas for plasma excitation into the processing container, a holding table configured to hold the substrate to be processed, a plasma generating mechanism configured to generate plasma in the processing container using a microwave, a pressure adjusting mechanism configured to adjust a pressure in the processing container, and a control unit configured to control the plasma doping apparatus. The control unit controls the pressure adjusting mechanism to set the pressure in the processing container to be equal to or more than 100 mTorr and less than 500 mTorr such that a plasma processing is performed on the substrate to be processed using the plasma generated by the plasma generating mechanism.
    Type: Application
    Filed: October 19, 2012
    Publication date: December 4, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Horigome, Hirokazu Ueda, Masahiro Oka, Yuuki Kobayashi, Takayuki Karakawa
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Publication number: 20140342537
    Abstract: A method of making a semiconductor device includes forming a fin structure over a substrate. The method further includes performing a plasma doping process on the fin structure. Performing the plasma doping process includes implanting plasma ions into the fin structures at a plurality of implant angles, and the plurality of implant angles has an angular distribution and at least one highest angle frequency value.
    Type: Application
    Filed: May 27, 2014
    Publication date: November 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chii-Ming WU, Yu Lien HUANG, Chun Hsiung TSAI
  • Patent number: 8889534
    Abstract: A method of doping a non-planar surface or a surface of a substrate subject to poor view factors is provided. The processing chamber comprises a window, walls, and a bottom of the processing chamber with oxygen-containing material, the processing chamber configured to supply oxygen radicals as an additive to doping materials. One or more quartz pieces are placed inside the processing chamber, where a magnet proximate to the processing chamber is configured to create a local magnetron plasma inside the processing chamber. Process gas containing an inert gas, sublimated doping materials, and optionally oxygen gas is flowed into the processing chamber; energy is applied to the process gas, generating a doping plasma used to expose a portion of the substrate surface while controlling operating variables to achieve target uniformity of dopant concentration, sheet resistance, degree of dopant clustering, and erosion of features on the substrate.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: November 18, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Peter L. G. Ventzek, Yuuki Kobayashi
  • Patent number: 8871618
    Abstract: An in-situ fabrication method for a silicon solar cell includes the following steps: pretreating a silicon chip; placing the pretreated silicon chip in an implantation chamber of a plasma immersion ion implantation machine; completing the preparation of black silicon via a plasma immersion ion implantation process; making a PN junction and forming a passivation layer on the black silicon; after making the PN junction and forming the passivation layer, removing the black silicon from the plasma immersion ion implantation machine; preparing a metal back electrode on the back of the black silicon; preparing a metal grid on the passivation layer; obtaining a solar cell after encapsulation. Said method enables black silicon preparation, PN junction preparation, and passivation layer formation in-situ, greatly reducing the amount of equipment needed for the preparation of solar cells and the preparation cost. In addition, the method is simple and easy to control.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: October 28, 2014
    Assignee: The Institute of Microelectronics of Chinese Academy of Sciences
    Inventors: Yang Xia, Bangwu Liu, Chaobo Li, Jie Liu, Minggang Wang, Yongtao Li
  • Patent number: 8859331
    Abstract: Methods of forming an oxide material layer are provided. The method includes mixing a precursor material with a peroxide material to form a precursor solution, coating the precursor solution on a substrate, and baking the coated precursor solution.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 14, 2014
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyun Jae Kim, Dong Lim Kim, Joohye Jung, You Seung Rim
  • Publication number: 20140302666
    Abstract: A method and apparatus for doping a surface of a substrate with a dopant, with the dopant being for example phosphine or arsine. The doping is performed with a plasma formed primarily of an inert gas such as helium or argon, with a low concentration of the dopant. To provide conformal doping, preferably to form a monolayer of the dopant, the gas flow introduction location is switched during the doping process, with the gas mixture primarily introduced through a center top port in the process chamber during a first period of time followed by introduction of the gas mixture primarily through peripheral or edge injection ports for a second period of time, with the switching continuing in an alternating fashion as the plasma process.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 9, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Peter VENTZEK, Takenao NEMOTO, Hirokazu UEDA, Yuuki KOBAYASHI, Masahiro HORIGOME
  • Patent number: 8855949
    Abstract: An object is to provide a plasma processing device capable of properly monitoring a state of plasma discharge and detecting a precursor to abnormal discharge, and a method of monitoring the state of discharge in the plasma processing device.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: October 7, 2014
    Assignee: Panasonic Corporation
    Inventor: Masaru Nonomura
  • Patent number: 8853090
    Abstract: A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 ?m and a depth of at least 5 ?m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 7, 2014
    Assignee: IPEnval Consultant Inc.
    Inventors: Chao-Yuan Huang, Yueh-Feng Ho, Ming-Sheng Yang, Hwi-Huang Chen
  • Patent number: 8846482
    Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Avogy, Inc.
    Inventors: David P. Bour, Richard J. Brown, Isik C. Kizilyalli, Thomas R. Prunty, Linda Romano, Andrew P. Edwards, Hui Nie, Mahdan Raj
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Publication number: 20140256121
    Abstract: An apparatus for hydrogen and helium implantation is disclosed. The apparatus includes a plasma source system to generate helium ions and hydrogen molecular ions comprising H3+ ions. The apparatus further includes a substrate chamber adjacent the plasma source system and in communication with the plasma source system via one or more apertures, an extraction system to extract the hydrogen molecular ions and helium ions from the plasma source system, and an acceleration system to accelerate extracted helium and hydrogen molecular ions to a predetermined energy and direct the extracted helium ions and hydrogen molecular ions to a substrate.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventor: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
  • Patent number: 8830078
    Abstract: A method of manufacturing a bearing device component is provided. The bearing device includes a shaft and a sleeve that surrounds the shaft, and at least either one of the shaft and the sleeve is referred to as a work. The method includes: a process of forming a coating of an anti-sticking-lube polymer on the work; a process of applying a photoluminescence material to a range overlapping a range where the coating of the anti-sticking-lube polymer is formed; and a condition detecting process of causing the photoluminescence material to emit light by causing the work to be irradiated with excitation light that excites the photoluminescence material, and detecting an applied condition of the photoluminescence material based on the light emission of the photoluminescence material, thereby detecting a condition of the coating of the anti-sticking-lube polymer.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: September 9, 2014
    Assignee: Samsung Electro-Mechanics Japan Advanced Technology Co., Ltd.
    Inventors: Chenglin Chen, Kazuhiro Matsuo
  • Patent number: 8828854
    Abstract: A method of introducing dopants into a semiconductor wafer includes implanting the dopants into a region below a surface of the semiconductor wafer using an ion beam to form a first implanted layer. The dopants when activated causing a conductivity of the implanted layer to be either of N-type or P-type. The first implanted layer is characterized by a peak dopant concentration at a first depth below the surface of the semiconductor wafer. The method also includes removing a layer from the semiconductor wafer surface, wherein said layer includes a portion of said dopants.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: September 9, 2014
    Inventor: Tzu-Yin Chiu
  • Publication number: 20140248759
    Abstract: A method of preventing toxic gas formation after an implantation process is disclosed. Certain dopants, when implanted into films disposed on a substrate, may react when exposed to moisture to form a toxic gas and/or a flammable gas. By in-situ exposing the doped film to an oxygen containing compound, dopant that is shallowly implanted into the layer stack reacts to form a dopant oxide, thereby reducing potential toxic gas and/or flammable gas formation. Alternatively, a capping layer may be formed in-situ over the implanted film to reduce the potential generation of toxic gas and/or flammable gas.
    Type: Application
    Filed: May 12, 2014
    Publication date: September 4, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Majeed A. FOAD, Manoj VELLAIKAL, Kartik SANTHANAM
  • Patent number: 8815719
    Abstract: A method and apparatus for implanting a semiconductor substrate with boron clusters. A substrate is implanted with octadecaborane by plasma immersion or ion beam implantation. The substrate surface is then annealed to completely dissociate and activate the boron clusters. The annealing may take place by melting the implanted regions or by a sub-melt annealing process.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: August 26, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jiping Li, Aaron Muir Hunter, Bruce E. Adams, Theodore Moffitt, Stephen Moffatt
  • Patent number: 8809168
    Abstract: Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8809132
    Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8796122
    Abstract: A method of fabricating a display device is provided. The method includes providing a substrate having a pixel region and a circuit region located at the periphery of the pixel region. A first semiconductor layer and a second semiconductor layer are formed on the pixel region and on the circuit region, respectively. The first semiconductor layer may be selectively surface treated to increase the density of lattice defects in a surface of the first semiconductor layer.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 5, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eui-Hoon Hwang, Deuk-Jong Kim
  • Patent number: 8785286
    Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
  • Patent number: 8779395
    Abstract: An ion implantation system for improving performance and extending lifetime of an ion source is disclosed whereby the selection, delivery, optimization and control of the flow rate of a co-gas into an ion source chamber is automatically controlled.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: July 15, 2014
    Assignee: Axcelis Technologies, Inc.
    Inventors: Neil K. Colvin, Tseh-Jen Hsieh
  • Patent number: 8772130
    Abstract: In order to keep the crystallinity of the semiconductor thin film layer high, a temperature of a semiconductor substrate during hydrogen ion addition treatment is suppressed to lower than or equal to 200° C. In addition, the semiconductor substrate is subjected to plasma treatment while the semiconductor substrate is kept at a temperature of higher than or equal to 100° C. and lower than or equal to 400° C. after the hydrogen ion addition treatment, whereby Si—H bonds which have low contribution to separation of the semiconductor thin film layer can be reduced while Si—H bonds which have high contribution to separation of the semiconductor thin film layer, which are generated by the hydrogen ion addition treatment, are kept.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroshi Ohki