Plasma (e.g., Glow Discharge, Etc.) Patents (Class 438/513)
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Patent number: 8586459Abstract: An ion implantation device and a method of manufacturing a semiconductor device is described, wherein ionized phosphorus-containing molecular clusters are implanted to form N-type transistor structures. The clusters are implanted to provide N-type doping for Source and Drain structures and Pocket or Halo formation, and for counter-doping Poly gates. These doping steps are critical to the formation of NMOS transistors. The molecular cluster ions have the chemical form AnHx+, or AnRHx+, where n and x are integers with 4<n and x?0, and A is either As or P, and R is a molecule not containing phosphorus or arsenic, which is not injurious to the implantation process.Type: GrantFiled: November 5, 2007Date of Patent: November 19, 2013Assignee: SemEquip, Inc.Inventors: Thomas N. Horsky, Erin Dyker, Brian Bernstein, Dennis Manning
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Patent number: 8586460Abstract: Methods of enabling the use of high wavelength lasers to create shallow melt junctions are disclosed. In some embodiments, the substrate may be preamorphized to change its absorption characteristics prior to the implantation of a dopant. In other embodiments, a single implant may serve to amorphize the substrate and provide dopant. Once the substrate is sufficiently amorphized, a laser melt anneal may be performed. Due to the changes in the absorption characteristics of the substrate, longer wavelength lasers may be used for the anneal, thereby reducing cost.Type: GrantFiled: September 21, 2011Date of Patent: November 19, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventor: Deepak Ramappa
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Publication number: 20130288465Abstract: Methods for filling high aspect ratio features are provided herein. In some embodiments, method of filling a high aspect ratio feature formed in a substrate includes implanting a first species using a first plasma into first surfaces of a first layer formed along the surfaces of the high aspect ratio feature to form implanted first surfaces such that a second species subsequently deposited atop the first layer has an increased mobility along the implanted first surfaces relative to the first surfaces, wherein the first layer substantially prevents the second species from diffusing completely through the first layer; and subsequently filling the high aspect ratio feature with the second species.Type: ApplicationFiled: April 12, 2013Publication date: October 31, 2013Applicant: APPLIED MATERIALS, INC.Inventors: IGOR PEIDOUS, MICHAEL G. WARD
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Publication number: 20130288466Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.Type: ApplicationFiled: June 27, 2013Publication date: October 31, 2013Inventors: Lequn Jennifer Liu, Shu Qin, Allen McTeer, Yongjun Jeff Hu
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Patent number: 8563374Abstract: Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate.Type: GrantFiled: September 16, 2011Date of Patent: October 22, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Stefan Flachowsky, Jan Hoentschel
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Patent number: 8558195Abstract: Methods and apparatus provide for: a source simultaneously producing first plasma, which includes a first species of ions, and second plasma, which includes a second, differing, species of ions; an accelerator system including an analyzer magnet, which cooperate to simultaneously: (i) accelerate the first and second plasma along an initial axis, (ii) alter a trajectory of the first species of ions from the first plasma, thereby producing at least one first ion beam along a first axis, which is transverse to the initial axis, and (iii) alter a trajectory of the second species of ions from the second plasma, thereby producing at least one second ion beam along a second axis, which is transverse to the initial axis and the first axis; and a beam processing system operating to simultaneously direct the first and second ion beams toward a semiconductor wafer such that the first and second species of ions bombard an implantation surface of the semiconductor wafer to create an exfoliation layer therein.Type: GrantFiled: November 19, 2010Date of Patent: October 15, 2013Assignee: Corning IncorporatedInventor: Sarko Cherekdjian
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Patent number: 8536658Abstract: The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.Type: GrantFiled: October 12, 2012Date of Patent: September 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chii-Ming Wu, Yu-Lien Huang, Chun Hsiung Tsai
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Patent number: 8536031Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.Type: GrantFiled: February 19, 2010Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Kuang-Jung Chen, Matthew E. Colburn, Dario L. Goldfarb, Stefan Harrer, Steven J. Holmes, Pushkara Varanasi
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Patent number: 8524584Abstract: Methods and carbon ion precursor compositions for implanting carbon ions generally includes vaporizing and ionizing a gas mixture including carbon oxide and methane gases in an ion source to create a plasma and produce carbon ions. The ionized carbon within the plasma is then extracted to form an ion beam. The ion beam is mass analyzed with a mass analyzer magnet to permit the ionized carbon to pass therethrough and implant into a workpiece.Type: GrantFiled: January 20, 2011Date of Patent: September 3, 2013Assignee: Axcelis Technologies, Inc.Inventors: William D. Lee, Daniel R. Tieger, Tseh-Jen Hsieh
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Patent number: 8501525Abstract: A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.Type: GrantFiled: June 1, 2011Date of Patent: August 6, 2013Assignee: Altis SemiconductorInventor: Faiz Dahmani
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Patent number: 8501631Abstract: A method for controlling a plasma processing system using wafer bias information derived from RF voltage information is proposed. The RF voltage is processed via an analog or digital methodology to obtain peak voltage information at least for each of the fundamental frequencies and the broadband frequency. The peak voltage information is then employed to derive the wafer bias information to serve as a feedback or control signal to hardware/software of the plasma processing system.Type: GrantFiled: December 7, 2010Date of Patent: August 6, 2013Assignee: Lam Research CorporationInventors: John C. Valcore, Jr., Henry S. Povolny
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Patent number: 8497194Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.Type: GrantFiled: November 12, 2012Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Lequn Jennifer Liu, Shu Qin, Allen McTeer, Yongjun Jeff Hu
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Patent number: 8497208Abstract: A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.Type: GrantFiled: September 16, 2010Date of Patent: July 30, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Michie Sunayama, Yoshiyuki Nakao, Noriyoshi Shimizu
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Patent number: 8497196Abstract: A method for fabricating a semiconductor device includes forming a gate electrode on a surface of a substrate via a gate insulating film, forming an insulating film on a side surface of the gate electrode, and exposing an oxygen plasma onto the surface of the substrate. An electron temperature of the oxygen plasma in a vicinity of the surface of the substrate is equal to or less than about 1.5 eV.Type: GrantFiled: October 4, 2009Date of Patent: July 30, 2013Assignee: Tokyo Electron LimitedInventor: Masaru Sasaki
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Publication number: 20130154059Abstract: A semiconductor device manufacturing method includes exciting plasma, applying RF power onto a target substrate to generate substrate bias and performing an ion implantation plural times by applying the RF power in the form of pulses.Type: ApplicationFiled: February 14, 2013Publication date: June 20, 2013Applicants: NATIONAL UNIVERSITY CORP TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITEDInventors: TOKYO ELECTRON LIMITED, NATIONAL UNIVERSITY CORP TOHOKU UNIVERSITY
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Patent number: 8461030Abstract: A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation.Type: GrantFiled: November 16, 2010Date of Patent: June 11, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Anthony Renau, Ludovic Godet, Timothy J. Miller, Joseph C. Olson, Vikram Singh, James Buonodono, Deepak A. Ramappa, Russell J. Low, Atul Gupta, Kevin M. Daniels
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Publication number: 20130137250Abstract: Methods of implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. A method of manufacturing a semiconductor device including implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. Also disclosed are a system for supplying a boron hydride precursor, and methods of forming a boron hydride precursor and methods for supplying a boron hydride precursor. In one implementation of the invention, the boron hydride precursors are generated for cluster boron implantation, for manufacturing semiconductor products such as integrated circuitry.Type: ApplicationFiled: December 26, 2012Publication date: May 30, 2013Applicant: Advanced Technology Materials, Inc.Inventor: Advanced Technology Materials, Inc.
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Publication number: 20130137249Abstract: The present invention generally relates to methods of forming substrates using remote radical hydride doping. The methods generally include remotely activating a gas and introducing activated radicals of the gas into a chamber. The activated radicals may be activated hydride radicals of a gas such as diborane (B2H6), phosphine (PH3), or arsine (AsH3) which are utilized to incorporate an element such as boron, phosphorus, or arsenic into a substrate having a surface temperature between about 400 degrees Celsius and about 1000 degrees Celsius. Alternatively, the activated radicals may be activated radicals of an inert gas. The activated radicals of the inert gas are introduced into a chamber having a dopant-containing gas, such as diborane, phosphine, or arsine, therein. The activated radicals of the inert gas activate the dopant-gas and incorporate dopants into a heated substrate located within the chamber.Type: ApplicationFiled: November 14, 2012Publication date: May 30, 2013Inventors: Christopher S. Olsen, Johanes S. Swenberg
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Publication number: 20130126892Abstract: A new composition of matter is described, amorphous GaN1-xAsx:Mg, wherein 0<x<1, and more preferably 0.1<x<0.8, which amorphous material is of low resistivity, and when formed as a thin, heavily doped film may be used as a low resistant p-type ohmic contact layer for a p-type group III-nitride layer in such applications as photovoltaic cells. The layer may be applied either as a conformal film or a patterned layer. In one embodiment, as a lightly doped but thicker layer, the amorphous GaN1-xAsx:Mg film can itself be used as an absorber layer in PV applications. Also described herein is a novel, low temperature method for the formation of the heavily doped amorphous GaN1-xAsx:Mg compositions of the invention in which the doping is achieved during film formation according to MBE methods.Type: ApplicationFiled: May 18, 2012Publication date: May 23, 2013Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Kin Man Yu, Wladyslaw Walukiewicz, Alejandro X. Levander, Sergei V. Novikov, C. Thomas Foxon
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Patent number: 8440551Abstract: A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate.Type: GrantFiled: May 11, 2012Date of Patent: May 14, 2013Assignee: ULVAC, Inc.Inventors: Kazuhiko Tonari, Tsutomu Nishihashi
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Publication number: 20130115763Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.Type: ApplicationFiled: November 2, 2012Publication date: May 9, 2013Applicant: ASM INTERNATIONAL. N.V.Inventor: ASM International. N.V.
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Publication number: 20130109162Abstract: A method for incorporating radicals of a plasma into a substrate or a material on a semiconductor substrate using a remote plasma source. In one embodiment, a method for processing doped materials on a substrate surface is provided and includes forming a doped layer on a substrate and optionally cleaning the doped layer, such as by a wet clean process. The method also includes generating an ionized nitrogen plasma in a remote plasma source, wherein the ionized nitrogen plasma has an ion concentration within a range from about 0.001% to about 0.1%, de-ionizing the ionized nitrogen plasma while forming non-ionized nitrogen plasma. The method further includes flowing the non-ionized nitrogen plasma into a processing region within a processing chamber, forming a nitrided capping layer from an upper portion of the doped layer by exposing the doped layer within the processing region to the non-ionized nitrogen plasma during a stabilization process.Type: ApplicationFiled: September 20, 2012Publication date: May 2, 2013Applicant: Applied Materials, Inc.Inventors: Matthew S. Rogers, Martin A. Hilkene
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Patent number: 8431468Abstract: An integrated circuit and method of making it, includes a semiconductor substrate and a support layer disposed on the semiconductor substrate. A gate insulator including a support layer doped using a noise-reducing dopant can be disposed on the semiconductor substrate. A gate stack can be disposed on the gate insulator.Type: GrantFiled: September 30, 2010Date of Patent: April 30, 2013Assignee: Infineon Technologies AGInventor: Domagoj Siprak
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Patent number: 8414790Abstract: The various embodiments described in the specification provide improved mechanisms of removal of unwanted deposits on the bevel edge to improve process yield. The embodiments provide apparatus and methods of treating the bevel edge of a copper plated substrate to convert the copper at the bevel edge to a copper compound that can be wet etched with a fluid at a high etch selectivity in comparison to copper. In one embodiment, the wet etch of the copper compound at high selectivity to copper allows the removal of the non-volatile copper at substrate bevel edge in a wet etch processing chamber. The plasma treatment at bevel edge allows the copper at bevel edge to be removed at precise spatial control to about 2 mm or below, such as about 1 mm, about 0.5 mm or about 0.25 mm, to the very edge of substrate.Type: GrantFiled: May 5, 2010Date of Patent: April 9, 2013Assignee: Lam Research CorporationInventors: Andrew D. Bailey, III, Yunsang Kim
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Patent number: 8409939Abstract: A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10?8/((1.72.51/24.51)×(Y/500)) [mol/(min·L·sec)], and the supply of a diluent gas per unit time and per unit volume is set greater than or equal to 1.7×10?4/((202.51/24.51)×(Y/500)) [mol/(min·L·sec)].Type: GrantFiled: November 11, 2010Date of Patent: April 2, 2013Assignee: Panasonic CorporationInventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
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Patent number: 8409961Abstract: An alteration method of a titanium nitride film, comprising exposing a titanium nitride film formed on a semiconductor substrate to plasma obtained by exciting a process gas that includes noble gas or nitrogen and excludes oxygen, thereby increasing a specific resistance of the titanium nitride film.Type: GrantFiled: July 8, 2009Date of Patent: April 2, 2013Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Yoshihiro Sato
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Patent number: 8409988Abstract: Provided are a method of manufacturing a semiconductor device and a substrate processing apparatus capable of improving defects of conventional CVD and ALD methods, satisfying requirements of film-thinning, and realizing high film-forming rate. The method includes forming a first layer including a first element being able to become solid state by itself on a substrate by supplying a gas containing the first element into a process vessel in which the substrate is accommodated under a condition that a CVD reaction occurs, and forming a second layer including the first element and a second element being unable to become solid state by itself by supplying a gas containing the second element into the process vessel to modify the first layer, wherein a cycle including the forming of the first layer and the forming of the second layer is performed at least once to form a thin film including the first and second elements and having a predetermined thickness.Type: GrantFiled: May 25, 2011Date of Patent: April 2, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Yushin Takasawa, Hajime Karasawa, Yoshiro Hirose
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Patent number: 8408797Abstract: A method of manufacturing a bearing device component is provided. The bearing device includes a shaft and a sleeve that surrounds the shaft, and at least either one of the shaft and the sleeve is referred to as a work. The method includes: a process of forming a coating of an anti-sticking-lube polymer on the work; a process of applying a photoluminescence material to a range overlapping a range where the coating of the anti-sticking-lube polymer is formed; and a condition detecting process of causing the photoluminescence material to emit light by causing the work to be irradiated with excitation light that excites the photoluminescence material, and detecting an applied condition of the photoluminescence material based on the light emission of the photoluminescence material, thereby detecting a condition of the coating of the anti-sticking-lube polymer.Type: GrantFiled: September 7, 2011Date of Patent: April 2, 2013Assignee: Alphana Technology Co., Ltd.Inventors: Chenglin Chen, Kazuhiro Matsuo
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Patent number: 8410704Abstract: Ionization devices that have at least two modes of ionization, and that can switch between these two modes of operation, are described. Illustratively, the ionization devices can switch between a photoionization (PI) mode and a combined mode of electroionization (EI) and PI (EI/PI mode).Type: GrantFiled: November 30, 2011Date of Patent: April 2, 2013Assignee: Agilent Technologies, Inc.Inventors: James Edward Cooley, Sameer Kothari
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Publication number: 20130078788Abstract: According to one embodiment, a producing method for a semiconductor device comprises: heating a semiconductor substrate to thereby maintain a substrate temperature of the semiconductor substrate at a desired temperature and simultaneously dope the semiconductor substrate with conductive impurities; and performing an activation treatment for activating the conductive impurities for doping.Type: ApplicationFiled: March 15, 2012Publication date: March 28, 2013Inventor: Kyoichi SUGURO
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Publication number: 20130078789Abstract: A substrate processing apparatus includes a process chamber accommodating a substrate including a thin film formed at a film-forming temperature; a gas supply unit for supplying a process gas including oxygen and/or nitrogen onto the substrate; an excitation unit for exciting the process gas supplied into the process chamber; a heating unit for heating the substrate; an exhaust unit for exhausting an inside of the process chamber; and a control unit for controlling the gas supply unit, the excitation unit, the heating unit and the exhaust unit such that a temperature of the substrate is equal to or lower than the film-forming temperature when the substrate is processed by heating the substrate by the heating unit, exciting the process gas supplied from the gas supply unit by the excitation unit, and supplying the process gas excited by the excitation unit onto a surface of the substrate.Type: ApplicationFiled: September 19, 2012Publication date: March 28, 2013Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventor: Hitachi Kokusai Electric Inc.
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Publication number: 20130072007Abstract: A method for fabricating black silicon by using plasma immersion ion implantation is provided, which includes: putting a silicon wafer into a chamber of a black silicon fabrication apparatus; adjusting processing parameters of the black silicon fabrication apparatus to preset scales; generating plasmas in the chamber of the black silicon fabrication apparatus; implanting reactive ions among the plasmas into the silicon wafer, and forming the black silicon by means of the reaction of the reactive ions and the silicon wafer. The method can form the black silicon which has a strong light absorption property and is sensitive to light, and has advantages of high productivity, low cost and simple production process.Type: ApplicationFiled: July 26, 2010Publication date: March 21, 2013Applicant: The Institute of Microelectronics of Chinese Academy of SciencesInventors: Yang Xia, Bangwu Liu, Chaobo Li, Jie Liu, Minggang Wang, Yongtao Li
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Publication number: 20130072006Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.Type: ApplicationFiled: November 12, 2012Publication date: March 21, 2013Applicant: Micron Technology, Inc.Inventor: Micron Technology, Inc.
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Patent number: 8399342Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.Type: GrantFiled: April 5, 2011Date of Patent: March 19, 2013Assignee: Hynix Semiconductor Inc.Inventor: Tae-Kyun Kim
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Patent number: 8389390Abstract: A method of introducing an impurity into a wafer surface is provided. The method comprises the steps of: low energy implantation of impurity into a surface of the wafer to generate an implanted dopant layer; and simultaneously removing an implanted surface of the implanted dopant layer to generate a doping profile with controlled areal impurity dosage.Type: GrantFiled: April 10, 2008Date of Patent: March 5, 2013Inventor: Tzu-Yin Chiu
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Patent number: 8389417Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.Type: GrantFiled: November 12, 2010Date of Patent: March 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama
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Publication number: 20130052811Abstract: A technique for processing a workpiece is disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for processing a substrate, where the method may comprise: providing the workpiece in the chamber; providing a plurality of electrodes between a wall of the chamber and the workpiece; generating a plasma containing ions between the plurality of electrodes and the workpiece, ion density in an inner portion of the plasma being greater than the ion density in an outer portion of the plasma portion, the outer portion being between the inner portion and the wall of the chamber; and providing a bias voltage to the plurality of electrodes and dispersing at least a portion of the ions in the inner portion until the ion density in the inner portion is substantially equal to the ion density in the periphery plasma portion.Type: ApplicationFiled: October 26, 2012Publication date: February 28, 2013Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventor: VARIAN SEMICONDUCTOR EQUIPMENT ASSO
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Patent number: 8383522Abstract: There is provided a micro pattern forming method including forming a thin film on a substrate; forming a film serving as a mask when processing the thin film; processing the film serving as a mask into a pattern including lines having a preset pitch; trimming the pattern including the lines; and forming an oxide film on the pattern including the lines and on the thin film by alternately supplying a source gas and an activated oxygen species. Here, the process of trimming the pattern and the process of forming an oxide film are consecutively performed in a film forming apparatus configured to form the oxide film.Type: GrantFiled: June 7, 2011Date of Patent: February 26, 2013Assignee: Tokyo Electron LimitedInventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
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Patent number: 8383496Abstract: A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate.Type: GrantFiled: August 7, 2009Date of Patent: February 26, 2013Inventors: Kazuhiko Tonari, Tsutomu Nishihashi
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Patent number: 8377804Abstract: To provide a semiconductor substrate in which a semiconductor element having favorable crystallinity and high performance can be formed. A single crystal semiconductor substrate having an embrittlement layer and a base substrate are bonded with an insulating layer interposed therebetween; the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment; a single crystal semiconductor layer is fixed to the base substrate; the single crystal semiconductor layer is irradiated with a laser beam; the single crystal semiconductor layer is in a partially melted state to be recrystallized; and crystal defects are repaired. In addition, the energy density of a laser beam with which the best crystallinity of the single crystal semiconductor layer is obtained is detected by a microwave photoconductivity decay method.Type: GrantFiled: September 29, 2009Date of Patent: February 19, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junpei Momo, Kosei Nei, Hiroaki Honda, Masaki Koyama, Akihisa Shimomura
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Publication number: 20130040444Abstract: Embodiments of the invention provide an improved apparatus and methods for nitridation of stacks of materials. In one embodiment, a remote plasma system includes a remote plasma chamber defining a first region for generating a plasma comprising ions and radicals, a process chamber defining a second region for processing a semiconductor device, the process chamber comprising an inlet port formed in a sidewall of the process chamber, the inlet port being in fluid communication with the second region, and a delivery member disposed between the remote plasma chamber and the process chamber and having a passageway in fluid communication with the first region and the inlet port, wherein the delivery member is configured such that a longitudinal axis of the passageway intersects at an angle of about 20 degrees to about 80 degrees with respect to a longitudinal axis of the inlet port.Type: ApplicationFiled: June 28, 2012Publication date: February 14, 2013Applicant: Applied Materials, Inc.Inventors: MATTHEW S. ROGERS, Roger Curtis, Lara Hawrylchak, Ken Kaung Lai, Bernard L. Hwang, Jeffrey Tobin, Christopher Olsen, Malcom J. Bevan
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Publication number: 20130037863Abstract: The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.Type: ApplicationFiled: October 12, 2012Publication date: February 14, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Taiwan Semiconductor Manufacturing Company,
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Patent number: 8372735Abstract: A method of using helium to create ultra shallow junctions is disclosed. A pre-implantation amorphization using helium has significant advantages. For example, it has been shown that dopants will penetrate the substrate only to the amorphous-crystalline interface, and no further. Therefore, by properly determining the implant energy of helium, it is possible to exactly determine the junction depth. Increased doses of dopant simply reduce the substrate resistance with no effect on junction depth. Furthermore, the lateral straggle of helium is related to the implant energy and the dose rate of the helium PAI, therefore lateral diffusion can also be determined based on the implant energy and dose rate of the helium PAI. Thus, dopant may be precisely implanted beneath a sidewall spacer, or other obstruction.Type: GrantFiled: December 19, 2008Date of Patent: February 12, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Christopher Hatem, Ludovic Godet, Alexander Kontos
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Patent number: 8367531Abstract: The present invention provides molecules useful for aluminum implant in semiconductor materials. The molecules can be used in various doping techniques such as ion implant, plasma doping or derivates methods.Type: GrantFiled: March 4, 2011Date of Patent: February 5, 2013Assignees: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude, American Air Liquide, Inc.Inventors: Vincent M. Omarjee, Christian Dussarrat, Jean-Marc Girard, Nicolas Blasco
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Patent number: 8367530Abstract: A substrate processing apparatus, including: a reaction container in which a substrate is processed; a seal cap, brought into contact with one end in an opening side of the reaction container via a first sealing member and a second sealing member so as to seal the opening of the reaction container air-tightly; a first gas channel, formed in a region between the first sealing member and the second sealing member in a state where the seal cap is in contact with the reaction container; a second gas channel, provided to the seal cap and through which the first gas channel is in communication with an inside of the reaction container; a first gas supply port that is provided to the reaction container and supplies a first gas to the first gas channel; and a second gas supply port that is provided to the reaction container and supplies a second gas into the reaction container, wherein a front end opening of the first gas supply port opening to the first gas channel, and a base opening of the second gas channel openinType: GrantFiled: March 26, 2010Date of Patent: February 5, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Kiyohiko Maeda, Takeo Hanashima, Masanao Osanai
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Publication number: 20130023104Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes a step of forming an impurity layer on a semiconductor layer, the impurity layer including an impurity element to be doped to the semiconductor layer, and a step of applying a first gas in a plasma state including a first noble gas atom and a second gas in a plasma state including a second noble gas atom or hydrogen (H) toward the impurity layer, the second noble gas atom having a smaller atomic mass than the first noble gas atom.Type: ApplicationFiled: June 29, 2012Publication date: January 24, 2013Inventor: Tatsunori ISOGAI
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Publication number: 20130023112Abstract: Methods for processing substrates are provided herein. In some embodiments, a method of processing a substrate may include implanting a substrate with a dopant in a first vacuum chamber; transferring the substrate to a second vacuum chamber at a first pressure below atmospheric; providing an inert gas to the second vacuum chamber to raise the pressure to a second pressure; pumping down the second vacuum chamber to a third pressure below the second pressure; and providing the inert gas to the second vacuum chamber to raise the pressure to a fourth pressure above the third pressure.Type: ApplicationFiled: October 28, 2011Publication date: January 24, 2013Applicant: APPLIED MATERIALS, INC.Inventor: Kartik SANTHANAM
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Patent number: 8343842Abstract: A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist which includes resist openings formed over the active circuit areas as well as additional resist openings formed over inactive areas in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures for use in manufacturing the final structure.Type: GrantFiled: March 31, 2011Date of Patent: January 1, 2013Assignee: Freescale Semiconductor, Inc.Inventors: David M. Schraub, Terry A. Breeden, James D. Legg, Mehul D. Shroff, Ruiqi Tian
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Patent number: 8343860Abstract: The present invention provides molecules with high carbon content for Carbon-containing species implant in semiconductor material. The molecules can be used in various doping techniques such as ion implant, plasma doping or derivates methods.Type: GrantFiled: March 4, 2011Date of Patent: January 1, 2013Assignees: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude, American Air Liquide, Inc.Inventors: Vincent M. Omarjee, Christian Dussarrat, Jean-Marc Girard, Nicolas Blasco
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Patent number: 8343857Abstract: To provide a manufacturing method of a microcrystalline semiconductor film, the manufacturing method comprises the steps of forming a first semiconductor film over a substrate by generating plasma by performing continuous discharge under an atmosphere containing a deposition gas; forming a second semiconductor film over the first semiconductor film by generating plasma by performing pulsed discharge under the atmosphere containing the deposition gas; forming a third semiconductor film over the second semiconductor film by generating plasma by performing continuous discharge under the atmosphere containing the deposition gas; and forming a fourth semiconductor film over the third semiconductor film by generating plasma by performing pulsed discharge under the atmosphere containing the deposition gas.Type: GrantFiled: April 25, 2011Date of Patent: January 1, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoshi Toriumi