Ionized Molecules Patents (Class 438/515)
  • Patent number: 10811503
    Abstract: An electrode having an embedded charge contains a substrate, a first electronic charge trap defined at the interface of a first insulating layer and a second insulating layer; and a first conductive layer disposed on the first electronic charge trap; wherein the first conductive layer contains a conductive material configured to permit an external electric field to penetrate the electrode from the first electronic charge trap; and wherein the first insulating layer is not the same as the second insulating layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 20, 2020
    Assignee: BECSIS, LLC
    Inventors: Nicholas Boruta, Michael Boruta
  • Patent number: 10651003
    Abstract: An ion implanting method includes providing a gas having a bonding energy ranged from about 220 kJ/mol to about 450 kJ/mol; ionizing the gas to form a plurality of types of ions; and directing at least one of the types of the ions to implant a substance. The gas includes at least one of N2H4, CH3N2H3, C6H5N2H3, CFCl3 and C(CH3)3F.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Ying Tsai, Ming-Hui Li, Chia-Cheng Liu
  • Patent number: 10636807
    Abstract: A semiconductor memory device includes a stacked body, a semiconductor portion, a first insulating film, a charge storage layer, and a second insulating film. The stacked body has a plurality of electrode layers stacked in a spaced apart manner from each other. The semiconductor portion is provided in the stacked body and extends in a first direction where the plurality of electrode layers are stacked. The first insulating film is provided between the plurality of electrode layers and the semiconductor portion. The charge storage layer is provided between the plurality of electrode layers and the first insulating film and contains a compound including at least one of hafnium oxide or zirconium oxide and a first material having a valence lower than that of the at least one of the hafnium oxide or the zirconium oxide.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Itokawa, Takashi Furuhashi
  • Patent number: 9911612
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate is prepared. Boron-containing ions are generated by reacting a borane-based compound and a halogen-containing source with each other. The borane-based compound includes boron having a mass number of 11 (11B). The boron-containing ions are implanted into the semiconductor substrate to form an impurity region.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: March 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Yeol Kim, Myung-Beom Park, Han-Gyul Ko, Hwi-Hyeon Oh, Hye-Young Jin
  • Patent number: 9536741
    Abstract: The method for performing activation of n-type or p-type dopants in a GaN-base semiconductor includes the following steps: providing a substrate including a GaN-base semiconductor material layer, performing the following successive steps at least twice: implanting electric dopant impurities in the semiconductor material layer, performing heat treatment so as to activate the electric dopant impurities in the semiconductor material layer, a cap layer covering the semiconductor material layer when the heat treatment is performed, two implantation steps of electric dopant impurities being separated by a heat treatment step.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 3, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Claire Agraffeil
  • Patent number: 9524849
    Abstract: A method for improving the ion beam quality in an ion implanter is disclosed. In some ion implantation systems, contaminants from the ion source are extracted with the desired ions, introducing contaminants to the workpiece. These contaminants may be impurities in the ion source chamber. This problem is exacerbated when mass analysis of the extracted ion beam is not performed, and is further exaggerated when the desired feedgas includes a halogen. The introduction of a diluent gas in the ion chamber may reduce the deleterious effects of the halogen on the inner surfaces of the chamber, reducing contaminants in the extracted ion beam. In some embodiments, the diluent gas may be germane or silane.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: December 20, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: John W. Graff, Bon-Woong Koo, John A. Frontiero, Nicholas PT Bateman, Timothy J. Miller, Vikram M. Bhosle
  • Patent number: 8975603
    Abstract: Systems and methods for plasma doping microfeature workpieces are disclosed herein. In one embodiment, a method of implanting boron ions into a region of a workpiece includes generating a plasma in a chamber, selectively applying a pulsed electrical potential to the workpiece with a duty cycle of between approximately 20 percent and approximately 50 percent, and implanting an ion specie into the region of the workpiece.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Allen McTeer
  • Patent number: 8969160
    Abstract: The present invention is related to microelectronic device technologies. A method for making an asymmetric source-drain field-effect transistor is disclosed. A unique asymmetric source-drain field-effect transistor structure is formed by changing ion implantation tilt angles to control the locations of doped regions formed by two ion implantation processes. The asymmetric source-drain field-effect transistor has structurally asymmetric source/drain regions, one of which is formed of a P-N junction while the other one being formed of a mixed junction, the mixed junction being a mixture of a Schottky junction and a P-N junction.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: March 3, 2015
    Assignee: Fudan University
    Inventors: Yinghua Piao, Dongping Wu, Shili Zhang
  • Patent number: 8956961
    Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Rexchip Electronics Corporation
    Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
  • Publication number: 20140357069
    Abstract: A novel method and system for using aluminum dopant compositions is provided. A composition of the aluminum dopant compositions is selected with sufficient vapor pressure and minimal carbon content, thereby enabling ease of delivery to an ion implant process and substantial reduction of carbon deposition during Al ion implantation. The source material is preferably stored and delivered from a sub-atmospheric storage and delivery device to enhance safety and reliability during the Al ion implantation process.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 4, 2014
    Inventors: Ashwini K. Sinha, Lloyd A. Brown
  • Patent number: 8883620
    Abstract: A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Praxair Technology, Inc.
    Inventors: Ashwini K. Sinha, Ching I Li
  • Patent number: 8846509
    Abstract: The present invention generally relates to methods of forming substrates using remote radical hydride doping. The methods generally include remotely activating a gas and introducing activated radicals of the gas into a chamber. The activated radicals may be activated hydride radicals of a gas such as diborane (B2H6), phosphine (PH3), or arsine (AsH3) which are utilized to incorporate an element such as boron, phosphorus, or arsenic into a substrate having a surface temperature between about 400 degrees Celsius and about 1000 degrees Celsius. Alternatively, the activated radicals may be activated radicals of an inert gas. The activated radicals of the inert gas are introduced into a chamber having a dopant-containing gas, such as diborane, phosphine, or arsine, therein. The activated radicals of the inert gas activate the dopant-gas and incorporate dopants into a heated substrate located within the chamber.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Christopher S. Olsen, Johanes S. Swenberg
  • Patent number: 8679914
    Abstract: A method of forming a chalcogenide material on a surface of a substrate comprising exposing a surface of a substrate to ionized gas clusters from a source gas, the ionized gas clusters comprising at least one chalcogen and at least one electropositive element. A method of forming a resistive random access memory device is also disclosed. The method comprises forming a plurality of memory cells wherein each cell of the plurality of memory cells is formed by forming a metal on a first electrode, forming a chalcogenide material on the metal by a gas cluster ion beam process, and forming a second electrode on the chalcogenide material. A method of forming another resistive random access memory device and a random access memory device including the chalcogenide material are also disclosed.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Timothy A. Quick
  • Patent number: 8642135
    Abstract: Systems and methods for plasma doping microfeature workpieces are disclosed herein. In one embodiment, a method of implanting boron ions into a region of a workpiece includes generating a plasma in a chamber, selectively applying a pulsed electrical potential to the workpiece with a duty cycle of between approximately 20 percent and approximately 50 percent, and implanting an ion specie into the region of the workpiece.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Allen McTeer
  • Patent number: 8603896
    Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: December 10, 2013
    Assignee: Soitec
    Inventors: Gweltaz Gaudin, Carlos Mazure
  • Patent number: 8598022
    Abstract: An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B2F4. Synthesis methods for such compounds, and ion implantation methods using such compounds, are described, as well as storage and dispensing vessels in which the isotopically-enriched, boron-containing compound is advantageously contained for subsequent dispensing use.
    Type: Grant
    Filed: November 19, 2011
    Date of Patent: December 3, 2013
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Robert Kaim, Joseph D. Sweeney, Oleg Byl, Sharad N. Yedave, Edward E. Jones, Peng Zou, Ying Tang, Barry Lewis Chambers, Richard S. Ray
  • Publication number: 20130260543
    Abstract: Techniques for processing a substrate are disclosed. In one exemplary embodiment, the technique may be realized with an ion implantation system for processing a substrate.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 3, 2013
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventor: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
  • Patent number: 8530343
    Abstract: A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach: (1) diffusion control for USJ formation; and (2) high dose carbon implantation for stress engineering. Diffusion control for USJ formation is demonstrated in conjunction with a boron or shallow boron cluster implant of the source/drain structures in PMOS. More particularly, first, a cluster carbon ion, such as C16Hx+, is implanted into the source/drain region at approximately the same dose as the subsequent boron implant; followed by a shallow boron, boron cluster, phosphorous or phosphorous cluster ion implant to form the source/drain extensions, preferably using a borohydride cluster, such as B18Hx+ or B10Hx+.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: September 10, 2013
    Assignee: SemEquip, Inc.
    Inventors: Wade A. Krull, Thomas N. Horsky
  • Patent number: 8524584
    Abstract: Methods and carbon ion precursor compositions for implanting carbon ions generally includes vaporizing and ionizing a gas mixture including carbon oxide and methane gases in an ion source to create a plasma and produce carbon ions. The ionized carbon within the plasma is then extracted to form an ion beam. The ion beam is mass analyzed with a mass analyzer magnet to permit the ionized carbon to pass therethrough and implant into a workpiece.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: September 3, 2013
    Assignee: Axcelis Technologies, Inc.
    Inventors: William D. Lee, Daniel R. Tieger, Tseh-Jen Hsieh
  • Patent number: 8497196
    Abstract: A method for fabricating a semiconductor device includes forming a gate electrode on a surface of a substrate via a gate insulating film, forming an insulating film on a side surface of the gate electrode, and exposing an oxygen plasma onto the surface of the substrate. An electron temperature of the oxygen plasma in a vicinity of the surface of the substrate is equal to or less than about 1.5 eV.
    Type: Grant
    Filed: October 4, 2009
    Date of Patent: July 30, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Masaru Sasaki
  • Patent number: 8440551
    Abstract: A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: May 14, 2013
    Assignee: ULVAC, Inc.
    Inventors: Kazuhiko Tonari, Tsutomu Nishihashi
  • Publication number: 20130078790
    Abstract: A method of implanting carbon ions into a target substrate, including: ionizing a carbon containing dopant material to produce a plasma having ions; optionally co-flowing an additional gas or series of gases with the carbon-containing dopant material; and implanting the ions into the target substrate. The carbon-containing dopant material is of the formula CwFxOyHz wherein if w=1, then x>0 and y and z can take any value, and wherein if w>1 then x or y is >0, and z can take any value. Such method significantly improves the efficiency of an ion implanter tool, in relation to the use of carbon source gases such as carbon monoxide or carbon dioxide.
    Type: Application
    Filed: November 20, 2012
    Publication date: March 28, 2013
    Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.
    Inventor: Advanced Technology Materials, Inc.
  • Patent number: 8404572
    Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
  • Patent number: 8389068
    Abstract: Methods of implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. A method of manufacturing a semiconductor device including implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. Also disclosed are a system for supplying a boron hydride precursor, and methods of forming a boron hydride precursor and methods for supplying a boron hydride precursor. In one implementation of the invention, the boron hydride precursors are generated for cluster boron implantation, for manufacturing semiconductor products such as integrated circuitry.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: March 5, 2013
    Assignee: Advanced Technology Materials, Inc.
    Inventors: W. Karl Olander, Jose I. Arno, Robert Kaim
  • Patent number: 8383496
    Abstract: A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: February 26, 2013
    Inventors: Kazuhiko Tonari, Tsutomu Nishihashi
  • Patent number: 8343860
    Abstract: The present invention provides molecules with high carbon content for Carbon-containing species implant in semiconductor material. The molecules can be used in various doping techniques such as ion implant, plasma doping or derivates methods.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: January 1, 2013
    Assignees: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude, American Air Liquide, Inc.
    Inventors: Vincent M. Omarjee, Christian Dussarrat, Jean-Marc Girard, Nicolas Blasco
  • Patent number: 8343859
    Abstract: A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee
  • Patent number: 8334193
    Abstract: Provided is a method of manufacturing a semiconductor device capable of preventing a relative displacement of the positions between a range where impurity ions are injected and a range where charged particles are injected. The method of manufacturing the semiconductor device includes: irradiating impurity ions in a state in which a mask is disposed between an impurity ion irradiation apparatus and a semiconductor substrate; and irradiating charged particles to form a short carrier lifetime region, in a state in which the mask is disposed between a charged particle irradiation apparatus and the semiconductor substrate. A relative positional relationship between the mask and the semiconductor substrate is not changed from a beginning of one of the irradiating the impurity ions and the irradiating the charged particles to a completion of both of the irradiating the impurity ions and the irradiating the charged particles.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 18, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Shinya Iwasaki, Akira Kamei
  • Patent number: 8328936
    Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 11, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Patent number: 8304033
    Abstract: Disclosed are methods of operation to grow, modify, deposit, or dope a layer upon a substrate using a multi-nozzle and skimmer assembly for introducing a process gas mixture, or multiple process gases mixtures, in a gas cluster ion beam (GCIB) system. Also disclosed is a method of forming a shallow trench isolation (STI) structure on a substrate, for example, an SiO2 STI structure, using a multiple nozzle system with two separate gas supplies, for example providing a silicon-containing gas and an oxygen-containing gas.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: November 6, 2012
    Assignee: TEL Epion Inc.
    Inventors: Martin D. Tabat, Matthew C. Gwinn, Robert K. Becker, Avrum Freytsis, Michael Graf
  • Patent number: 8288257
    Abstract: Methods for implanting material into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting material into a substrate includes providing a substrate into a processing chamber, the substrate comprising a substrate surface having a material layer formed thereon, generating a first plasma of a non-dopant processing gas, exposing the material layer to the plasma of the non-dopant processing gas, generating a second plasma of a dopant processing gas including a reacting gas adapted to produce dopant ions, and implanting dopant ions from the plasma into the material layer. The method may further include a cleaning or etch process.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: October 16, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Matthew D. Scotney-Castle, Majeed A. Foad, Peter I. Porshnev
  • Publication number: 20120202340
    Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be performed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 9, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Xianfeng LU, Ludovic GODET, Anthony RENAU
  • Publication number: 20120202341
    Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be preformed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 9, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Xiangfeng LU, Ludovic GODET, Anthony RENAU
  • Patent number: 8222119
    Abstract: A method for temperature control during a process of cleaving a plurality of free-standing thick films from a bulk material includes clamping a bulk material using a mechanical clamp device adapted to engage the bottom region of the bulk material through a seal with a planar surface of a stage to form a cavity with a height between the bottom region and the planar surface. The planar surface includes a plurality of gas passageways allowing a gas filled in the cavity with adjustable pressure. The method also includes maintaining the temperature of the surface region by processing at least input data and executing a control scheme utilizing at least one or more of: particle bombardment to heat the surface region; radiation to heat the surface region; and gas-assisted conduction between the bottom region and the stage.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: July 17, 2012
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 8178951
    Abstract: There is provided a compound semiconductor substrate prepared by forming a point defect in an inside structure thereof by implanting an electrically-neutral impurity with energy of 0.1 to 10 MeV on a surface of the substrate. When the compound semiconductor is undoped, electrical resistance increases to increase insulating properties, and when the compound semiconductor is doped with an n-type dopant, the impurity is implanted and charge concentration of the substrate increases to increase conductive properties. In accordance with the present invention, the various electrical properties needed for the compound semiconductor can be effectively controlled by increasing the insulating properties of the undoped compound semiconductor or by increasing the charge concentration of the n-type compound semiconductor, and the application range to various devices can be expanded.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: May 15, 2012
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventors: Young Zo Yoo, Hyun Min Shin, Jun Sung Choi
  • Patent number: 8105926
    Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: January 31, 2012
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hiroyuki Ito, Bunji Mizuno
  • Publication number: 20120021592
    Abstract: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current.
    Type: Application
    Filed: August 12, 2011
    Publication date: January 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Koichiro Tanaka
  • Patent number: 8101488
    Abstract: Embodiments of the present invention provide for a system for accelerating hydrogen ions. A hydrogen generator holding a supply of water is configured to generate a flow of hydrogen gas from the supply of water. An ion source structure is configured to generate a plurality of hydrogen ions from the flow of hydrogen gas. An accelerator tube is configured to accelerate the plurality of hydrogen ions. The supply of water has an isotopic ratio of deuterium that is smaller than the isotopic ratio of deuterium in Vienna Standard Mean Ocean Water.
    Type: Grant
    Filed: December 25, 2010
    Date of Patent: January 24, 2012
    Assignee: Twin Creeks Technologies, Inc.
    Inventors: Theodore H. Smick, Steven Richards, Geoffrey Ryding, Kenneth H Purser
  • Patent number: 8097529
    Abstract: A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach: (1) diffusion control for USJ formation; and (2) high dose carbon implantation for stress engineering. Diffusion control for USJ formation is demonstrated in conjunction with a boron or shallow boron cluster implant of the source/drain structures in PMOS. More particularly, first, a cluster carbon ion, such as C16Hx+, is implanted into the source/drain region at approximately the same dose as the subsequent boron implant; followed by a shallow boron, boron cluster, phosphorous or phosphorous cluster ion implant to form the source/drain extensions, preferably using a borohydride cluster, such as B18Hx+ or B10Hx+.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: January 17, 2012
    Assignee: Semequip, Inc.
    Inventors: Wade A. Krull, Thomas N. Horsky
  • Publication number: 20120009769
    Abstract: The invention is directed to ion implantation. Ion implantation is a process whereby energetic ions are used to uniformly irradiate the surface of a material—typically a semiconductor wafer. Either atomic or molecular ions are created in an ion source and then extracted for analysis (e.g. by magnetic separation) to ensure the purity of the ion beam. Post-analysis acceleration and scanning of the beam is done prior to sample irradiation. Each dopant-type acts, in general, to increase the conductivity of the silicon.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 12, 2012
    Applicant: Amethyst Research, Inc.
    Inventors: Orin W. Holland, Khalid Hossain
  • Publication number: 20110306193
    Abstract: A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach: (1) diffusion control for USJ formation; and (2) high dose carbon implantation for stress engineering. Diffusion control for USJ formation is demonstrated in conjunction with a boron or shallow boron cluster implant of the source/drain structures in PMOS. More particularly, first, a cluster carbon ion, such as C16Hx+, is implanted into the source/drain region at approximately the same dose as the subsequent boron implant; followed by a shallow boron, boron cluster, phosphorous or phosphorous cluster ion implant to form the source/drain extensions, preferably using a borohydride cluster, such as B18Hx+ or B10Hx+.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 15, 2011
    Applicant: SemEquip, Inc.
    Inventors: Wade A. Krull, Thomas N. Horsky
  • Patent number: 8076210
    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: December 13, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
  • Patent number: 8053847
    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: November 8, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
  • Patent number: 8048788
    Abstract: A method for treating a structure is described. One embodiment includes forming a structure on a substrate, wherein the structure has a plurality of surfaces including one or more first surfaces lying substantially parallel to a first plane parallel with said substrate and one or more second surfaces lying substantially perpendicular to the first plane. Additionally, the method comprises directing a gas cluster ion beam (GCIB) formed from a material source toward the substrate with a direction of incidence, and orienting the substrate relative to the direction of incidence. The method further comprises treating the one or more second surfaces.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: November 1, 2011
    Assignee: TEL Epion Inc.
    Inventors: John J. Hautala, Noel Russell
  • Patent number: 7994031
    Abstract: A method of manufacturing a semiconductor device is further described, comprising the steps of providing a supply of dopant atoms or molecules into an ionization chamber, combining the dopant atoms or molecules into clusters containing a plurality of dopant atoms, ionizing the dopant clusters into dopant cluster ions, extracting and accelerating the dopant cluster ions with an electric field, selecting the desired cluster ion by mass analysis, modifying the final implant energy of the cluster ion through post-analysis ion optics, and implanting the dopant cluster ions into a semiconductor substrate. In general, dopant clusters contain n dopant atoms where n can be 2, 3, 4 or any integer number. This method provides the advantages of increasing the dopant dose rate to n times the implantation current with an equivalent per dopant atom energy of 1/n times the cluster implantation energy.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: August 9, 2011
    Assignee: Semequip, Inc.
    Inventors: Thomas Neil Horsky, Dale Conrad Jacobson, Wade Allen Krull
  • Patent number: 7972945
    Abstract: A top plate, disposed on an upper portion of a vacuum container so as to face a substrate-placing area of a sample electrode, is provided with an impurity-containing film that contains an impurity, and is formed on a top plate peripheral edge portion area that is a face exposable to a plasma generated in the vacuum container, and is located on a peripheral edge of a top plate center portion area that faces the center portion of the substrate-placing area.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Publication number: 20110143527
    Abstract: Herein an improved technique for generating uniform ion beam is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for processing a substrate with an ion implanter comprising an ion source. The method may comprise: introducing dopant into an ion source chamber of the ion source, the dopant may comprise molecules containing boron and hydrogen; introducing diluent into the ion source chamber, the diluent containing halogen; ionizing the dopant and the diluent into molecular ions and halogen containing ions, the molecular ions containing boron and hydrogen; extracting the molecular ions and the halogen containing ions from the ions source chamber; and directing the molecular ions toward the substrate, where the halogen containing ions may improve uniformity of the molecular ions extracted from the ion source and extend the lifetime of the ion source.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 16, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Wilhelm P. PLATOW, Neil J. Bassom, Peter F. Kurunczi, Alexander S. Perel, Craig R. Chaney
  • Publication number: 20110136329
    Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method further comprises depositing on the surface of the semiconductor substrate an impurity thin film including an impurity atom which becomes a donor or an acceptor in the semiconductor substrate and performing an ion implantation from a diagonal upper direction to the impurity thin film deposited on the concavity and convexity part of the semiconductor substrate. The method still further comprises recoiling the impurity atom from the inside of the impurity thin film to the inside of the concavity and convexity part by performing the ion implantation.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 9, 2011
    Applicant: SEN Corporation
    Inventors: Michiro SUGITANI, Genshu Fuse
  • Patent number: 7947582
    Abstract: A method of preparing a floating trap type device on a substrate is described. The method comprises forming a trap layer structure on a substrate, and modifying a composition of one or more layers in the trap layer structure by exposing the trap layer structure to a gas cluster ion beam (GCIB).
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: May 24, 2011
    Assignee: TEL Epion Inc.
    Inventors: John J. Hautala, Mitchell A. Carlson
  • Patent number: 7943204
    Abstract: Methods of implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. A method of manufacturing a semiconductor device including implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. Also disclosed are a system for supplying a boron hydride precursor, and methods of forming a boron hydride precursor and methods for supplying a boron hydride precursor. In one implementation of the invention, the boron hydride precursors are generated for cluster boron implantation, for manufacturing semiconductor products such as integrated circuitry.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: May 17, 2011
    Assignee: Advanced Technology Materials, Inc.
    Inventors: W. Karl Olander, Jose I. Arno, Robert Kaim