Using Oblique Beam Patents (Class 438/525)
  • Patent number: 10256243
    Abstract: A semiconductor structure, a method for fabricating the semiconductor structure and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pull-up transistor region and a pull-down transistor region. The method also includes forming a gate structure on each fin; and forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region. In addition, the method includes forming a first pull-down doped region connected to an adjacent pull-up doped epitaxial layer in the fin on one side of the gate structure in the pull-down transistor region. Further, the method includes forming a second pull-down doped region by performing an ion-doped non-epitaxial layer process on the fin on another side of the gate structure in the pull-down transistor region.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 9, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 9885957
    Abstract: Provided herein are approaches for patterning a semiconductor device. Exemplary approaches include providing a set of photoresist patterning features atop a substrate, the set of patterning features having a surface roughness characterized by a set of protrusions and a set of indentations. The approaches further include implanting first ions into a sidewall surface of the set of photoresist patterning features to form a film layer having a non-uniform thickness along the sidewall surface, wherein a thickness of the film layer formed over the indentations is greater than a thickness of the film layer formed over the protrusions. The approaches further include sputtering the sidewall surface of the photoresist patterning features following the formation of the film layer to modify a portion of the film layer and/or the set of protrusions, wherein the sputtering includes directing second ions to photoresist patterning features at an angle with the sidewall surface.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: February 6, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Maureen K. Petterson, Tristan Ma, John Hautala
  • Patent number: 9755094
    Abstract: To provide an imaging device equipped with a photodiode, which is capable of enhancing both of a capacity and sensitivity. In an area of a P-type well in which a photodiode is formed, a P-type impurity region is formed from the surface of the P-type well to a predetermined depth. Further, an N-type impurity region is formed to extend to a deeper position. N-type impurity regions and P-type impurity regions respectively extending in a gate width direction from a lower part of the N-type impurity region to a deeper position so as to contact the N-type impurity region are alternately arranged in a plural form along a gate length direction in a form to contact each other.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: September 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Sakai, Katsumi Eikyu
  • Patent number: 9634165
    Abstract: An apparatus, system, and method are disclosed for restoring efficiency of a photovoltaic cell. An illumination module illuminates photovoltaic cells so the cells receive a time integrated irradiance equivalent to at least 5 hours of solar illumination. After illumination, an annealing module anneals the photovoltaic cells at a temperature above 90 degrees Celsius for a minimum of 10 minutes. In one embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 20 hours of solar illumination. In another embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 16 hours of solar illumination while being heated to at least 50 degrees Celsius. In another embodiment, a solar concentrator irradiates the photovoltaic cells in sunlight for at least 10 hours and increases the irradiance of solar illumination on the cells by a factor of 2 to 5.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Rainer Krause, Zhengwen Li, Gerd Pfeiffer, Kevin Prettyman, Brian C. Sapp
  • Patent number: 9041164
    Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 26, 2015
    Assignee: IMEC
    Inventors: Roel Gronheid, Christoph Adelmann, Annelies Delabie, Gustaf Winroth
  • Patent number: 9040399
    Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
  • Patent number: 9029249
    Abstract: Disclosed is a plasma doping apparatus provided with a plasma generating mechanism. The plasma generating mechanism includes a microwave generator that generates microwave for plasma excitation, a dielectric window that transmits the microwave generated by the microwave generator into a processing container, and a radial line slot antenna formed with a plurality of slots. The radial line slot antenna radiates the microwave to the dielectric window. A control unit controls the plasma doping apparatus such that a doping gas and a gas for plasma excitation are supplied into the processing container by a gas supply unit in a state where the substrate is placed on a holding unit, and then plasma is generated by the plasma generating mechanism to perform doping on the substrate such that the concentration of the dopant implanted into the substrate is less than 1×1013 atoms/cm2.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hirokazu Ueda, Masahiro Oka, Masahiro Horigome, Yuuki Kobayashi
  • Patent number: 8993425
    Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ying Zhang
  • Patent number: 8993424
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Patent number: 8987041
    Abstract: Certain embodiments provide method for manufacturing a solid-state imaging device, including forming an electrode and forming a second impurity layer. The electrode is formed on a semiconductor substrate including a first impurity layer of a first conductivity type on a surface. The second impurity layer is a second conductivity type and is formed by implanting an impurity of a second conductivity type into the first impurity layer in an oblique direction with respect to the surface of the semiconductor substrate on the condition that the impurity penetrates an end portion of the electrode, based on a position of the electrode. The second impurity layer is bonded to the first impurity layer to constitute a photodiode, and a portion of the second impurity layer is disposed under the electrode.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ken Tomita, Atsushi Sasaki
  • Patent number: 8981337
    Abstract: The various technologies presented herein relate to a three dimensional manufacturing technique for application with semiconductor technologies. A membrane layer can be formed over a cavity. An opening can be formed in the membrane such that the membrane can act as a mask layer to the underlying wall surfaces and bottom surface of the cavity. A beam to facilitate an operation comprising any of implantation, etching or deposition can be directed through the opening onto the underlying surface, with the opening acting as a mask to control the area of the underlying surfaces on which any of implantation occurs, material is removed, and/or material is deposited. The membrane can be removed, a new membrane placed over the cavity and a new opening formed to facilitate another implantation, etching, or deposition operation. By changing the direction of the beam different wall/bottom surfaces can be utilized to form a plurality of structures.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: March 17, 2015
    Assignee: Sandia Corporation
    Inventors: David Bruce Burckel, Paul S. Davids, Paul J. Resnick, Bruce L. Draper
  • Publication number: 20150069582
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of pillars vertically extending from the semiconductor substrate, each pillar including a groove formed in an upper surface thereof, a salicide layer formed to cover the upper surface and a lateral circumference of an upper end of each pillar and a lower electrode formed to cover an upper surface and a lateral surface of the salicide layer.
    Type: Application
    Filed: December 5, 2013
    Publication date: March 12, 2015
    Applicant: SK hynix Inc.
    Inventor: Myoung Sub KIM
  • Patent number: 8889503
    Abstract: Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 18, 2014
    Assignee: Panasonic Corporation
    Inventor: Kenji Yoneda
  • Publication number: 20140312471
    Abstract: A semiconductor device has a plurality of closely spaced fins each coated at its top and sidewalls with a SiGe layer used for improving charge carrier mobility in a channel portion of the device. The sidewalls of the closely adjacent Fins are selectively thinned so as to prevent an undesired bridging of SiGe material between immediately adjacent ones of the Fins. A method of manufacturing the same comprises: providing a substrate having a plurality of tri-gate transistors, at least two fins of the tri-gate transistors being closely adjacent to each other, where respective top and sidewall surfaces of the fins are coated with a SiGe layer; performing a tilted ion implantation on the SiGe coated fins so as to partially convert the SiGe material into a predetermined etch resistant material (e.g., and oxide of the SiGe); and etching away the non-converted sidewall parts of the SiGe coating layers so as to provide greater spacing between the immediately adjacent sidewalls of the SiGe coated fins.
    Type: Application
    Filed: February 13, 2014
    Publication date: October 23, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: James HONG
  • Publication number: 20140291807
    Abstract: A semiconductor device includes a substrate, a first well of a first conductivity type formed within the substrate, a second well of a second conductivity type formed underneath the first well within the substrate and a third well of the second conductivity type formed horizontally to the first well within the substrate, and including a first region formed to a first depth from a surface of the substrate, and a second region formed to a second depth greater than the first depth from the surface of the substrate and connected to the second well.
    Type: Application
    Filed: March 12, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Junichi Ariyoshi
  • Patent number: 8835269
    Abstract: A method of manufacturing a solid-state image sensor having photoelectric conversion elements and one or more MOS transistors are formed on a semiconductor substrate is provided. The method includes forming a resist pattern having an opening and a shielding portion over the substrate; and implanting ions in the substrate through the opening. When the substrate is viewed from a direction, an isolation region that is positioned between accumulation regions adjacent to one another is exposed in the opening, and when viewed from a different direction, a channel region of the MOS transistors is exposed in the opening, and the isolation region is shielded by the shielding portion. Ions irradiated in the direction are implanted in the isolation region, and ions irradiated in the different direction are implanted in the channel region.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 16, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mahito Shinohara, Junji Iwata
  • Patent number: 8790970
    Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Ping-Wei Wang, Hao-Yu Chen, Fu-Liang Yang, Chenming Hu
  • Patent number: 8772102
    Abstract: One illustrative method disclosed herein involves forming an etch stop layer above a plurality of sacrificial gate structures, performing an angled ion implant process to implant an etch-inhibiting species into less than an entirety of the etch stop layer, and forming a layer of insulating material above the etch stop layer. The method further includes removing the sacrificial gate structures, forming replacement gate structures, forming a hard mask layer above the replacement gate structures and layer of insulating material, forming a patterned hard mask layer, performing another etching process through the patterned hard mask layer to define an opening in the layer of insulating material to expose a portion of the etch stop layer, performing another etching process on the exposed portion to define a contact opening therethrough that exposes a doped region and forming a conductive contact in the opening that is conductively coupled to the doped region.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: July 8, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Min-Hwa Chi
  • Patent number: 8772142
    Abstract: An ion implantation method includes reciprocally scanning an ion beam, mechanically scanning a wafer in a direction perpendicular to the ion beam scanning direction, implanting ions into the wafer, and generating an ion implantation amount distribution in a wafer surface of an isotropic concentric circle shape for correcting non-uniformity in the wafer surface in other semiconductor manufacturing processes, by controlling a beam scanning speed in the ion beam scanning direction and a wafer scanning speed in the mechanical scanning direction at the same time and independently using the respective control functions defining speed correction amounts.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 8, 2014
    Assignee: SEN Corporation
    Inventors: Shiro Ninomiya, Tetsuya Kudo, Akihiro Ochi
  • Patent number: 8765583
    Abstract: An improved method of tilting a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. The mask and substrate are tilted at a first angle relative to the incoming ion beam. After the substrate is exposed to the ion beam, the mask and substrate are tilted at a second angle relative to the ion beam and a subsequent implant step is performed. Through the selection of the aperture size and shape, the cross-section of the mask, the distance between the mask and the substrate and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 1, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Benjamin Riordon, Nicholas Bateman, Atul Gupta
  • Patent number: 8765557
    Abstract: A first layer constituting a first surface of a silicon carbide layer and of a first conductivity type is prepared. An internal trench is formed at a face opposite to the first surface of the first layer. Impurities are implanted such that the conductivity type of the first layer is inverted on the sidewall of the internal trench. By the implantation of impurities, there are formed from the first layer an implantation region located on the sidewall of the internal trench and of a second conductivity type, and a non-implantation region of the first conductivity type. A second layer of the first conductivity type is formed, filling the internal trench, and constituting the first region together with the non-implantation region.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Hayashi, Takeyoshi Masuda
  • Patent number: 8735266
    Abstract: A fin field-effect transistor (FinFET) includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region uniformly beneath a top surface and sidewall surfaces of the fin structure, the LDD region having a depth less than about 25 nm. Another FinFET includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region, and a top surface of the fin structure has a different crystal structure from a sidewall surface of the fin structure. A method of making a FinFET includes forming a fin structure on a substrate. The method further includes performing a pulsed plasma doping on the fin structure to form lightly doped drain (LDD) regions in the fin structure.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ming Wu, Yu Lien Huang, Chun Hsiung Tsai
  • Patent number: 8716086
    Abstract: A first layer constituting a first surface of a silicon carbide layer and of a first conductivity type is prepared. An internal trench is formed at a face opposite to the first surface of the first layer. Impurities are implanted such that the conductivity type of the first layer is inverted on the sidewall of the internal trench. By the implantation of impurities, there are formed from the first layer an implantation region located on the sidewall of the internal trench and of a second conductivity type, and a non-implantation region of the first conductivity type. A second layer of the first conductivity type is formed, filling the internal trench, and constituting the first region together with the non-implantation region.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Hayashi, Takeyoshi Masuda
  • Patent number: 8709928
    Abstract: An angled implantation process is used in implanting semiconductor fins of a semiconductor device and provides for covering some but not necessarily all of semiconductor fins of a first type with patterned photoresist, and implanting using an implant angle such that all semiconductor fins of a second type are implanted and none of the semiconductor fins of the first type, are implanted. A higher tilt or implant angle is achieved due to the reduced portions of patterned photoresist, that are used.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang
  • Patent number: 8703592
    Abstract: Provided are methods of forming semiconductor devices. A method may include preparing a semiconductor substrate including a first region and a second region adjacent the first region. The method may also include forming sacrificial pattern covering the second region and exposing the first region. The method may further include forming a capping layer including a faceted sidewall on the first region using selective epitaxial growth (SEG). The faceted sidewall may be separate from the sacrificial pattern. The sacrificial pattern may be removed. Impurity ions may be implanted into the semiconductor substrate.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-Sun Kim, Dong-Suk Shin, Dong-Hyuk Kim, Yong-Joo Lee, Hoi-Sung Chung
  • Publication number: 20140097517
    Abstract: In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, UIS performance.
    Type: Application
    Filed: September 20, 2013
    Publication date: April 10, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Peter Moens, Ana Villamor, Piet Vanmeerbeek, Jaume Roig-Guitart, Filip Bogman
  • Patent number: 8669160
    Abstract: A method for manufacturing a semiconductor device is provided. The method comprises providing a semiconductor substrate; forming a dummy gate structure and a spacer surrounding the dummy gate structure on the semiconductor substrate; forming source/drain regions on both sides of the gate structure within the semiconductor substrate using the dummy gate structure and the spacer as a mask; forming an interlayer dielectric layer on the upper surface of the semiconductor substrate, the upper surface of the interlayer dielectric layer being flush with the upper surface of the dummy gate structure; removing at least a part of the dummy gate structure so as to form a trench surrounded by the spacer; performing tilt angle ion implantation into the semiconductor substrate using the interlayer dielectric layer and spacer as a mask so as to form an asymmetric Halo implantation region; sequentially forming a gate dielectric layer and a metal gate in the trench.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: March 11, 2014
    Assignee: The Institute of Microelectronics, Chinese Academy of Science
    Inventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu, Da Yang
  • Patent number: 8669170
    Abstract: Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: March 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ricardo P. Mikalo, Stefan Flachowsky
  • Patent number: 8664100
    Abstract: A first facet of each of a plurality of pyramids on a surface of a workpiece is doped to a first dose while a second facet and a third facet of each of the plurality of pyramids is simultaneously doped to a second dose different than the first dose. The first facets may enable low resistance contacts and the second and third facets may enable higher current generation and an improved blue response. Ion implantation may be used to perform the doping.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: March 4, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Atul Gupta
  • Patent number: 8647970
    Abstract: An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow RDSON to be lower for a given BVDSS.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: February 11, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Prasad Venkatraman
  • Patent number: 8642456
    Abstract: A method and structures are provided for implementing semiconductor signal-capable capacitors with deep trench and Through-Silicon-Via (TSV) technologies. A deep trench N-well structure is formed and an implant is provided in the deep trench N-well structure with a TSV formed in a semiconductor chip. At least one angled implant is created around the TSV in a semiconductor chip. The TSV is surrounded with a dielectric layer and filled with a conducting material which forms one electrode of the capacitor. A connection is made to one implant forming a second electrode to the capacitor.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Philip R. Germann, John E. Sheets, II
  • Patent number: 8643107
    Abstract: In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey W. Sleight, Chung-Hsun Lin, Josephine B. Chang, Leland Chang
  • Patent number: 8623718
    Abstract: In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng Yuan, Tsung-Lin Lee, Shao-Ming Yu, Clement Hsingjen Wann
  • Patent number: 8598007
    Abstract: One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: December 3, 2013
    Assignee: Globalfoundries Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8598006
    Abstract: An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: December 3, 2013
    Assignees: International Business Machines Corporation, Toshiba America Electronic Components, Inc.
    Inventors: Joel P. de Souza, Masafumi Hamaguchi, Ahmet S. Ozcan, Devendra K. Sadana, Katherine L. Saenger, Donald R. Wall
  • Publication number: 20130299899
    Abstract: The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this.
    Type: Application
    Filed: November 6, 2012
    Publication date: November 14, 2013
    Applicant: MaxPower Semiconductor, Inc
    Inventors: Amit Paul, Mohamed N. Darwish
  • Publication number: 20130288468
    Abstract: One illustrative method disclosed herein involves forming an etch stop layer above a plurality of sacrificial gate structures, performing an angled ion implant process to implant an etch-inhibiting species into less than an entirety of the etch stop layer, and forming a layer of insulating material above the etch stop layer. The method further includes removing the sacrificial gate structures, forming replacement gate structures, forming a hard mask layer above the replacement gate structures and layer of insulating material, forming a patterned hard mask layer, performing another etching process through the patterned hard mask layer to define an opening in the layer of insulating material to expose a portion of the etch stop layer, performing another etching process on the exposed portion to define a contact opening therethrough that exposes a doped region and forming a conductive contact in the opening that is conductively coupled to the doped region.
    Type: Application
    Filed: April 25, 2012
    Publication date: October 31, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Min-Hwa Chi
  • Patent number: 8569185
    Abstract: A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Hui Ouyang, Han-Pin Chung, Shiang-Bau Wang
  • Patent number: 8569154
    Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
  • Publication number: 20130234201
    Abstract: A field stop structure is disclosed. The field stop structure is divided into a three-dimensional structure by a plurality of trenches formed on a back side of a silicon substrate and hence obtains a greater formation depth in the substrate and can achieve a higher ion activation efficiency. Moreover, a first electrode region of a fast recovered diode (FRD) is formed in the trenches, thereby enabling the integration of a FRD with an insulated gate bipolar transistor (IGBT) device. Methods for forming field stop structure and reverse conducting IGBT semiconductor device are also disclosed.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 12, 2013
    Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventor: Shengan Xiao
  • Patent number: 8519403
    Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: August 27, 2013
    Assignee: Altera Corporation
    Inventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
  • Patent number: 8513103
    Abstract: A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and a second side surface in the opposite side of the first side surface; forming a one side contact mask having an opening which selectively opens a portion of the first side surface of the wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer by diffusing impurities having different diffusivities into the portion of the first side surface exposed to the opening.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: August 20, 2013
    Assignee: SK Hynix Inc.
    Inventors: Eun Shil Park, Yong Seok Eun, Kyong Bong Rouh
  • Patent number: 8513105
    Abstract: An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: August 20, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Charles Baldwin, James Walter Blatchford
  • Patent number: 8492252
    Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
  • Patent number: 8492250
    Abstract: A method for forming a polysilicon layer includes forming an amorphous silicon layer over a substrate, performing a first thermal treatment of the amorphous silicon layer by performing an implantation with a gas that includes silicon (Si), and performing a second thermal treatment on the thermally treated layer at a temperature higher than a temperature of the first thermal treatment.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: July 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun-Jung Ko
  • Publication number: 20130183817
    Abstract: Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.
    Type: Application
    Filed: January 16, 2012
    Publication date: July 18, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ricardo P. Mikalo, Stefan Flachowsky
  • Publication number: 20130161725
    Abstract: A semiconductor memory device includes conductive films and insulating layers alternately stacked on a substrate, substantially vertical channel layers penetrating the conductive films and the insulating layers, multilayer films including a charge storage film interposed between the conductive films and the substantially vertical channel layers, and a first anti-diffusion film formed on etched surfaces of the conductive films.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 27, 2013
    Applicant: SK HYNIX INC.
    Inventors: Yong Dae PARK, Ga Hee LEE
  • Patent number: 8470677
    Abstract: Gate electrodes are formed in a high speed transistor forming region, a low leakage transistor forming region, and a medium voltage transistor forming region, respectively. Thereafter, a photoresist film covering the medium voltage transistor forming region is formed. Then, ions of an impurity are implanted into a semiconductor substrate while using the photoresist film and the gate electrodes as a mask, and p-type pocket regions, extension regions, and impurity regions are thereby formed. Subsequently, another photoresist film covering the high speed transistor forming region is formed. Then, ions of an impurity are implanted into the semiconductor substrate while using the other photoresist film and the gate electrodes as a mask, and impurity regions and extension regions are thereby formed.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: June 25, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Junichi Ariyoshi
  • Patent number: 8450195
    Abstract: The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: May 28, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Jing Chen, Xiaolu Huang, Jiexin Luo, Qingqing Wu, Xi Wang
  • Patent number: 8426324
    Abstract: A method for manufacturing a memory element is proposed. A laser beam emitted from a laser oscillator is entered into a deflector, and a laser beam which has passed through the deflector is entered into a diffractive optical element to be diverged into a plurality of laser beams. Then, a photoresist formed over an insulating film is irradiated with the laser beam which is made to diverge into the plurality of laser beams, and the photoresist irradiated with the laser beam is developed so as to selectively etch the insulating film.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Hirotada Oishi