Abstract: A method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; forming gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions; etching the gate oxide lines and the field oxide regions between the gate lines; and forming a self-aligned source (SAS) region by injecting impurity ions into the etched regions, the impurity ion being injected in a direction at a predetermined angle other than 90° relative to the semiconductor substrate.

Abstract: A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.

Abstract: Semiconductors having electrically coupled gate and impurity doped regions and methods for fabricating the same are provided. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and an impurity doped region within the substrate. A first spacer is formed on a first side and a second spacer on a second side of the gate electrode. An ion is implanted into the first spacer with an angle greater than zero from an axis perpendicular to the surface of the substrate. The first spacer is etched to remove a portion thereof and a silicon film is deposited overlying a remainder of the first spacer, the impurity doped region and the second spacer. The silicon film is etched, forming a silicon spacer, and a silicide-forming metal is deposited to form a silicide contact that electrically couples the gate electrode and the impurity doped region.

Abstract: Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.

Abstract: When the second harmonic of a YAG laser is irradiated onto semiconductor films, concentric-circle patterns are observed on some of the semiconductor films. This phenomenon is due to the non-uniformity of the properties of the semiconductor films. If such semiconductor films are used to fabricate TFTs, the electrical characteristics of the TFTs will be adversely influenced. A concentric-circle pattern is formed by the interference between a reflected beam 1 reflected at a surface of a semiconductor film and a reflected beam 2 reflected at the back surface of a substrate. If the reflected beam 1 and the reflected beam 2 do not overlap each other, such interference does not occur. For this reason, a laser beam is obliquely irradiated onto the semiconductor film to solve the interference. The properties of a crystalline silicon film formed by this method are uniform, and TFTs which are fabricated by using such crystalline silicon film have good electrical characteristics.

Abstract: Disclosed are methods of forming a halo region in n-channel type MOS (NMOS) transistors. In one example, the method includes forming, on a channel region of a semiconductor substrate, a structure having a gate insulation film pattern and a gate conductive film pattern stacked sequentially; forming an ion implantation buffer film on an exposed surface of the semiconductor substrate and the gate conductive film pattern; performing a first ion implantation process for injecting fluorine ions into the semiconductor substrate; performing a second ion implantation process for implanting p-type halo ions into the semiconductor substrate; performing a third ion implantation process for implanting n-type impurity ions into the semiconductor substrate; and diffusing the p-type halo ions and the n-type impurity ions using a thermal process.

Abstract: Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor gate and an asymmetric transistor gate on a substrate. The symmetric and asymmetric transistor gates are substantially perpendicular. A mask is formed on the substrate with a first opening and a second opening. The first opening is sized to enable implantation of first and second halo regions beneath the symmetric transistor gate. The second opening is sized to enable implantation of a third halo region beneath and on one but not both sides of the asymmetric gate. The first and second halo regions are formed beneath the first gate by implanting through the first opening toward opposite sides of the symmetric gate. The third halo region is formed beneath and proximate one but not both sides of the asymmetric transistor gate by implanting through the second opening.

Abstract: A method for fabricating a body-tied SOI transistor with reduced body resistance is presented. During the wafer fabrication process, a semiconductor wafer is placed in an ion implantation device and oriented to a first position relative to a beam path of the ion implantation device in order to obtain a substantially non-orthogonal twist orientation between the beam path and the transistor gate edge. Following this orientation of the first position, an ion species is implanted into a first implantation region. The wafer is then rotated to a second substantially non-orthogonal twist orientation, where another ion implantation is conducted. This process continues in the same manner, such that further substantially non-orthogonal twists and ion implantations are conducted, until the desired number of implantation areas is created. Halo or pocket implants are an example of the type of implantations to which the technique may be applied.

Abstract: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell.

Abstract: Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.

Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

Abstract: A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region and form a trench, and performing a selective epitaxial growth to fill epitaxial crystal into the trenches, thereby forming a source/drain of the MOS transistor.

Abstract: A process is provided for forming an isolating nitride film to isolate gate polysilicon of a gate structure. Specifically, the process comprises providing a channel region defined by a source and drain region of a semiconductor substrate having a gate structure comprising an isolating oxide layer positioned on the channel region and the polysilicon layer positioned on the oxide layer. More specifically, the process comprises the steps of forming the nitrogen implanted regions over the semiconductor substrate by implanting nitrogen atoms into those regions and growing spacers from exposed portions of the polysilicon layer. During the spacer growth, the spacer grows vertically as well as laterally extending under the polysilicon edges. Diffusion of nitrogen atoms to the substrate surface forms silicon nitride under the gate edges, which minimizes current leakages into gate polysilicon.

Abstract: An impurity having a conductivity type same as that contained in a source-and-drain region is implanted to an exposed surface of a gate electrode along a direction inclined to the surface of said semiconductor substrate, while using over-etched sidewalls as a mask, where the gate electrode is implanted both at the top surface and the upper portion of one side face thereof, whereas one of the source-and-drain regions is implanted with the impurity in an amount possibly attained by a single implantation, but the other portion is not implanted or only slightly implanted to a less affective degree.

Abstract: MOSFETs with pocket regions are fabricated. A gate electrode layer is formed on a semiconductor substrate; and lightly doped drain regions are formed in the semiconductor substrate adjacent the gate electrode layer. A blocking pattern is formed on the semiconductor substrate where the gate electrode layer is formed. The blocking pattern is adjacent and spaced apart from the gate electrode layer a predetermined distance and exposes portions of the semiconductor substrate adjacent sidewalls of the gate electrode layer. Pocket regions are formed in the semiconductor substrate by implanting impurity ions using the gate electrode layer and the blocking pattern as an ion implantation mask.

Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.

Abstract: A method for forming a plurality of MOSFETs wherein each one of the MOSFET has a unique predetermined threshold voltage. A doped well or tub is formed for each MOSFET. A patterned mask is then used to form a material line proximate each semiconductor well, wherein the width of the line is dependent upon the desired threshold voltage for the MOSFET. A tilted ion implantation is performed at an acute angle with respect to the substrate surface such that the ion beam passes through the material line. Thicker lines have a lower transmission coefficient for the ion beam and thus the intensity of the ion beam reaching the adjacent semiconductor well is reduced. By appropriate selection of the line width the dopant density in the well, and thus the final MOSFET threshold voltage, is controllable.

Abstract: A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).

Abstract: A manufacturing apparatus of a semiconductor device is disclosed, which comprises an implantation source which applies particles or an electromagnetic wave into an implantation region of a semiconductor substrate in a ? direction shifted by an angle ? from a vertical direction of the semiconductor substrate, a first stencil mask disposed between the semiconductor substrate and the implantation source, the first stencil mask having a first opening corresponding in the ? direction to the implantation region, and a second stencil mask disposed between the first stencil mask and the implantation source, the second stencil mask having a second opening corresponding in the ? direction to the implantation region.

Abstract: Transistor of semiconductor device and method for manufacturing the same are disclosed. The transistor comprises a channel region formed on a sidewall of a silicon fin extruding above a device isolation region. The silicon fin serves as an active region and is shorter in length so as to be spaced apart from an adjacent gate electrode. The width of the channel region is determined by the height of the silicon fin. The source/drain region of the transistor is disposed at an upper surface and the sidewall of the silicon fin to increase the contact region.

Abstract: A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region of at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from said top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanting into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.

Abstract: A method is provided for fabricating a MOSFET device. The method begins by forming a semiconductor device having a substrate on which a gate conductor having sidewalls separates a source region and a drain region. An oxide layer is formed over the gate sidewalls and a portion of the substrate. Ions of a first conductivity are implanted into the source and the drain regions to define source and drain extensions that respectively extend in part under the gate conductor. A nitride layer is formed over the oxide layer that extends over the portion of the substrate. An angled ion implant is performed during which the gate conductor shields a portion of the nitride layer over at least a portion of the drain region from damage by the angled ion implant. The angled ion implant selectively damages portions of the nitride layer in which ions are implanted to form damaged portions of the nitride layer.

Abstract: This invention provides a semiconductor device with an element isolation implemented by a method of manufacturing a semiconductor device comprising the steps of: forming a pad oxide film 140 and a nitride film 150 sequentially on a silicon layer 130 in an element region S; forming a metal oxide film 180 for generating a fixed electric charge on the nitride film 150 and on the silicon layer 130 in an element isolation region A; forming a field oxide film 160 in the element isolation region A by implementing an oxidation treatment; and removing the metal oxide film 180 on the nitride film 150, the nitride film 150 and the pad oxide film 140. In the semiconductor device, the threshold voltage of a parasitic transistor is made high and prevented from turning on, and the influence of leak current is reduced and the hump characteristic of element is restrained.

Abstract: The present invention relates to a method for fabricating a complementary metal oxide semiconductor (CMOS) image sensor, wherein a mini-p-well is stably formed in a pixel region being correspondent to a trend of large scale of integration. The method includes the steps of: preparing a substrate defined with a peripheral region and a pixel region; performing a first ion-implantation process by using a first photoresist having a first thickness to thereby form a normal first conductive well in the pixel region; and performing a second ion-implantation process by using a second photoresist having a second thickness to thereby form a mini-well of the first conductive type in the peripheral region, wherein the first thickness is greater than the second thickness.

Abstract: A method of fabricating a chalcogenide random access memory (CRAM) is provided. The method is to provide a substrate having a bottom electrode thereon and then form a chalcogenide film and a patterned mask corresponding to the bottom electrode sequentially over the substrate. Thereafter, using the patterned mask, an ion implantation is performed to convert a portion of the chalcogenide film into a modified region while the chalcogenide film underneath the patterned mask is prevented from receiving any dopants and hence is kept as a non-modified region. The modified region has a lower conductivity than the non-modified region. After that, the patterned mask is removed and then a top electrode is formed over the non-modified region. Utilizing the ion implantation as a modifying treatment, the contact area between the chalcogenide film and the bottom electrode is decreased and the operating current of the CRAM is reduced.

Abstract: Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.

Abstract: A method of forming a contact opening is provided. First, a substrate having a plurality of conductive structures formed thereon is provided. An ion implantation is performed. Thereafter, a thermal treatment is carried out to form a liner layer on the sidewall of the conductive structure and the exposed substrate. The liner layer on the sidewall of the conductive structure has a thickness smaller than the liner layer on the substrate surface. A spacer is formed on each side of the conductive structure and then an insulation layer is formed over the substrate. The insulation layer is patterned to form a contact opening between two neighboring conductive structures. Since the liner layer on the sidewall of the conductive structures is already quite thin, there is no need to reduce thickness through an etching operation and uniformity of the liner layer on the substrate can be ensured.

Abstract: Disclosed is a method of manufacturing a semiconductor device. A monoatomic dopant having a high atomic weight is implanted to form an ion implantation layer, instead of using a dopant of a small atomic weight such as B or a molecular ion such as a BF2 in order to control the threshold voltage of the semiconductor device. Therefore, in an annealing process for mitigating damage caused by ion implantation, it is possible to limit TED (transient enhanced diffusion) of the dopant and prevent degradation of the film quality due to outgasing.

Abstract: In a method of producing a doped semiconductor structure with a trench, it is possible to set the doping of the trench side walls independently from the doping of the trench bottom, and to set different doping concentrations of the individual trench side walls relative to each other. In the method, a mask layer with a window therein is provided on a surface of a semiconductor body, and then a first doping step, a trench etching step, and a second doping step are carried out successively through this window while this one mask layer remains in place on the surface of the semiconductor body. Further etching and doping steps can be carried out successively also through this window of the mask layer.

Abstract: A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle ?+? with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle ? with respect to vertical of a dopant into the channel below the source.

Abstract: A method of manufacturing a semiconductor device is disclosed which comprises, forming a first well region by performing an ion implantation process for implanting first ions into a semiconductor substrate, and then forming a second well region in the first well region by performing an ion implantation process for implanting second ions having larger mass than the first ions; and forming a three-part or three-fold well region by performing an annealing process on the result structure wherein the lighter first ions are disposed in the upper and lower well regions and the heavier second ions are disposed in the middle well region.

Abstract: A memory comprises a gate oxide layer formed on a semiconductor substrate; an ion trap region formed in a corner portion of the gate oxide layer; a floating gate formed on the gate oxide layer; a dielectric layer formed on the floating gate; a control gate formed on the dielectric layer; a spacer provided along side walls of a formed gate; an LDD formed under the spacer on the semiconductor substrate, the LDD being doped at a low concentration with impurities; and a source/drain region formed on an element region of the semiconductor substrate contacting the LDD, the source/drain region being doped at a high concentration with impurities. In one embodiment, the ion trap region is formed by performing ion injection into a corner portion of the gate oxide after the gate, including the control gate and the floating gate, is formed.

Abstract: An electrooptical substrate device has pixel electrodes and pixel-switching TFTs connected thereto, on a substrate. The TFT is a P-channel TFT of an SOI structure that does not have a body contact. Due to this, a transistor is architected in each pixel that is suited to broaden the opening area in each pixel, and having comparatively high performance, thereby enabling bright, high-quality image display.

Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.

Abstract: A method for forming an isolation layer of a semiconductor device. The method includes: a) sequentially laminating a pad oxide layer and pad nitride layer on a semiconductor substrate; b) selectively removing the pad nitride layer, selectively removing the pad oxide layer and the substrate, thereby forming a trench in the substrate; c) implanting ions in a direction with a tilted angle into a side wall of the pad nitride layer located in an upper side of the trench; d) removing the side wall portion of the pad nitride layer in the trench, in which the ions are implanted, to form a sloped side wall of the pad nitride layer, wherein the sloped side wall is inclined in an inverse direction; e) filling a HDP oxid layer in an upper surface of an entire structure including the trench; f) planarizing the HDP oxide layer and the pad nitride layer; and g) removing a remaining pad nitride layer, thereby forming an isolation layer.

Abstract: Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor and an asymmetric transistor on a substrate. A first mask is formed on the substrate with a first opening to enable implantation formation of first and second halo regions proximate first and second source/drain regions of the symmetric transistor. First and second halo regions of a first dosage are formed beneath the first gate by implanting off-axis through the first opening. A second mask is formed on the substrate with a second opening to enable implantation formation of a third halo region proximate a source region of the second asymmetric transistor while preventing formation of a halo region proximate a drain region of the asymmetric transistor. A third halo region of a second dosage greater than the first dosage is formed by implanting off-axis through the second opening.

Abstract: A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.

Abstract: A method for forming contact openings in various locations of the upper surface of an integrated circuit having raised areas, critical openings having to be formed between two neighboring raised areas, including the steps of covering the entire structure with a first protection layer; forming non-critical openings in the first protection layer; coating the structure with a second protection layer; performing an oblique irradiation so that the second protection layer is not irradiated at the bottom of the regions located between two raised areas; removing the non-irradiated portions of the second protection layer; removing the portions of the first protection layer located under the second protection layer at the locations where this second protection layer has been removed; and removing the irradiated portions of the second protection layer.

Abstract: A gate structure (4), an LDD region (6) and a sidewall (7) are provided in this order. Arsenic ions (8) are thereafter implanted into the upper surface of a silicon substrate (1) by tilted implantation. The next step is annealing for forming an MDD region (9) in the upper surface of the silicon substrate (1). The MDD region (9) and the gate structure (4) do not overlap one another in plan view. Further, the MDD region (9) formed into a depth shallower than that of the LDD region (6) is higher in concentration than the LDD region (6). Thereafter a source/drain region (11) higher in concentration than the MDD region (9) is provided by vertical implantation into a depth greater than that of the LDD region (6).

Abstract: An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n? source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

Abstract: A semiconductor device includes doped regions of a substrate spaced at selected distances from features at an upper surface of the substrate. According to an example embodiment of the present invention, the doped regions are implanted and spaced apart from the features with the height of the features and the angle of an implant used for implanting the doped regions setting the space between the doped regions and the features. In one implementation, the height of the features is varied (e.g., with the features being defined using different steps, such as photolithography) to set the spacing of different doped regions. In another implementation, the angle of the implant is varied to set the spacing for different doped regions. In still another implementation, both the height of the features and angle of the implant are varied to set the spacing for different doped regions.

Abstract: A method for fabricating a body-tied SOI transistor with reduced body resistance is presented. During the wafer fabrication process, a semiconductor wafer is placed in an ion implantation device and oriented to a first position relative to a beam path of the ion implantation device in order to obtain a substantially non-orthogonal twist orientation between the beam path and the transistor gate edge. Following this orientation of the first position, an ion species is implanted into a first implantation region. The wafer is then rotated to a second substantially non-orthogonal twist orientation, where another ion implantation is conducted. This process continues in the same manner, such that further substantially non-orthogonal twists and ion implantations are conducted, until the desired number of implantation areas is created. Halo or pocket implants are an example of the type of implantations to which the technique may be applied.

Abstract: A hard mask 21a which has an opening for exposing a p-type region 2 defined in a silicon substrate 1 and is made of, for example, a BPSG film is formed. Then, the hard mask 21a is subjected to isotropic etching using argon gas, to have its edge rounded off, thereby forming an implantation hard mask 21 having a tapered edge. Subsequently, large-angle-tilt ion implantation of an n-type impurity is performed using the implantation hard mask 21 as a mask, thereby forming an n− layer 13 having an LDD structure. Thereafter, the implantation hard mask 11 is removed. In this manner, it is possible to perform large-angle-tilt ion implantation using an implantation mask thinner than a conventional implantation mask.

Abstract: A semiconductor memory device comprises a trench etched from a substrate below a shallow trench isolation and a doped collar oxide. The device further comprises a buried-strap junction formed adjacent to the shallow trench isolation and above the collar oxide, and a channel stop formed below the buried-strap junction, wherein a junction between the channel stop and the buried-strap junction is formed in the substrate.

Abstract: When an opening diameter of a top end of a substantially column-shaped contact hole is S1, an opening diameter of a top end of a substantially column-shaped contact hole is T1, and a thickness of a silicon insulating layer is h, then contact holes are formed so as to satisfy the following conditional expression 1. T1/h<tan &thgr;1<S1/h (expression 1). With this formation method, a manufacturing method of a semiconductor device can be provided which does not need covering processing using a photolithography technique when impurity regions of different conductivity types are formed using contact holes.

Abstract: In a manufacturing method of a thin-film transistor having a polycrystalline Si film as its active region, an amorphous-phase Si film is first formed, and pulse laser beams are irradiated to crystallize the Si film and thereby form a polycrystalline Si film. After electrodes are made on a source region and a drain region, a SiNx film as a hydrogen-containing film is formed on the entire surface. By irradiating pulse laser beams to heat the SiNx film, hydrogen in the SiNx film is diffused into the polycrystalline Si film to hydrogenate it and reduce the trap density along crystal grain boundaries in the polycrystalline Si film.

Abstract: In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Abstract: A method of fabricating a semiconductor device forms a shallow source/drain region after a deep source/drain region. First, a gate insulating layer including a gate pattern and a gate electrode are formed on a semiconductor substrate. A buffer insulating layer, a first insulating layer, and a second insulating layer are then sequentially formed on the entire surface of the gate pattern and the semiconductor substrate. A first spacer is formed on the first insulating layer at both sidewalls of the gate pattern by etching the second insulating layer. A deep source/drain region is then formed on the semiconductor substrate as aligned by the first spacer. The first spacer is removed. Next, an offset spacer is formed at both sidewalls of the gate pattern by etching the first insulating layer. Finally, a shallow source/drain region is formed on the semiconductor substrate adjacent to the deep source/drain region as aligned by the offset spacer.

Abstract: The present invention relates to a method for fabricating a semiconductor transistor device. The method comprises: forming a first conductive type well in a semiconductor substrate having a device isolation film formed thereon; implanting first conductive type impurity ions into the first conductive type well, so as to form a punch-through stopper region; implanting the first conductive type impurity ions into the upper portion of the resulting structure at fixed tilt angle and ion implantation energy, so as to form a channel region; forming a gate electrode including a gate insulating film on the semiconductor substrate; forming LDD regions in the semiconductor substrate at both sides of the gate electrode; forming an insulating spacer film on the side of the gate electrode; and forming source and drain regions in the semiconductor substrate at portions below the sides of the insulating spacer films.

Abstract: A method for fabricating a bipolar transistor includes: a first step of implanting, along the normal direction of the principle surface of a first-conductive-type semiconductor single crystalline substrate, ions of a second-conductive-type first impurity into the semiconductor single crystalline substrate to form a second-conductive-type collector layer; a second step of implanting, along the direction tilted from the normal direction, ions of a second-conductive-type second impurity into the semiconductor single crystalline substrate at a higher injection energy than that in the ion implantation of the first step to form a buried collector layer in a lower portion of the collector layer; and a third step of forming each of a first-conductive-type base layer and a second-conductive-type emitter layer in a predetermined region of a surface portion of the collector layer.