Abstract: A method for forming wells of a semiconductor device, comprising the steps of forming a plurality of field insulating layers on a field region of a semiconductor substrate; forming first impurity regions of a first conductive type at a first depth beneath a surface of the semiconductor substrate; forming first impurity regions of a second conductive type beneath the surface of the semiconductor substrate at a second depth between the field insulating layers; selectively forming second impurity regions of the second conductive type in the first impurity regions of the first conductive type between adjacent field insulating layers; forming second impurity regions of the first conductive type in the first impurity regions of the second conductive type at both sides of the second impurity regions of the second conductive type; and diffusing the first and second impurity regions of the first conductive type and the first and second impurity regions of the second conductive type by a drive-in process to form a firs

Abstract: A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.

Abstract: A semiconductor device having an electrostatic discharge protection device and at least one accompanying device selected from the group comprising of a N or P channel MOS transistor, CMOS, bipolar transistor and BiCMOS, in which the electrostatic discharge protection device comprises a vertical type bipolar transistor including; a semiconductor substrate; an epitaxial layer laminated on the semiconductor substrate; a buried collector of a first conductivity type which is formed of the semiconductor substrate or which is formed from the surface of the semiconductor substrate to the epitaxial layer; a base of a second conductivity type which is a lightly doped well and formed on the epitaxial layer; and an emitter of the first conductivity type and formed on the surface layer of the base of the second conductivity type; and in which the base is adapted to have impurity concentration and depth so that a punch-through is generated between the emitter and the collector of the electrostatic discharge protection dev

Abstract: In the manufacture of an MOS gated semiconductor device, indentations are provided on a surface of a semiconductor wafer extending inwardly of respective spaced apart regions at the wafer surface having doping concentrations greater than that present in the remainder of the wafer. A layer of silicon having a doping concentration less than that of the substrate is conformally provided on the substrate surface whereby the indentations in the substrate surface are replicated on the surface of the silicon layer. Dopants in the substrate regions are then out-diffused into the silicon layer to provide highly doped buried regions within the layer. Then, using the silicon layer surface indentations as photomask alignment marks, gate electrode structures are formed on and within the silicon layer in preselected orientation relative to the buried regions. The buried regions provide low resistance paths for current through the resulting devices.

Abstract: A method for fabricating a CMOS device having BILLI (buried implanted layers for lateral isolation) structure capable of effectively preventing latch-up is disclosed, having the following steps. A mask pattern is formed on the semiconductor substrate of a predetermined conductivity type to expose a region where the MOS transistor, having a same conductivity type as that of the substrate, is to be formed wherein the mask pattern has a vertical boundary face having a gradual slope. A buried layer is then formed in the form of island by ion-implanting the impurity ions into the substrate to pass through the mask pattern, the buried layer having a same conductivity type as that of the substrate, and being formed to be continuous under the vertical boundary face of the mask pattern.

Abstract: A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.

Abstract: There is disclosed a method of fabricating a semiconductor device having excellent characteristics. The device comprises a substrate having an insulating surface. A hydrogen-rich region is formed inside the substrate by ion doping. Thermal processing is performed at 300 to 450.degree. C. to thermally diffuse hydrogen ions. Thus, dangling bonds and defect levels in an active layer are compensated. Since the hydrogenation from inside the semiconductor device is enabled in this way, hydrogen termination can be performed at a high efficiency.

Abstract: A semiconductor processing method for forming a diffusion region is described and which includes providing a semiconductor substrate; forming a first layer of material over the semiconductor substrate; and after forming the first layer, ion implanting a conductivity modifying impurity through the first layer and into the semiconductor substrate to form a diffusion region therein. In an alternative form, a method for forming a field effect transistor is described and which includes providing a substrate; forming a field oxide region and active area region on the substrate; forming a gate dielectric layer atop the substrate and within the active area region; and after forming the gate dielectric layer, ion implanting a dopant impurity through the field oxide region and into the underlying substrate to form a field implant beneath the field oxide region for facilitating electrical isolation of the field effect transistor from adjacent electrical devices.

Abstract: In a method for manufacturing a charge transfer device, an N type semiconductor region is formed in a principal surface of a P type semiconductor substrate, to constitute a transfer channel of the charge transfer device. A silicon oxide film is formed to over a surface of the N type semiconductor region. Furthermore, a plurality of silicon nitride films are selectively formed on a surface of the silicon oxide film, separated from one another at predetermined intervals. Boron ions are ion-implanted into the N type semiconductor region, using as a mask the silicon nitride films and a photoresist formed to have an end partially overlapping each of the silicon nitride films, so that an N.sup.

Abstract: A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in successive steps the field regions of the P- and N-wells; (ii) creating an oxide layer over the field regions, (iii) creating in successive steps the active regions. The method achieves the P- and N-wells without increasing the number of photoresist masking steps. In addition, optical alignment targets (OATs) are optionally formed simultaneously with these P- and N-wells without increasing the total number of process steps.

Abstract: A method of manufacturing a buried contact is disclosed, wherein a thin silicon oxide layer is formed on the silicon substrate. The thin oxide functions as a gate dielectric. Subsequently, a thin first polysilicon layer is formed on the thin silicon oxide layer. Then, a buried contact opening is defined by a first photoresist mask. The portion of the thin polysilicon layer exposed through the first photoresist mask and the thin silicon oxide layer underneath the exposed thin polysilicon are anisotropically etched to forma buried contact hole. An ion implantation is performed into the substrate throughout the buried contact hole to form an N+region. The first photoresist mask is removed and a layer of undoped silicon oxide is deposited on the entire surface. An anisotropic etching is used to etch the undoped silicon oxide. The etching depth can be controlled by this process. Residual amounts of undoped silicon oxide are retained on the vertical edges of the buried contact hole to act as spacers.

Abstract: A method of forming shallow diffusion layers in a semiconductor substrate is provided wherein the shallow diffusion layers are positioned in the vicinity of edge portions of a gate electrode and laterally extend from source/drain diffusion layers having a bottom level deeper than the shallow diffusion layers. The above method comprises the following steps. Crystal defects are selectively formed at least in predetermined shallow regions positioned in a surface region of the semiconductor substrate and in the vicinity of the edge portions of the gate electrode. The predetermined shallow regions are laterally in contact with impurity-introduced deep regions having been formed. The predetermined shallow regions have a bottom level shallower than the impurity-introduced deep regions.

Abstract: Thin layers of semiconductor material having a high degree of surface uniformity are produced by: implantion of deuterium ions into a body of semiconductor material to form a buried region of high stress, the buried region defining a thin outer region of the body; attaching a stiffening carrier to the thin outer region of the semiconductor body; and heating the body at 350-450 degrees C. to separate the thin outer region. The separated layer is useful in the production of silicon-on-insulator semiconductor devices, and silicon-on-glass devices for liquid crystal display and microwave applications.

Abstract: A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

Abstract: A vertical cavity surface emitting laser having a planar structure, having an implantation or diffusion at the top of the mirror closest to the substrate or at the bottom of the mirror farthest from the substrate, to provide current confinement with the gain region, and having an active region and another mirror formed subsequent to the implantation or diffusion. This structure has an implantation or diffusion that does not damage or detrimentally affect the gain region, and does provide dimensions of current confinement that are accurately ascertained. Alternatively, the implantation or diffusion for current confinement may be placed within the top mirror, and several layers above the active region, still with minimal damage to the gain region and having a well-ascertained current confinement dimension.

Abstract: A field-effect transistor has a source region, a drain region, a gate electrode, and a low resistivity layer. The source and drain regions are of a first conductivity type and formed as surface regions of a semiconductor layer formed on one of an insulating substrate and a semi-insulating substrate. The gate electrode is formed on a channel region between the source region and the drain region. The low resistivity layer serving as a shield layer is disposed underneath and spaced apart from the source, drain and channel regions, and overlaps the source region with an overlap area being larger than an overlap area between the low resistivity layer and the drain region. The arrangement enables the prevention of noise margin reduction and erroneous operation.

Abstract: According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.

Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.

Abstract: To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; forming a second semiconductor layer with a second-conductivity type different from the first-conductivity type on the first semiconductor layer; insulation separating the formed second semiconductor layer into a first semiconductor region and a second semiconductor region by an insulating film; changing the second semiconductor region to the first-conductivity type; forming a pattern of an insulating film or a photoresist film having a hole at a partial area of the first semiconductor region of the semiconductor substrate; and implanting first-conductivity type impurities and second-conductivity type impurities at the first semiconductor region, respectively by use of the formed pattern as a mask, to form a first-conductivity type impurity region contacting wi

Abstract: High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

Abstract: In an NPN bipolar transistor having a special structure in which each impurity region is formed by ion implantation, a width of a base region is significantly reduced, and therefore, current amplification factor hfe is increased, resulting in improvement in performance thereof. Furthermore, a Bi-CMOS transistor can be manufactured using a CMOS process. The use of the bipolar transistor having a special structure for a driving circuit allows implementation of a driving circuit having large driving force with slight increase in cost.

Abstract: A process is described for forming a heavily doped buried element below an active device region of a silicon wafer without the use of costly epitaxial layers and without incurring ion implantation damage within active device regions. The method is particularly applicable to active device regions which have small lateral dimensions. Thus, the technological trend towards shrinking devices favors the incorporation of the process of the invention. The process utilizes a silicon nitride hardmask to define a narrow band around the perimeter of the device active area. A deep implant is performed through this mask, placing a ring of dopant below and outside the active area. The silicon nitride hardmask is then patterned a second time to define the conventional field oxide isolation regions. The LOCOS field oxidation is then performed whereby the implanted dopant diffuses vertically, engaging the field oxide around the perimeter of the device region and laterally filling in the region under the device active area.

Abstract: A method of manufacturing a semiconductor device in which a first ion implantation is carried out into a semiconductor substrate. Then, a second ion implantation is carried out to a projection range deeper than that of the first ion implantation. The ions of the second implantation are formed from the same type of atoms constituting the semiconductor substrate or from impurity atoms having the same conduction type as the semiconductor substrate at the projection range of the second ion implantation. A further ion implantation may be carried out to electrically shield the second implantation, or the method may be carried out in a SOI substrate with the second implantation extending through the insulating layer of the SOI structure.

Abstract: To form NPN and PNP transistors on the same base for example to obtain a complementary bipolar transistor it has been necessary to make an epitaxial layer a thick film, and this has resulted in deterioration of the characteristics of the NPN transistor. Also, because a step of forming an alignment mark has been necessary this has increased the number of manufacturing steps needed to make a complementary bipolar transistor. This invention provides a semiconductor device manufacturing method which solves this problem as follows: After a first opening 13 (alignment mark 16) and a second opening 14 are formed in an insulating film 12 formed on a semiconductor base 11 and a doping mask 15 is then formed on the semiconductor base 11, a third opening 17 is formed thereon with the alignment mark 16 as a reference.

Abstract: A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: A method for isolating elements in semiconductor devices is disclosed, which includes the steps of: forming a field oxide layer on the surface of a semiconductor substrate; using a photo resist pattern to define a field region and an active region; carrying out an ion implantation of several MeV with the photo resist pattern remaining on the field region, so as to form a channel stop layer on the field oxide layer region; and forming a soft error-preventing buried layer in the active region. The field insulating layer may be a silicon oxide layer or a silicon nitride layer. Additionally, a selective epitaxial process may be carried out so as to raise the level of the active region to substantially the height of the field isolating region, thereby flattening the surface.

Abstract: CMOS vertically modulated wells are constructed by using a blanket implant to form a blanket buried layer and then using clustered MeV ion implantation to form a structure having a buried implanted layer for lateral isolation in addition to said blanket buried layer.

Abstract: CMOS vertically modulated wells have a structure with a buried implanted layer for lateral isolation (BILLI). This structure includes a field oxide area, a first retrograde well of a first conductivity type, a second retrograde well of a second conductivity type adjacent the first well, and a BILLI layer below the first well and connected to the second well by a vertical portion. This structure has a distribution in depth underneath the field oxide which kills lateral beta while preventing damage near the surface under the field oxide.

Abstract: The present invention relates to forming a narrow gate MOSFET having a local ion implantation to reduce the junction capacitance. A polysilicon layer is formed over a semiconductor substrate. An opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a thermal oxidation is performed to oxidize the polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to the polysilicon layer thereby narrowing said opening. Then an ion implantation is performed by using said polysilicon-oxide layer as a mask.

Abstract: A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.

Abstract: A CMOS SRAM cell in which a patterned SIMOX layer forms a buried oxide beneath the PMOS devices, but not beneath the NMOS devices. Latchup is impossible, and well diffusions are not needed.

Abstract: A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

Abstract: A process for fabricating an MOS device (44) having a segmented channel region (48) includes the fabrication of a compound MOS gate electrode (46). Both the segmented channel region (48) and the MOS gate electrode (46) are formed by creating an opening (18) and an insulating layer (16) overlying a first polycrystalline silicon layer (14). The lateral extent of both the MOS gate electrode (46) and a buried junction region (24) formed in the semiconductor substrate (10) are defined by first sidewall spacer (22) and a second sidewall spacer (32) formed adjacent to the first sidewall spacer (22).

Abstract: Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate.

Abstract: A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration impurity region 8 of the second conductivity type and the low concentration impurity layer 2 of a first conductivity type can be made moderate to relax the electric field, which leads to provision of higher breakdown voltage of the semiconductor device. Further, the depth of impurity diffusion of the low concentration impurity region 6 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type is made at least three times the depth of impurity diffusion of the high concentration impurity region 8 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type.