Having Diaphragm Element Patents (Class 438/53)
  • Patent number: 10923460
    Abstract: A device for the transfer of chips from a source substrate onto a destination substrate, including: a source substrate having a lower surface and an upper surface; and a plurality of elementary chips arranged on the upper surface of the source substrate, wherein each elementary chip is suspended above the source substrate by at least one breakable mechanical fastener, said at least one breakable mechanical fastener having a lower surface fastened to the upper surface of the source substrate and an upper surface fastened to the lower surface of the chip.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 16, 2021
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Stéphane Caplet, Laurent Mollard
  • Patent number: 10899604
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, where the stress-sensitive sensor is sensitive to mechanical stress; a stress-decoupling trench that has a vertical extension that extends from the first surface into the substrate, where the stress-decoupling trench vertically extends partially into the substrate towards the second surface although not completely to the second surface; and a plurality of particle filter trenches that vertically extend from the second surface into the substrate, wherein each of the plurality of particle filter trenches have a longitudinal extension that extends orthogonal to the vertical extension of the stress-decoupling trench.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 26, 2021
    Inventors: Florian Brandl, Christian Geissler, Robert Gruenberger, Claus Waechter, Bernhard Winkler
  • Patent number: 10879449
    Abstract: Semiconductor strain gages fabricated on Silicon-on-insulator (SOI) material, and the method of making them. Force sensing elements are uniformly batch-fabricated at wafer level and singulated individually by a wire bonding method. In another method, they are singulated by plucking them off the wafer from their attachment site.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: December 29, 2020
    Inventor: Nihat Okulan
  • Patent number: 10876903
    Abstract: A multi-purpose Micro-Electro-Mechanical Systems (MEMS) thermopile sensor able to use as a thermal conductivity sensor, a Pirani vacuum sensor, a thermal flow sensor and a non-contact infrared temperature sensor, respectively.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 29, 2020
    Inventor: Xiang Zheng Tu
  • Patent number: 10850306
    Abstract: Processes for fabricating capacitive micromachined ultrasonic transducers (CMUTs) are described, as are CMUTs of various doping configurations. An insulating layer separating conductive layers of a CMUT may be formed by forming the layer on a lightly doped epitaxial semiconductor layer. Dopants may be diffused from a semiconductor substrate into the epitaxial semiconductor layer, without diffusing into the insulating layer. CMUTs with different configurations of N-type and P-type doping are also described.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 1, 2020
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Susan A. Alie, Joseph Lutsky, David Grosjean
  • Patent number: 10775253
    Abstract: A method for manufacturing a micromechanical component having a disengaged pressure sensor device includes: configuring an electrically conductive sacrificial element in or on a first outer surface of a first substrate; applying a second substrate on or upon the outer surface of the first substrate over the sacrificial element; configuring a pressure sensor device by anodic etching of the second substrate; configuring in the second substrate at least one trench that extends to the sacrificial element; and at least partly removing the sacrificial element in order to disengage the pressure sensor device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: September 15, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Heiko Stahl, Arne Dannenberg, Daniel Haug, Daniel Kaercher, Michaela Mitschke, Mike Schwarz, Timo Lindemann
  • Patent number: 10651817
    Abstract: In described examples of a micromechanical system (MEMS), a rigid cantilevered platform is formed on a base substrate. The cantilevered platform is anchored to the base substrate by only a single anchor point. A MEMS resonator is formed on the cantilevered platform.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 12, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ting-Ta Yen, Brian Goodlin, Ricky Alan Jackson, Nicholas Stephen Dellas
  • Patent number: 10634569
    Abstract: A pressure measurement device comprising a pressure sensor of a first type and a pressure sensor of a second type different from the first, which sensors are mounted on a common support in order to be subjected to the same pressure, in which the pressure sensor of the first type is of the capacitive type, the device being characterized in that the pressure sensor of the first type comprises at least one membrane and a first internal channel passing through the common support, a second internal channel bringing a fluid to the membrane being in fluid flow connection with the first internal channel. A calibration method associated with the device.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: April 28, 2020
    Assignee: SAFRAN ELECTRONICS & DEFENSE
    Inventors: Eric Bailly, Jean-Christophe Riou
  • Patent number: 10626008
    Abstract: A micro-electro-mechanical device formed in a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region above the first buried cavity; and a second buried cavity extending in the sensitive region. A decoupling trench extends from a first face of the monolithic body as far as the first buried cavity and laterally surrounds the second buried cavity. The decoupling trench separates the sensitive region from a peripheral portion of the monolithic body.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 21, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Lorenzo Baldo, Enri Duqi, Flavio Francesco Villa
  • Patent number: 10626011
    Abstract: An integrated MEMS electronic circuit that comprises a circuit wafer; a micromechanical structure being attached to a first surface of the circuit wafer and electrically coupled to an integrated circuit formed under said first surface. A capping chip having side surfaces substantially perpendicular to its main surfaces comprises a recess and is bonded to the first surface of the circuit wafer such that said micromechanical structure is enclosed in a cavity comprising the recess in the capping chip. Both the circuit wafer and the capping wafer can be further thinned while exposing at least one connection pad on the first surface of the circuit wafer that is not covered by the capping chip and that is coupled electrically to the integrated circuit.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: April 21, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Randall L. Kubena, Hung Nguyen
  • Patent number: 10597288
    Abstract: A method for manufacturing a MEMS device includes a hole forming step of forming a plurality of holes concaved from a principal surface in a substrate material including a semiconductor, a connecting-hollow-portion forming step of forming a connecting hollow portion that connects the plurality of holes together, and a movable-portion forming step of, by partially moving the semiconductor of the substrate material so as to close at least one part of the plurality of holes, forming a hollow portion that exists inside the substrate material and a movable portion that coincides with the hollow portion when viewed in a thickness direction of the substrate material.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: March 24, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Masahiro Sakuragi
  • Patent number: 10551192
    Abstract: An inertial sensor having a simple configuration by vacuum sealing a resonator which detects acceleration and exploits a resonance vibration using a high Q value MEMS device. The sensor includes: a detecting proof mass and beam which detects acceleration; a driving electrode which excites the detecting proof mass and beam; a resonant frequency tuning electrode which changes the resonant frequency of the detecting proof mass and beam; and a detecting circuit which applies voltage to the resonant frequency tuning electrode for changing the resonant frequency to cancel a change of the resonant frequency of the detecting proof mass and beam when the acceleration is applied to the detecting proof mass and beam during the vibration of the detecting proof mass and beam by the voltage applied to the detecting proof mass and beam, and outputs the acceleration based on a value of the voltage applied to resonant frequency tuning electrode.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: February 4, 2020
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Daisuke Maeda, Heewon Jeong, Masahide Hayashi
  • Patent number: 10506345
    Abstract: According to an embodiment, a microfabricated structure includes a cavity disposed in a substrate, a first clamping layer overlying the substrate, a deflectable membrane overlying the first clamping layer, and a second clamping layer overlying the deflectable membrane. A portion of the second clamping layer overlaps the cavity.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Wolfgang Klein, Reinhard Gabl
  • Patent number: 10490565
    Abstract: According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: November 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Osamu Arisumi, Yusuke Kawano
  • Patent number: 10393718
    Abstract: A MEMS apparatus for thermal energy control including a sensor and an IC chip is provided. The sensor includes a heating device for heating a sensing element and a detecting device for detecting a physical quantity. The IC chip includes a memory unit for storing a target value of the sensing element and a data processing unit for convert the physical quantity to a converted value, where a gap value is defined by subtracting the converted value from the target value. Besides, a control unit of the IC chip sets a parameter value according to the gap value, and a driving unit adjusts a quantity of thermal energy generated by the heating device according to the parameter value to reduce heating time and frequency of the heating device thereby reducing electrical power consumption. The MEMS apparatus is applicable to MEMS sensors requiring controlled operating temperature, such as a gas sensor.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 27, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Wen Hsu, Ying-Che Lo, Chao-Ta Huang, Li-Tao Teng
  • Patent number: 10370243
    Abstract: A method includes forming a mask that defines a masked area and an unmasked area on a front side of a substrate, and implanting a buried layer corresponding to the unmasked area on the front side of the substrate. The method also includes forming an epitaxial layer having a back side on the front side of the substrate and on a front side of the buried layer, and creating an opening into a back side of the substrate up to a back side of the epitaxial layer and a back side of the one or portions of the buried layer.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: August 6, 2019
    Assignee: Honeywell International Inc.
    Inventors: Carl Stewart, Richard Davis, Gilberto Morales
  • Patent number: 10329140
    Abstract: A semiconductor device includes at least one suspension region of a membrane structure, where the suspension region lies laterally in a first region of a surface of a semiconductor substrate; and a membrane region of the membrane structure, where a cavity is arranged vertically between the membrane region and at least one part of the semiconductor substrate, and the first region of the surface of the semiconductor substrate is formed by a surface of a shielding doping region of the semiconductor substrate.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: June 25, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Marco Haubold, Henning Feick, Kerstin Kaemmer
  • Patent number: 10148020
    Abstract: An electrical assembly includes a first electrical component with a first conductor, a second electrical component with a second conductor, and an accommodating chamber which is formed on the electrical assembly and in which an electrical contact point between the first and second conductors is arranged. The first conductor is arranged in a first insulating part and has at a free conductor end that protrudes from the first insulating part. The second conductor is arranged in a second insulating part and has a free conductor end that protrudes from the second insulating part. The accommodating chamber is partially filled with a potting mass such that the contact point and the free conductor ends are covered by the potting mass and the potting mass is bounded by an inner wall of the accommodating chamber. The inner wall of the accommodating chamber is formed by wall surfaces of the insulating parts.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 4, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Peter Zweigle, Franco Zeleny
  • Patent number: 10090405
    Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Matthew V. Metz
  • Patent number: 10060813
    Abstract: A sensor includes a diaphragm having a bonding portion and a main boss separated from the bonding portion by at least one channel, the main boss having a first side face, a second side face and a chamfered corner face connecting the first side face to the second side face. A base of the sensor has a first contact area aligned with the main boss and separated from the main boss, wherein the bonding portion of the diaphragm is bonded to the base. At least one sensing element senses movement of the diaphragm.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 28, 2018
    Assignee: ROSEMOUNT INC.
    Inventors: Charles R. Willcox, Nicholas E. Meyer
  • Patent number: 10048148
    Abstract: A process for manufacturing a MEMS pressure sensor having a micromechanical structure envisages: providing a wafer having a substrate of semiconductor material and a top surface; forming a buried cavity entirely contained within the substrate and separated from the top surface by a membrane suspended above the buried cavity; forming a fluidic-communication access for fluidic communication of the membrane with an external environment, set at a pressure the value of which has to be determined; forming, suspended above the membrane, a plate region made of conductive material, separated from the membrane by an empty space; and forming electrical-contact elements for electrical connection of the membrane and of the plate region, which are designed to form the plates of a sensing capacitor, the value of capacitance of which is indicative of the value of pressure to be detected. A corresponding MEMS pressure sensor having the micromechanical structure is moreover described.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: August 14, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Lorenzo Baldo, Sarah Zerbini, Enri Duqi
  • Patent number: 10008958
    Abstract: The present invention relates to a method of manufacturing a capacitive micro-machined transducer (100), in particular a CMUT, the method comprising depositing a first electrode layer (10) on a substrate (1), depositing a first dielectric film (20) on the first electrode layer (10), depositing a sacrificial layer (30) on the first dielectric film (20), the sacrificial layer (30) being removable for forming a cavity (35) of the transducer, depositing a second dielectric film (40) on the sacrificial layer (30), and depositing a second electrode layer (50) on the second dielectric film (40), wherein the first dielectric film (20) and/or the second dielectric film (40) comprises a first layer comprising an oxide, a second layer comprising a high-k material, and a third layer comprising an oxide, and wherein the depositing steps are performed by Atomic Layer Deposition. The present invention further relates to a capacitive micro-machined transducer (100), in particular a CMUT, manufactured by such method.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: June 26, 2018
    Assignee: Koninklijke Philips N.V.
    Inventors: Peter Dirksen, Ruediger Mauczok, Koray Karakaya, Johan Hendrik Klootwijk, Bout Marcelis, Marcel Mulder
  • Patent number: 9988260
    Abstract: A surface of a cavity of a MEMS device that is rough to reduce stiction. In some embodiments, the average roughness (Ra) of the surface is 5 nm or greater. In some embodiments, the rough surface is formed by forming one or more layers of a rough oxidizable material, then oxidizing the material to form an oxide layer with a rough surface. Another layer is formed over the oxide layer with the rough surface, wherein the roughness of the oxide layer is transferred to the another layer.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: June 5, 2018
    Assignee: NXP USA, Inc.
    Inventors: Ruben B. Montez, Arvind S. Salian, Robert F. Steimle
  • Patent number: 9963739
    Abstract: In one embodiment, a polymerase chain reaction (PCR) system includes a mixture chamber, a denature chamber, an annealing chamber, an extension chamber, and a product chamber, that are fluidically coupled to one another through a plurality of microfluidic channels. An inertial pump is associated with each microfluidic channel, and each inertial pump includes a fluid actuator integrated asymmetrically within its associated microfluidic channel. The fluid actuators are capable of selective activation to circulate fluid between the chambers in a controlled cycle.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 8, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Pavel Kornilovich, Eric D. Torniainen, Alexander Govyadinov, David P. Markel
  • Patent number: 9964476
    Abstract: The present disclosure relates to shear sensor arrays. In particular, the present disclosure relates to a floating element shear stress sensor array on a chip that is calibrated to high shear levels and is calibrated to determine the sensitivity to streamwise pressure gradients.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: May 8, 2018
    Assignee: TUFTS UNIVERSITY
    Inventors: Robert D. White, Zhengxin Zhao
  • Patent number: 9771257
    Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of fabricating or manufacturing MEMS having mechanical structures that operate in controlled or predetermined mechanical damping environments. In this regard, the present invention encapsulates the mechanical structures within a chamber, prior to final packaging and/or completion of the MEMS. The environment within the chamber containing and/or housing the mechanical structures provides the predetermined, desired and/or selected mechanical damping. The parameters of the encapsulated fluid (for example, the gas pressure) in which the mechanical structures are to operate are controlled, selected and/or designed to provide a desired and/or predetermined operating environment.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: September 26, 2017
    Assignee: ROBERT BOSCH GMBH
    Inventors: Aaron Partridge, Markus Lutz, Silvia Kronmueller
  • Patent number: 9679779
    Abstract: Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using selectively thermally-assisted chemical vapor deposition (STA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to heat. The freestanding film is then selectively heated in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 13, 2017
    Assignee: The Aerospace Corporation
    Inventors: David P. Taylor, Margaret H. Abraham
  • Patent number: 9634645
    Abstract: A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, Mario Francisco Velez, John H. Hong
  • Patent number: 9617150
    Abstract: Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a CMOS substrate and a MEMS substrate bonded with the CMOS substrate. The CMOS substrate includes a semiconductor substrate, a first dielectric layer formed over the semiconductor substrate, and a plurality of conductive pads formed in the first dielectric layer. The MEMS substrate includes a semiconductor layer having a movable element and a second dielectric layer formed between the semiconductor layer and the CMOS substrate. The MEMS substrate also includes a closed chamber surrounding the movable element. The MEMS substrate further includes a blocking layer formed between the closed chamber and the first dielectric layer of the CMOS substrate. The blocking layer is configured to block gas, coming from the first dielectric layer, from entering the closed chamber.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 9458012
    Abstract: A method includes applying a compressive force against MEMS structures at a front side of a MEMS wafer using a protective material covering at least a portion of the front side of the MEMS wafer. The method further includes concurrently dicing through the protective material and the MEMS wafer from the front side to produce a plurality of MEMS dies, each of which includes at least one of the MEMS structures. The protective material is secured over the front side of the MEMS wafer to apply pressure to the protective material, and thereby impart the compressive force against the MEMS structures to largely limit movement of the MEMS structures during dicing. A tack-free surface of the protective material enables its removal following dicing.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: October 4, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alan J. Magnus, Vijay Sarihan
  • Patent number: 9383282
    Abstract: A MEMS pressure sensor wherein at least one of the electrode arrangements comprises an inner electrode and an outer electrode arranged around the inner electrode. The capacitances associated with the inner electrode and the outer electrode are independently measured and can be differentially measured. This arrangement enables various different read out schemes to be implemented and also enables improved compensation for variations between devices or changes in device characteristics over time.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: July 5, 2016
    Assignee: AMS INTERNATIONAL AG
    Inventors: Willem Frederik Adrianus Besling, Klaus Reimann, Peter Steeneken, Olaf Wunnicke, Reinout Woltjer
  • Patent number: 9352960
    Abstract: There is provided a method for manufacturing a capacitive micromachined ultrasonic transducer. In this method, a first insulating layer and a vibrating membrane are bonded by heat treatment and a second insulating layer is formed by thermal oxidation in a single heating step, with a cavity provided in the transducer communicating with the outside of the transducer through a communication portion.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 31, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koichiro Nakanishi
  • Patent number: 9321626
    Abstract: A packaged MEMS transducer device comprising: a die, including: a semiconductor body having a front side and a back side, opposite to one another in a first direction, at least one cavity extending through the semiconductor body between the front side and the back side, and at least one membrane extending on the front side at least partially suspended over the cavity; and a package designed to house the die on an inner surface thereof. The transducer device moreover includes a sealing layer extending on the back side of the semiconductor body for sealing the cavity, and includes a paste layer extending between the sealing layer and the inner surface of the package for firmly coupling the die to the package.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mark Andrew Shaw, Fabrizio Soglio
  • Patent number: 9318603
    Abstract: The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.
    Type: Grant
    Filed: March 8, 2014
    Date of Patent: April 19, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yi Su, Daniel Ng, Anup Bhalla, Jun Lu
  • Patent number: 9263500
    Abstract: An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a thermal conductivity based gas sensor having an electrically resistive sensor element located on the major surface for exposure to a gas to be sensed. The integrated circuit further includes a barrier located on the major surface for inhibiting a flow of the gas across the sensor element.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: February 16, 2016
    Assignee: ams International AG
    Inventors: Aurelie Humbert, Roel Daamen, Viet Hoang Nguyen
  • Patent number: 9254998
    Abstract: An integrated circuit device includes a dielectric layer disposed onto a first substrate, the dielectric layer having a sacrificial cavity formed therein. The circuit also includes a membrane layer formed onto the dielectric layer and suspended over the sacrificial cavity, and a capping substrate bonded to the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Huan Chu
  • Patent number: 9240375
    Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 19, 2016
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Patent number: 9221674
    Abstract: A semiconductor structure for a microelectromechanical systems (MEMS) device is provided. A first substrate region includes an electrical isolation layer arranged over a top surface of the first substrate region. A second substrate region is arranged over the electrical isolation layer and includes a MEMS device structure arranged within the second substrate region. The MEMS device structure includes a fixed mass and a proof mass. A dielectric region is arranged over the electrical isolation layer around the fixed mass. A fixed mass electrode is arranged around the dielectric region, and extends through the second substrate region to the electrical isolation layer. An isolated electrode extends through the second substrate region and the electrical isolation layer to the first substrate region on an opposite side of the proof mass as the fixed mass electrode. The method of forming the semiconductor structure is also provided.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Kuei-Sung Chang, Chun-Wen Cheng
  • Patent number: 9206038
    Abstract: A capacitive micro-machined ultrasonic transducer (CMUT) and a method of singulating the same. Singulating CMUTs may include forming first trenches in regions of a device wafer defining a plurality of ultrasonic transducer structures, the device wafer including a plurality of the ultrasonic transducer structures, forming an ultrasonic transducer wafer having a plurality of ultrasonic transducers by bonding an electrode pad wafer supplying electricity to the plurality of ultrasonic transducers and the device wafer, and dicing the ultrasonic transducer wafer to form the plurality of ultrasonic transducers by cutting the plurality of ultrasonic transducer structures on the first trench and the electrode pad wafer below the first trench.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: December 8, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-gil Jeong, Seog-woo Hong
  • Patent number: 9184125
    Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: November 10, 2015
    Assignee: ZIPTRONIX, INC.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain
  • Patent number: 9176018
    Abstract: A method of fabrication of one or more ultra-miniature piezoresistive pressure sensors on silicon wafers is provided. The diaphragm of the piezoresistive pressure sensors is formed by fusion bonding. The piezoresistive pressure sensors can be formed by silicon deposition, photolithography and etching processes.
    Type: Grant
    Filed: February 22, 2014
    Date of Patent: November 3, 2015
    Inventor: Bin Qi
  • Patent number: 9178126
    Abstract: Provided is a thermoelectric device including a first electrode, a substrate electrically connected to the first electrode, a thin film on the substrate, and a second electrode on the thin film. The substrate and the thin film may be configured to exhibit a metallic property at a temperature over a critical temperature, thereby having a thermoelectric power of the device that is higher than that of a semiconductor junction.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 3, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun-Tak Kim, Jeong Yong Choi, Hyun-Woo Jeon, Jae ho Choi, Gi-wan Seo
  • Patent number: 9131896
    Abstract: A pressure sensor having a substrate and a first, deformable membrane, partially supported by the substrate, which generates a first sensor reading when deformed by pressure. A second membrane is contiguous to the first membrane. When the second membrane is energized, it deforms the first membrane to alter the first sensor reading.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: September 15, 2015
    Assignee: MEDOS INTERNATIONAL S.A.R.L.
    Inventors: Juergen Burger, Toralf Bork
  • Patent number: 9121896
    Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: September 1, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 9121820
    Abstract: The present disclosure relates to a top-down method of forming a nanowire structure extending between source and drain regions of a nanowire transistor device, and an associated apparatus. In some embodiments, the method provides a substrate having a device layer disposed over a first dielectric layer. The device layer has a source region and a drain region separated by a device material. The first dielectric layer has an embedded gate structure abutting the device layer. One or more masking layers are selectively formed over the device layer to define a nanowire structure. The device layer is then selectively etched according to the one or more masking layers to form a nanowire structure at a position between the source region and the drain region. By forming the nanowire structure through a masking and etch process, the nanowire structure is automatically connected to the source and drain regions.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shao Liu, Fei-Lung Lai, Chun-Wen Cheng
  • Patent number: 9096427
    Abstract: Method for making at least one first suspended part of a microelectronic or nanoelectronic structure from a monolithic part of a first substrate, the method comprising the following steps: make a first etching with a first given depth in the monolithic substrate to define the suspended part, deposit a protective layer on at least the side edges of the first etching, make a second etching with a second depth in the first etching, make a physicochemical treatment of at least part of the zone located under the suspended structure so as to modify it, and release the suspended part by removal of the physicochemically treated part.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: August 4, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Sofiane Ben Mbarek, Sophie Giroud, Frederic-Xavier Gaillard
  • Patent number: 9084067
    Abstract: A method of manufacturing a resonant transducer having a vibration beam includes: (a) providing an SOI substrate including: a first silicon layer; a silicon oxide layer on the first silicon layer; and a second silicon layer on the silicon oxide layer; (b) forming a first gap and second gap through the second silicon layer by etching the second silicon layer using the silicon oxide layer as an etching stop layer; (c) forming an impurity diffusion source layer on the second silicon layer; (d) forming an impurity diffused layer in a surface portion of the second silicon layer; (e) removing the impurity diffusion source layer through etching; and (f) removing at least a portion of the silicon oxide layer through etching such that an air gap is formed between the first silicon layer and a region of the second silicon layer surrounded by the first and second gaps.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 14, 2015
    Assignee: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Ryuichiro Noda, Takashi Yoshida
  • Patent number: 9074985
    Abstract: The invention concerns a device for analysing the microporosities of a given material including at least two phases, one of which is a fluid phase, including: multiple sensors (100) incorporated in the given material (M), where each of the sensors includes one or more cMUT acoustic and capacitive transducers.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: July 7, 2015
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, LABORATOIRE CENTRAL DES PONTS ET CHAUSSEES, ECOLE NATIONALE DES PONTS ET CHAUSSEES
    Inventors: Berengere Lebental, Elisabeth Delevoye, Anne Ghis
  • Publication number: 20150147841
    Abstract: A method for releasing a diaphragm of a micro-electro-mechanical systems (MEMS) device at a stage of semi-finished product. The method includes pre-wetting the MEMS device in a pre-wetting solution to at least pre-wet a sidewall surface of a cavity of the MEMS device. Then, a wetting process after the step of pre-wetting the MEMS device is performed to etch a dielectric material of a dielectric layer for holding the diaphragm, wherein a sensing portion of the diaphragm is released from the dielectric layer.
    Type: Application
    Filed: November 28, 2013
    Publication date: May 28, 2015
    Applicant: Solid State System Co., Ltd.
    Inventors: Tsung-Min Hsieh, Chien-Hsing Lee, Jhyy-Cheng Liou
  • Publication number: 20150145079
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes oxidizing a substrate to form local oxide regions that extend above a top surface of the substrate. A membrane layer is formed over the local oxide regions and the top surface of the substrate. A portion of the substrate under the membrane layer is removed. The local oxide regions under the membrane layer is removed.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventors: Alfons Dehe, Stefan Barzen, Wolfgang Friza, Wolfgang Klein