Physical Stress Responsive Patents (Class 438/50)
  • Patent number: 11398402
    Abstract: A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 26, 2022
    Assignee: Akoustis, Inc.
    Inventor: Jeffrey B. Shealy
  • Patent number: 11249242
    Abstract: A manufacturing system for fabricating self-aligned grating elements with a variable refractive index includes a patterning system, a deposition system, and an etching system. The manufacturing system performs a lithographic patterning of one or more photoresists to create a stack over a substrate. The manufacturing system performs a conformal deposition of a protective coating on the stack. The manufacturing system performs a deposition of a first photoresist of a first refractive index on the protective coating. The manufacturing system performs a removal of the first photoresist to achieve a threshold value of first thickness. The manufacturing system performs a deposition of a second photoresist of a second refractive index on the first photoresist. The second refractive index is greater than the first refractive index. The manufacturing system performs a removal of the second photoresist to achieve a threshold value of second thickness to form a portion of an optical grating.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: February 15, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Matthew E. Colburn, Giuseppe Calafiore, Matthieu Charles Raoul Leibovici, Erik Shipton, Pasi Saarikko
  • Patent number: 11220425
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: January 11, 2022
    Assignee: SiTime Corporation
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Patent number: 11194780
    Abstract: According to embodiments of the present invention, methods, systems and computer-readable media are presented for scanning a plurality of storage regions within memory for a specified quantity of results, wherein each storage region is associated with an interval including first and second interval values indicating a value range for values within that storage region. The techniques comprise sorting the first interval values into an order, wherein the order of the first interval values determines a scanning order for the plurality of storage regions, determining a result value, wherein the result value is an upper bound, a lower bound, or is outside of the specified quantity of results, and examining the sorted first interval values and scanning corresponding individual storage regions in response to a comparison of the determined result value with the first interval value of that storage region.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Garth A. Dickie, Dmitry Letin
  • Patent number: 11125772
    Abstract: Motion and/or orientation sensing systems can utilize gyroscopes, accelerometers, magnetometers, and other sensors for measuring motion or orientation of connected objects. Temperature changes affect the precision of the data output by the motion/orientation sensing device. A system is provided for controllably heating a device within a package to a desired temperature that varies based on the ambient temperature. The operating temperature of the device can then be known and controlled. The ambient temperature can be known through an ambient temperature sensor, for example. Given this information, a controller compensates the data output by the device to further improve the accuracy in the measurements. Like the amount of heating provided to the package, the amount of compensation is also based on the ambient temperature and/or the device temperature.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 21, 2021
    Assignee: BLILEY TECHNOLOGIES, INC.
    Inventors: Jay Mitchell, Anthony Challoner, Sangwoo Lee
  • Patent number: 11084716
    Abstract: A method for producing a micromechanical component having a substrate and a cap that are connected to each other and that enclose a first cavity, where a first pressure prevails inside the first cavity and a first gas mixture having a first chemical composition is enclosed within the first cavity, includes, in a first method step, developing in the substrate or cap an access opening connecting the first cavity to an environment of the micromechanical component, in a second method step, setting the first pressure and/or the first chemical composition in the first cavity, in a third method step, sealing the access opening using a laser by introduction of energy or heat into an absorbing part of the substrate or the cap, and, in a fourth method step, performing a thermal treatment of the substrate or the cap, thereby reducing temperature gradients in the substrate or in the cap.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 10, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Julia Amthor, Mawuli Ametowobla, Philip Kappe
  • Patent number: 11079427
    Abstract: An inspection device comprises: a detecting unit that is connected to a plurality of semiconductor chips having mutually different rates of change of electrical resistance with respect to stress loading direction, and that detects an electrical resistance value of each semiconductor chip from electric current flowing in each semiconductor chip; a first memory unit that is used to hold model data meant for converting an electrical resistance value into a characteristic value indicating at least either temperature, or stress, or strain; a converting unit that converts the electrical resistance value of each semiconductor chip as detected by the detecting unit into the characteristic value using the model data held in the first memory unit; and a second memory unit that is used to store the characteristic value, which is obtained by conversion by the converting unit, as time-series data for each of the plurality of semiconductor chips.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: August 3, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuaki Kato, Akihiro Goryu, Kenji Hirohata
  • Patent number: 11024795
    Abstract: A microelectronic device including a substrate including, in a stack, a base portion, a dielectric portion and an upper layer with a semi-conductive material base, at least one electrical connection element made of an electrically conductive material located above the upper layer and electrically insulated from the upper layer at least by a dielectric layer, the dielectric layer being in contact with the surface of the upper layer, at least one dielectric element including at least one trench forming a closed edge at the periphery or upright of at least one portion of the dielectric electrical connection element, located at least partially in the upper layer and delimiting a closed zone of said upper layer, at least one dielectric element having a portion exposed to the surface of the upper layer, device wherein the dielectric layer totally covers the exposed portion of at least one dielectric element.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 1, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Philippe Robert, Stephanus Louwers
  • Patent number: 11018003
    Abstract: In an embodiment, a method of selectively depositing a silicon germanium material on a substrate is provided. The method includes positioning the substrate within a substrate processing chamber, the substrate having a dielectric material and a silicon containing single crystal thereon; maintaining the substrate at a temperature of about 450° C. or less; exposing the substrate to a process gas comprising: a silicon source gas, a germanium source gas, an etchant gas, a carrier gas, and at least one dopant source gas; and epitaxially and selectively depositing a first silicon germanium material on the substrate.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: May 25, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Hua Chung
  • Patent number: 10962362
    Abstract: This disclosure is directed to a system and method for detecting a surface of a substrate within a scanner.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 30, 2021
    Assignee: RareCyte, Inc.
    Inventors: Paulina Varshavskaya, Edward Shafer, Steve Quarre, Ronald C. Seubert
  • Patent number: 10928257
    Abstract: A sensor and a method for measuring a pressure are disclosed. In an embodiment the sensor includes a main body including a piezoelectric material and at least two internal electrodes arranged in the piezoelectric material, wherein the at least two internal electrodes are arranged in such a way that a voltage arises between the at least two internal electrodes when a pressure acts on a side surface of the main body that is provided for an application of pressure.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: February 23, 2021
    Assignee: TDK ELECTRONICS AG
    Inventors: Martin Galler, Harald Kastl, Markus Puff
  • Patent number: 10910257
    Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 2, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Srikanth Kommu, Gang Wang, Shawn George Thomas
  • Patent number: 10829368
    Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack over a first main surface of a substrate, forming a polymer layer over a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Alfons Dehe, Stephan Pindl, Bernhard Knott, Carsten Ahrens
  • Patent number: 10793430
    Abstract: A method for producing thin MEMS wafers including: (A) providing an SOI wafer having an upper silicon layer, a first SiO2 layer and a lower silicon layer, the first SiO2 layer being situated between the upper silicon layer and the lower silicon layer, (B) producing a second SiO2 layer on the upper silicon layer, (C) producing a MEMS structure on the second SiO2 layer, (D) introducing clearances into the lower silicon layer down to the first SiO2 layer, (E) etching the first SiO2 layer and thus removing the lower silicon layer.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 6, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Sebastien Loiseau, Arnim Hoechst, Bernhard Gehl, Eugene Moliere Tanguep Njiokep, Sandra Altmannshofer
  • Patent number: 10787360
    Abstract: The present disclosure provides a method of manufacturing a structure. The method comprises: providing a first substrate; forming a conductive mesa over the first substrate; forming a silicon containing layer over the mesa; and forming a cavity comprising a movable member proximal to the first substrate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • Patent number: 10669151
    Abstract: A production method for a double-membrane MEMS component includes: providing a layer arrangement on a carrier substrate, wherein the layer arrangement comprises a first membrane structure, a sacrificial material layer adjoining the first membrane structure, and a counterelectrode structure in the sacrificial material layer and at a distance from the first membrane structure, wherein at least one through opening is formed in the sacrificial material layer as far as the first membrane structure; forming a filling material structure in the at least one through opening by applying a first filling material layer on the wall region of the at least one through opening; applying a second membrane structure on the layer arrangement with the sacrificial material; and removing the sacrificial material from an intermediate region to expose the filling material structure in the intermediate region.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 2, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Johann Strasser, Alfons Dehe, Gerhard Metzger-Brueckl, Juergen Wagner, Arnaud Walther
  • Patent number: 10665670
    Abstract: A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: May 26, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazutoyo Takano, Kazushige Matsuo, Masayoshi Hirao, Junji Yahiro
  • Patent number: 10598578
    Abstract: A tensile stress measurement device is to be attached to an object to be measured. The tensile stress measurement device may include an IC having a semiconductor substrate and tensile stress detection circuitry, the semiconductor substrate having opposing first and second attachment areas. The tensile stress measurement device may include a first attachment plate coupled to the first attachment area and extending outwardly to be attached to the object to be measured, and a second attachment plate coupled to the second attachment area and extending outwardly to be attached to the object to be measured. The tensile stress detection circuitry may be configured to detect a tensile stress imparted on the first and second attachment plates when attached to the object to be measured.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: March 24, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Pagani, Bruno Murari, Federico Giovanni Ziglioli
  • Patent number: 10446410
    Abstract: Embodiments of the present invention provide a method of processing a surface of a polysilicon and a method of processing a surface of a substrate assembly. The method of processing a surface of a polysilicon includes forming a material film on the surface of the polysilicon; and processing, by using a chemico-mechanical polishing technology, the surface of the polysilicon on which the material film is formed. The material film is selected such that the polysilicon is preferentially removed in a polishing process.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 15, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaoyong Lu, Chunping Long, Chien Hung Liu, Yucheng Chan, Xiaolong Li, Zheng Liu
  • Patent number: 10407301
    Abstract: MEMS device, in which a body made of semiconductor material contains a chamber, and a first column inside the chamber. A cap of semiconductor material is attached to the body and forms a first membrane, a first cavity and a first channel. The chamber is closed on the side of the cap. The first membrane, the first cavity, the first channel and the first column form a capacitive pressure sensor structure. The first membrane is arranged between the first cavity and the second face, the first channel extends between the first cavity and the first face or between the first cavity and the second face and the first column extends towards the first membrane and forms, along with the first membrane, plates of a first capacitor element.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 10, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enri Duqi, Lorenzo Baldo, Roberto Carminati
  • Patent number: 10272682
    Abstract: A piezoelectric device includes a first substrate that includes a piezoelectric element (32) provided in a first region where bending deformation is allowed and an electrode layer (39) electrically connected to the piezoelectric element (32), a second substrate in which a bump electrode (43) abutting and conducting the electrode layer (39), and having elasticity is formed, and which is disposed so as to face the piezoelectric element (32) with a predetermined space, and adhesive (43) that bonds the first substrate and the second substrate in a state where a distance between the first substrate and the second substrate is maintained. The adhesive (43) has a width in a center portion in a height direction relative to a surface of the first substrate or the second substrate greater than a width in end portions in the same direction.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: April 30, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Masashi Yoshiike
  • Patent number: 10120130
    Abstract: A solar cell includes a waveguide core for receiving light, a first layer formed on the waveguide core, a second layer formed on the first layer, a third layer formed on the second layer, first metalization coupled to the first layer, and second metalization coupled to the third layer. The first layer comprises a first optical film which varies in an index of refraction in a lateral direction between a first input end where the light is received and a first output end where the light is emitted. In some embodiments, wherein one or more of the first, second, or third layers has a tapered lateral thickness. In some embodiments, the first, second, and third layers form a PIN device. In some embodiments, the waveguide core has a first index of refraction that is lower than respective indexes of refraction for the first, second, and third layers.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: November 6, 2018
    Assignee: DEMARAY, LLC
    Inventor: R. Ernest Demaray
  • Patent number: 10049909
    Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick, Edmund J. Sprogis
  • Patent number: 9985194
    Abstract: Embodiments provide a solidly-mounted bulk acoustic wave (BAW) resonator and method of making same. In embodiments, the BAW resonator may include a planzarization portion in an inactive region of the BAW resonator that is coplanar with a piezoelectric layer of the BAW resonator in an active region of the BAW restonator. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: May 29, 2018
    Assignee: Qorvo US, Inc.
    Inventor: Alireza Tajic
  • Patent number: 9975766
    Abstract: An MEMS-based method for manufacturing a sensor comprises the steps of: forming a shallow channel (120) and a support beam (140) on a front surface of a substrate (100); forming a first epitaxial layer (200) on the front surface of the substrate (100) to seal the shallow channel (120); forming a suspended mesh structure (160) below the first epitaxial layer (200); and forming a deep channel (180) at a position on a back surface of the substrate (100) corresponding to the shallow channel (120), so that the shallow channel (120) is in communication with the deep channel (180). In the Method of manufacturing a MEMS-based sensor, when a shallow channel is formed on a front surface, a support beam of a mass block is formed, so the etching of a channel is easier to control, the process is more precise, and the uniformity and the homogeneity of the formed support beam are better.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: May 22, 2018
    Assignee: CSMC TECHNOLOGIES FABI CO., LTD.
    Inventors: Yonggang Hu, Guoping Zhou
  • Patent number: 9941117
    Abstract: A p-channel tunneling field effect transistor (TFET) is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy. An n-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The n-channel TFET includes an n-type region, a p-type region with a p-type delta doping, and a channel region disposed between and spacing apart the n-type region and the p-type region. The p-channel TFET and the n-channel TFET may be electrically connected to define a complementary field-effect transistor element. TFETs may be fabricated from a silicon-germanium TFET layer structure grown by low temperature molecular beam epitaxy at a growth temperature at or below 500° C.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: April 10, 2018
    Assignee: OHIO STATE INNOVATION FOUNDATION
    Inventor: Paul R. Berger
  • Patent number: 9929255
    Abstract: After formation of a gate structure and a lower dielectric spacer laterally surrounding the gate structure, a disposable material layer is deposited and planarized such that the top surface of the disposable material layer is formed below the topmost surface of the lower dielectric spacer. An upper dielectric spacer is formed around the gate structure and over the top surface of the disposable material layer. The disposable material layer is removed selective to the upper and lower dielectric spacers and device components underlying the gate structure. Semiconductor surfaces of the gate structure can be laterally sealed by the stack of the lower and upper dielectric spacers. Formation of any undesirable semiconductor deposition on the gate structure can be avoided by the combination of the lower and upper dielectric spacers during a subsequent selective epitaxy process.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 9798082
    Abstract: Methods of depositing materials to provide for efficient coupling of light from a first device to a second device are disclosed. In general, these methods include mounting one or more wafers on a rotating table that is continuously rotated under one or more source targets. A process gas can be provided and one or more of the source targets powered while the wafers are biased to deposit optical dielectric films on the one or more wafers. In some embodiments, a shadow mask can be laterally translated across the one or more wafers during deposition. In some embodiments, deposited films can have lateral and/or horizontal variation in index of refraction and/or lateral variation in thickness.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: October 24, 2017
    Assignee: DEMARAY, LLC
    Inventor: R. Ernest Demaray
  • Patent number: 9701533
    Abstract: A packing structure including: a cap secured to at least one first substrate and forming at least one cavity between the cap and the first substrate; a layer of at least one first material permeable to a gas, arranged in the cap and/or in the first substrate and/or at the interface between the cap and the first substrate, and forming at least one part of a wall of the cavity; a portion of at least one second material non-permeable to said gas, the thickness of which is higher than or equal to that of the layer of the first material, and surrounding at least one first part of the layer of the first material forming said part of the wall of the cavity; an aperture passing through the cap or the first substrate and opening onto or into said part of the layer of the first material.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: July 11, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Stephane Nicolas
  • Patent number: 9650239
    Abstract: A method embodiment for forming a micro-electromechanical (MEMS) device includes providing a MEMS wafer, wherein a portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer, and the carrier wafer is etched to expose the first membrane for the microphone device to an ambient environment. A MEMS substrate is patterned and portions of a first sacrificial layer are removed of the MEMS wafer to form a MEMS structure. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure. A second sealed cavity and a cavity exposed to an ambient environment on opposing sides of the second membrane for the pressure sensor device are formed.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 9630833
    Abstract: A method of manufacturing a cantilever structure includes providing a semiconductor substrate, forming a recess in the semiconductor substrate, forming a sacrificial layer in the recess, forming a cantilever structure layer on the semiconductor substrate and the sacrificial layer, performing an etching process to remove a portion of the cantilever structure layer until a surface of the sacrificial layer is exposed to form a cantilever structure and an opening, and removing a portion of the sacrificial layer to form a void below the cantilever structure so that the cantilever structure is suspended in the void. The cantilever structure thus formed has good morphological properties to ensure that the cantilever structure is free of residues at the bottom and has excellent suspension even if the width of the cantilever structure is relatively large.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 25, 2017
    Assignee: Semiconductore Manufacturing International (Shanghai) Corporation
    Inventors: Liang Ni, Xinxue Wang
  • Patent number: 9528890
    Abstract: A pressing force sensor that includes an expandable and contractible film, pressing force detecting resistor membranes formed on a portion of a main surface of the film, and a support disposed along the main surface of the film. The support is provided with recesses or holes with openings located in areas where the pressing force detecting resistor membranes on the main surface of the film are located. In the pressing force sensor, when a pressing force is exerted on the main surface of the film, the film is expanded with a pressing force detecting resistor membrane. As a result, the pressing force detecting resistor membrane is deformed, and a change in resistance value of the pressing force detecting resistor membrane corresponding to the deformation is detected.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: December 27, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hideki Kawamura, Masamichi Ando
  • Patent number: 9513184
    Abstract: One example discloses a MEMS device, including: a cavity having an internal environment; a seal isolating the internal environment from an external environment outside the MEMS device; wherein the seal is susceptible to damage in response to a calibration unsealing energy; wherein upon damage to the seal, a pathway forms which couples the internal environment to the external environment; and a calibration circuit capable of measuring the internal environment before and after damage to the seal.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: December 6, 2016
    Assignee: AMS INTERNATIONAL AG
    Inventors: Martijn Goossens, Willem Frederik Adrianus Besling, Peter Gerard Steeneken, Casper van der Avoort, Remco Henricus Wilhelmus Pijnenburg
  • Patent number: 9505030
    Abstract: Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: November 29, 2016
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Nevada J. Sanchez, Susan A. Alie
  • Patent number: 9499392
    Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: November 22, 2016
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Tyler S. Ralston, Gregory L. Charvat, Nevada J. Sanchez
  • Patent number: 9494477
    Abstract: According to various embodiments, a dynamic pressure sensor includes a substrate, a reference volume formed in the substrate, a deflectable membrane sealing the reference volume, a deflection sensing element coupled to the membrane and configured to measure a deflection of the membrane, and a ventilation hole configured to equalize an absolute pressure inside the reference volume with an absolute ambient pressure outside the reference volume.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Andreas Wiesbauer, Alfons Dehe
  • Patent number: 9487393
    Abstract: A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: November 8, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Hsin-Yi Liao, Chun-An Huang, Shih-Kuang Chiu, Chien-An Chen
  • Patent number: 9366816
    Abstract: Methods of depositing materials to provide for efficient coupling of light from a first device to a second device are disclosed. In general, these methods include mounting one or more wafers on a rotating table that is continuously rotated under one or more source targets. A process gas can be provided and one or more of the source targets powered while the wafers are biased to deposit optical dielectric films on the one or more wafers. In some embodiments, a shadow mask can be laterally translated across the one or more wafers during deposition. In some embodiments, deposited films can have lateral and/or horizontal variation in index of refraction and/or lateral variation in thickness.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: June 14, 2016
    Assignee: DEMARAY, LLC
    Inventor: R. Ernest Demaray
  • Patent number: 9343530
    Abstract: The present invention provides a method of manufacturing a fin structure of a FinFET, comprising: providing a substrate (200); forming a first dielectric layer (210); forming a second dielectric layer (220), the material of the portion where the second dielectric layer is adjacent to the first dielectric layer being different from that of the first dielectric layer (210); forming an opening (230) through the second dielectric layer (220) and the first dielectric layer (2100, the opening portion exposing the substrate; filling a semiconductor material in the opening (230); and removing the second dielectric layer (220) to form a fin structure. In the present invention, the height of the fin structure in the FinFET is controlled by the thickness of the dielectric layer. The etching stop can be controlled well by using the etching selectivity between different materials, which can achieve etching uniformity better compared to time control.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 17, 2016
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Haizhou Yin, Wei Jiang, Huilong Zhu
  • Patent number: 9334160
    Abstract: A method for creating MEMS structures comprises depositing and patterning a first mask on a wafer in order to define desired first areas to be etched in a first trench etching and desired second areas to be etched in a second trench etching. A first intermediate mask is deposited and patterned on top of the first mask. Recession trenches are etched on parts of the wafer. After the first intermediate mask is removed, first trenches are etched with further etching the recession trenches. The first trenches and the recession trenches are filled with a deposit layer. Part of the deposit layer is removed on second areas. A remainder is left on certain areas, to function as a second mask. A third mask is deposited. The third mask defines the final structure. The parts of the wafer on the second areas are etched in the second trench etching. The masks are then removed.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: May 10, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Altti Torkkeli, Antti Iihola
  • Patent number: 9260290
    Abstract: An apparatus is formed on a substrate including at least one semiconductor device. The apparatus includes a microelectromechanical system (MEMS) device comprising at least one of a portion of a first structural layer and a portion of a second structural layer formed above the first structural layer. The second structural layer has a thickness substantially greater than a thickness of the first structural layer. In at least one embodiment, the MEMS device includes a first portion of the second structural layer and a second portion of the second structural layer. In at least one embodiment, the MEMS device further comprises a gap between the first portion of the second structural layer and the second portion of the second structural layer. In at least one embodiment, the gap has a width at least one order of magnitude less than the thickness of the second structural layer.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: February 16, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Emmanuel P. Quevy, Carrie W. Low, Jeremy Ryan Hui, Zhen Gu
  • Patent number: 9221675
    Abstract: A method for integrating an IC and a MEMS component includes the following steps: S1) providing a SOI base (20) having a first area (21) and a second area (22); S2) fabricating an IC on the first area through a standard semiconductor process, and simultaneously forming a metal conductive layer (26) and a medium insulation layer (25c) extending to the second area; S3) partly removing the medium insulation layer and then further partly removing the silicon component layer so as to form a backplate diagram; S4) depositing a sacrificial layer (32) above the SOI base; S5) forming a Poly Sil-xGex film (33) on the sacrificial layer; S6) forming a back cavity (34); and S7) eroding the sacrificial layer to form a chamber (36) in communication with the back cavity. Besides, a chip (10) fabricated by the above method is also disclosed.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: December 29, 2015
    Assignee: MEMSENSING MICROSYSTEMS TECHNOLOGY CO., LTD
    Inventors: Wei Hu, Gang Li, Jia-Xin Mei
  • Patent number: 9193582
    Abstract: A method of forming a microelectronic device comprising, on a same substrate, at least one electro-mechanical component provided with a suspended structure and at least one transistor, the method comprising a step of release of the suspended structure from the electromechanical component after having formed metal interconnection levels of components.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: November 24, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Eric Ollier, Julien Arcamone, Mylene Savoye
  • Patent number: 9187317
    Abstract: A method embodiment for forming a micro-electromechanical (MEMS) device includes providing a MEMS wafer, wherein a portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer, and the carrier wafer is etched to expose the first membrane for the microphone device to an ambient environment. A MEMS substrate is patterned and portions of a first sacrificial layer are removed of the MEMS wafer to form a MEMS structure. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure. A second sealed cavity and a cavity exposed to an ambient environment on opposing sides of the second membrane for the pressure sensor device are formed.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: November 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu
  • Patent number: 9170164
    Abstract: The invention discloses a capacitive pressure sensor and a method of fabricating the same. The capacitive pressure sensor includes a fixed plate configured as a back plate, a movable plate configured as diaphragm for sensing pressure, wherein a cavity is formed between the fixed plate and the movable plate, an isolation layer between the fixed plate and the movable plate and electrical contacts thereof for minimizing the leakage current, plurality of damping holes for configuring the contour of the fixed plate as the deflected diaphragm when pressure is exerted, a vent hole extending to the cavity having resistive air path for providing equilibrium to the diaphragm and an extended back chamber for increasing the sensitivity of the capacitive pressure sensor. The capacitive pressure sensor is also configured for minimizing parasitic capacitance.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 27, 2015
    Inventors: Dieter Naegele-Preissmann, J. V. Sreedhar
  • Patent number: 9171783
    Abstract: A method for manufacturing a semiconductor device includes forming a lower electrode pattern on a substrate, forming a first insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first insulating layer, forming an etch blocking spacer at a side of the upper electrode pattern, forming a second insulating layer on the upper electrode pattern, etching the second insulating layer to form a cavity which exposes the etch blocking spacer, and forming a contact ball in the cavity.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 27, 2015
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Ki Jun Yun
  • Patent number: 9162518
    Abstract: Silicon microcarriers suitable for fluorescent assays as a well as a method of producing such microcarriers are provided. The method includes the steps of providing a SOI wafer having a bottom layer of monocristalline silicone, an insulator layer and a bottom layer of monocristalline silicon, delineating microparticles, etching away the insulator layer and then depositing an oxide layer on the wafer still holding the microparticles before finally lifting-off the microparticles.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: October 20, 2015
    Assignee: MYCARTIS NV
    Inventors: Nicolas Demierre, Stephan Gamper
  • Patent number: 9156681
    Abstract: Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: October 13, 2015
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Chung Kyung Jung, Ki Jun Yun, Oh Jin Jung, Sang Wook Ryu, Seong Hun Jeong, Sung Wook Joo
  • Patent number: 9139425
    Abstract: A method of avoiding stiction during vapor hydrofluoride (VHF) release of a microelectromechanical system (MEMS) or nanoelectromechanical system (NEMS) composed of a mechanical device and a substrate is described. A silicon nitride layer is provided between the substrate and a sacrificial oxide layer and/or between a device layer and the sacrificial oxide layer, and/or on a side of the device layer facing away from the sacrificial oxide layer, and converted to thicker ammonium hexafluorosilicate with VHF while simultaneously removing a portion of the sacrificial oxide. The ammonium hexafluorosilicate acts as a temporary support, shim, wedge, or tether which limits device movement during fabrication and is later removed by sublimation under heat and/or reduced pressure.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: September 22, 2015
    Assignee: SPTS Technologies Limited
    Inventor: Daniel J. Vestyck
  • Patent number: 9133017
    Abstract: A MEMS structure incorporating multiple joined substrates and a method for forming the MEMS structure are disclosed. An exemplary MEMS structure includes a first substrate having a bottom surface and a second substrate having a top surface substantially parallel to the bottom surface of the first substrate. The bottom surface of the first substrate is connected to the top surface of the second substrate by an anchor, such that the anchor does not extend through either the bottom surface of the first substrate or the top surface of the second substrate. The MEMS structure may include a bonding layer in contact with the bottom surface of the first substrate, and shaped to at least partially envelop the anchor.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Jiou-Kang Lee, Chung-Hsien Lin, Te-Hao Lee, Chia-Hua Chu