Having Diaphragm Element Patents (Class 438/53)
  • Patent number: 9318603
    Abstract: The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.
    Type: Grant
    Filed: March 8, 2014
    Date of Patent: April 19, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yi Su, Daniel Ng, Anup Bhalla, Jun Lu
  • Patent number: 9263500
    Abstract: An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a thermal conductivity based gas sensor having an electrically resistive sensor element located on the major surface for exposure to a gas to be sensed. The integrated circuit further includes a barrier located on the major surface for inhibiting a flow of the gas across the sensor element.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: February 16, 2016
    Assignee: ams International AG
    Inventors: Aurelie Humbert, Roel Daamen, Viet Hoang Nguyen
  • Patent number: 9254998
    Abstract: An integrated circuit device includes a dielectric layer disposed onto a first substrate, the dielectric layer having a sacrificial cavity formed therein. The circuit also includes a membrane layer formed onto the dielectric layer and suspended over the sacrificial cavity, and a capping substrate bonded to the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Huan Chu
  • Patent number: 9240375
    Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 19, 2016
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Patent number: 9221674
    Abstract: A semiconductor structure for a microelectromechanical systems (MEMS) device is provided. A first substrate region includes an electrical isolation layer arranged over a top surface of the first substrate region. A second substrate region is arranged over the electrical isolation layer and includes a MEMS device structure arranged within the second substrate region. The MEMS device structure includes a fixed mass and a proof mass. A dielectric region is arranged over the electrical isolation layer around the fixed mass. A fixed mass electrode is arranged around the dielectric region, and extends through the second substrate region to the electrical isolation layer. An isolated electrode extends through the second substrate region and the electrical isolation layer to the first substrate region on an opposite side of the proof mass as the fixed mass electrode. The method of forming the semiconductor structure is also provided.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Kuei-Sung Chang, Chun-Wen Cheng
  • Patent number: 9206038
    Abstract: A capacitive micro-machined ultrasonic transducer (CMUT) and a method of singulating the same. Singulating CMUTs may include forming first trenches in regions of a device wafer defining a plurality of ultrasonic transducer structures, the device wafer including a plurality of the ultrasonic transducer structures, forming an ultrasonic transducer wafer having a plurality of ultrasonic transducers by bonding an electrode pad wafer supplying electricity to the plurality of ultrasonic transducers and the device wafer, and dicing the ultrasonic transducer wafer to form the plurality of ultrasonic transducers by cutting the plurality of ultrasonic transducer structures on the first trench and the electrode pad wafer below the first trench.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: December 8, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-gil Jeong, Seog-woo Hong
  • Patent number: 9184125
    Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: November 10, 2015
    Assignee: ZIPTRONIX, INC.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain
  • Patent number: 9176018
    Abstract: A method of fabrication of one or more ultra-miniature piezoresistive pressure sensors on silicon wafers is provided. The diaphragm of the piezoresistive pressure sensors is formed by fusion bonding. The piezoresistive pressure sensors can be formed by silicon deposition, photolithography and etching processes.
    Type: Grant
    Filed: February 22, 2014
    Date of Patent: November 3, 2015
    Inventor: Bin Qi
  • Patent number: 9178126
    Abstract: Provided is a thermoelectric device including a first electrode, a substrate electrically connected to the first electrode, a thin film on the substrate, and a second electrode on the thin film. The substrate and the thin film may be configured to exhibit a metallic property at a temperature over a critical temperature, thereby having a thermoelectric power of the device that is higher than that of a semiconductor junction.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 3, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun-Tak Kim, Jeong Yong Choi, Hyun-Woo Jeon, Jae ho Choi, Gi-wan Seo
  • Patent number: 9131896
    Abstract: A pressure sensor having a substrate and a first, deformable membrane, partially supported by the substrate, which generates a first sensor reading when deformed by pressure. A second membrane is contiguous to the first membrane. When the second membrane is energized, it deforms the first membrane to alter the first sensor reading.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: September 15, 2015
    Assignee: MEDOS INTERNATIONAL S.A.R.L.
    Inventors: Juergen Burger, Toralf Bork
  • Patent number: 9121820
    Abstract: The present disclosure relates to a top-down method of forming a nanowire structure extending between source and drain regions of a nanowire transistor device, and an associated apparatus. In some embodiments, the method provides a substrate having a device layer disposed over a first dielectric layer. The device layer has a source region and a drain region separated by a device material. The first dielectric layer has an embedded gate structure abutting the device layer. One or more masking layers are selectively formed over the device layer to define a nanowire structure. The device layer is then selectively etched according to the one or more masking layers to form a nanowire structure at a position between the source region and the drain region. By forming the nanowire structure through a masking and etch process, the nanowire structure is automatically connected to the source and drain regions.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shao Liu, Fei-Lung Lai, Chun-Wen Cheng
  • Patent number: 9121896
    Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: September 1, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 9096427
    Abstract: Method for making at least one first suspended part of a microelectronic or nanoelectronic structure from a monolithic part of a first substrate, the method comprising the following steps: make a first etching with a first given depth in the monolithic substrate to define the suspended part, deposit a protective layer on at least the side edges of the first etching, make a second etching with a second depth in the first etching, make a physicochemical treatment of at least part of the zone located under the suspended structure so as to modify it, and release the suspended part by removal of the physicochemically treated part.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: August 4, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Sofiane Ben Mbarek, Sophie Giroud, Frederic-Xavier Gaillard
  • Patent number: 9084067
    Abstract: A method of manufacturing a resonant transducer having a vibration beam includes: (a) providing an SOI substrate including: a first silicon layer; a silicon oxide layer on the first silicon layer; and a second silicon layer on the silicon oxide layer; (b) forming a first gap and second gap through the second silicon layer by etching the second silicon layer using the silicon oxide layer as an etching stop layer; (c) forming an impurity diffusion source layer on the second silicon layer; (d) forming an impurity diffused layer in a surface portion of the second silicon layer; (e) removing the impurity diffusion source layer through etching; and (f) removing at least a portion of the silicon oxide layer through etching such that an air gap is formed between the first silicon layer and a region of the second silicon layer surrounded by the first and second gaps.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 14, 2015
    Assignee: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Ryuichiro Noda, Takashi Yoshida
  • Patent number: 9074985
    Abstract: The invention concerns a device for analysing the microporosities of a given material including at least two phases, one of which is a fluid phase, including: multiple sensors (100) incorporated in the given material (M), where each of the sensors includes one or more cMUT acoustic and capacitive transducers.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: July 7, 2015
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, LABORATOIRE CENTRAL DES PONTS ET CHAUSSEES, ECOLE NATIONALE DES PONTS ET CHAUSSEES
    Inventors: Berengere Lebental, Elisabeth Delevoye, Anne Ghis
  • Publication number: 20150147841
    Abstract: A method for releasing a diaphragm of a micro-electro-mechanical systems (MEMS) device at a stage of semi-finished product. The method includes pre-wetting the MEMS device in a pre-wetting solution to at least pre-wet a sidewall surface of a cavity of the MEMS device. Then, a wetting process after the step of pre-wetting the MEMS device is performed to etch a dielectric material of a dielectric layer for holding the diaphragm, wherein a sensing portion of the diaphragm is released from the dielectric layer.
    Type: Application
    Filed: November 28, 2013
    Publication date: May 28, 2015
    Applicant: Solid State System Co., Ltd.
    Inventors: Tsung-Min Hsieh, Chien-Hsing Lee, Jhyy-Cheng Liou
  • Publication number: 20150145079
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes oxidizing a substrate to form local oxide regions that extend above a top surface of the substrate. A membrane layer is formed over the local oxide regions and the top surface of the substrate. A portion of the substrate under the membrane layer is removed. The local oxide regions under the membrane layer is removed.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventors: Alfons Dehe, Stefan Barzen, Wolfgang Friza, Wolfgang Klein
  • Patent number: 9034680
    Abstract: In a method for producing a micro-electromechanical device in a material substrate, a component element defining the position of an electronic component and/or required for the function of the electronic component is selectively formed on the material substrate from an etching stop material acting as an etching stop in case of etching of the material substrate and/or in case of etching of a material layer disposed on the material substrate. When the component element of the electronic component is implemented, a bounding region is also formed on the material substrate along at least a partial section of an edge of the surface structure, wherein the bounding region bounds the partial section. The material substrate thus implemented is selectively etched for forming the surface structure, in that the edge of the bounding region defines the position of the surface structure to be implemented on the material substrate.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: May 19, 2015
    Assignee: ELMOS Semiconductor AG
    Inventor: Arnd Ten-Have
  • Patent number: 9035451
    Abstract: The present disclosure relates to a method of forming a plurality of MEMs device having a plurality of cavities with different pressures on a wafer package system, and an associated apparatus. In some embodiments, the method is performed by providing a work-piece having a plurality of microelectromechanical system (MEMs) devices. A cap wafer is bonded onto the work-piece in a first ambient environment having a first pressure. The bonding forms a plurality of cavities abutting the plurality of MEMs devices, which are held at the first pressure. One or more openings are formed in one or more of the plurality of cavities leading to a gas flow path that could be held at a pressure level different from the first pressure. The one or more openings in the one or more of the plurality of cavities are then sealed in a different ambient environment having a different pressure, thereby causing the one or more of the plurality of cavities to be held at the different pressure.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Kuei-Sung Chang, Chun-Wen Cheng
  • Publication number: 20150132880
    Abstract: A method for fabricating MEMS device includes providing a silicon substrate. A structural dielectric layer is formed over a first side of the silicon substrate. Structure elements are embedded in the structural dielectric layer. The structure elements include a conductive backplate disposed over the silicon substrate, having venting holes and protrusion structures on top of the conductive backplate; and diaphragm located above the conductive backplate by a distance. A chamber is formed between the diaphragm and the conductive backplate. A cavity is formed in the silicon substrate at a second side. The cavity corresponds to the structure elements. An isotropic etching is performed on a dielectric material of the structural dielectric layer to release the structure elements. A first side of the diaphragm is exposed by the chamber and faces to the protrusion structures of the conductive backplate. A second side of the diaphragm is exposed to an environment space.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventors: Tsung-Min Hsieh, Chien-Hsing Lee, Jhyy-Cheng Liou
  • Patent number: 9029179
    Abstract: A method for producing a MEMS device having improved charge elimination characteristics includes providing a substrate having one or more layers, and applying a first charge elimination layer onto at least one portion of one given layer of the substrate. The method may then (1) apply a sacrificial layer onto the first charge elimination layer, (2) apply a second charge elimination layer onto at least a portion of the sacrificial layer, and (3) deposit a movable layer onto at least a portion of the second charge elimination layer. To form a structure within the movable layer the method may etch the movable layer. The method may then etch the sacrificial layer to release the structure.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 12, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Fang Liu, Kuang L. Yang
  • Patent number: 9029963
    Abstract: Mechanical resonating structures, as well as related devices and methods of manufacture. The mechanical resonating structures can be microphones, each including a diaphragm and a piezoelectric stack. The diaphragm can have one or more openings formed therethrough to enable the determination of an acoustic pressure being applied to the diaphragm through signals emitted by the piezoelectric stack.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Sand 9, Inc.
    Inventors: Andrew Sparks, Todd M. Borkowski
  • Publication number: 20150125984
    Abstract: A microphone system includes a diaphragm suspended by springs and including a sealing layer that seals passageways which, if left open, would degrade the microphone's frequency response by allowing air to pass from one side of the diaphragm to the other when the diaphragm is responding to an incident acoustic signal. In some embodiments, the sealing layer may include an equalization aperture to allow pressure to equalize on both sides of the diaphragm.
    Type: Application
    Filed: January 8, 2015
    Publication date: May 7, 2015
    Inventors: Fang Liu, Kuang L. Yang
  • Patent number: 9018030
    Abstract: A transparent force sensor for use in touch panel displays (touch screens) and method for fabricating the same are disclosed. The transparent force sensor is capable of detecting touch by measuring local pressure applied by a touch input to a display area of the touch screen.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: April 28, 2015
    Assignee: Symbol Technologies, Inc.
    Inventors: Hao Li, Papu Maniar, Yi Wei
  • Publication number: 20150102437
    Abstract: A device (20) includes sensors (30, 32, 34) that sense different physical stimuli. Fabrication (90) entails forming (92) a device structure (22) to include the sensors and coupling (150) a cap structure (24) with the device structure so that the sensors are interposed between the cap structure and a substrate layer (28) of the device structure. Fabrication (90) further entails forming ports (38, 40) in the substrate layer (28) such that one port (38) exposes a sense element (44) of the sensor (30) to an external environment (72), and another port (40) temporarily exposes the sensor (34) to the external environment. A seal structure (26) is attached to the substrate layer (28) such that one port (40) is hermetically sealed by the seal structure and an external port (46) of the seal structure is aligned with the port (38).
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Inventors: Lianjun Liu, James S. Bates, Mamur Chowdhury, David J. Monk, Babak A. Taheri
  • Patent number: 9006846
    Abstract: This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 14, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Janusz Bryzek, John Gardner Bloomsburgh, Cenk Acar
  • Publication number: 20150096374
    Abstract: Disclosed herein is an angular velocity sensor, including: a mass body part; an internal frame supporting the mass body part; a first flexible part each connecting the mass body part to the internal frame; a second flexible part each connecting the mass body part to the internal frame; an external frame supporting the internal frame; a third flexible part connecting the internal frame and the external frame to each other; and a fourth flexible part connecting the internal frame and the external frame to each other, wherein the internal frame, the second flexible part, and the fourth flexible part have an oxide layer formed thereon.
    Type: Application
    Filed: September 28, 2014
    Publication date: April 9, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Woon Kim, Jae Chang Lee, Sang Kee Yoon, Hyun Kee Lee, Yeong Gyu Lee, Seung Mo Lim
  • Publication number: 20150096376
    Abstract: In accordance with one embodiment, a single chip combination inertial and pressure sensor device includes a substrate, an inertial sensor including a movable sensing structure movably supported above the substrate, and a first fixed electrode positioned adjacent to the movable sensing structure, and a pressure sensor including a gap formed in the sensor at a location directly above the movable sensing structure, and a flexible membrane formed in a cap layer of the device, the flexible membrane defining a boundary of the gap and configured to flex toward and away from the gap in response to a variation in pressure above the flexible membrane.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 9, 2015
    Inventors: Ando Feyh, Gary O'Brien
  • Patent number: 8999757
    Abstract: A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port extending through the lid. A first base component is bonded to the sidewalls defining an internal cavity. This first base component further includes an aperture extending therethrough. The MEMS device is inserted through the aperture and bonded said to the lid with the MEMS device at least partially overlapping the port. Assembly is completed by bonding a second base component to the first base component to seal the aperture. The package so formed has a cover with a lid, sidewalls and a port extending through the lid. A MEMS device is bonded to the lid and electrically interconnected to electrically conductive features disposed on the first base component. A second base component is bonded to the first base component spanning the aperture.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: April 7, 2015
    Assignee: Unisem (M) Berhad
    Inventors: Rob Protheroe, Alan Evans, Timothy Leung, Ming Xiang Tang, JunHua Guan
  • Patent number: 9000544
    Abstract: A MEMS package structure, including a substrate, an interconnecting structure, an upper metallic layer, a deposition element and a packaging element is provided. The interconnecting structure is disposed on the substrate. The MEMS structure is disposed on the substrate and within a first cavity. The upper metallic layer is disposed above the MEMS structure and the interconnecting structure, so as to form a second cavity located between the upper metallic layer and the interconnecting structure and communicates with the first cavity. The upper metallic layer has at least a first opening located above the interconnecting structure and at least a second opening located above the MEMS structure. Area of the first opening is greater than that of the second opening. The deposition element is disposed above the upper metallic layer to seal the second opening. The packaging element is disposed above the upper metallic layer to seal the first opening.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: April 7, 2015
    Assignee: Pixart Imaging Inc.
    Inventors: Hsin-Hui Hsu, Sheng-Ta Lee, Chuan-Wei Wang
  • Patent number: 8993362
    Abstract: A method and structure for fabricating a monolithic integrated MEMS device. The method includes providing a substrate having a surface region and forming at least one conduction material and at least one insulation material overlying at least one portion of the surface region. At least one support structure can be formed overlying at least one portion of the conduction and insulation surface regions, and at least one MEMS device can be formed overlying the support structure(s) and the conduction and insulation surface regions. In a variety of embodiments, the support structure(s) can include dielectric or oxide materials. The support structure(s) can then be removed and a cover material can be formed overlying the MEMS device(s), the conduction and insulation materials, and the substrate. In various embodiments, the removal of the support structure(s) can be accomplished via a vapor etching process.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: March 31, 2015
    Assignee: mCube Inc.
    Inventor: Anthony F. Flannery, Jr.
  • Patent number: 8994129
    Abstract: Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a substrate and a MEMS structure over the substrate, and the MEMS structure has a movable element. The movable element is surrounded by a cavity. The MEMS device also includes a fuse layer on the movable element, and the fuse layer has a wide portion and a narrow portion linked to the wide portion.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chun-Ren Cheng
  • Patent number: 8991262
    Abstract: A capacitive pressure sensor includes a semiconductor substrate, a first insulating portion configured to define a sensor region, a reference pressure chamber configured to divide a lower portion of the sensor region in a direction, a second insulating portion configured to divide a surface portion of the sensor region above the reference pressure chamber in the direction, and a trench configured to divide the sensor region in the direction. The sensor region is divided into at least three semiconductor parts by the reference pressure chamber, the second insulating portion, and the trench.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: March 31, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Goro Nakatani
  • Patent number: 8989411
    Abstract: A vacuum sealed directional microphone and methods for fabricating said vacuum sealed directional microphone. A vacuum sealed directional microphone includes a rocking structure coupled to two vacuum sealed diaphragms which are responsible for collecting incoming sound and deforming under sound pressure. The rocking structure's resistance to bending aids in reducing the deflection of each diaphragm under large atmospheric pressure. Furthermore, the rocking structure exhibits little resistance about its pivot thereby enabling it to freely rotate in response to small pressure gradients characteristic of sound. The backside cavities of such a device can be fabricated without the use of the deep reactive ion etch step thereby allowing such a microphone to be fabricated with a CMOS compatible process.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: March 24, 2015
    Assignee: Board of Regents, The University of Texas System
    Inventors: Neal A. Hall, Michael Louis Kuntzman, Karen Denise Kirk
  • Publication number: 20150076627
    Abstract: A MEMS microphone with reduced parasitic capacitance is provided. A microphone includes a protection film covering a rim-sided area of the backplate.
    Type: Application
    Filed: November 14, 2011
    Publication date: March 19, 2015
    Inventors: Leif Steen Johansen, Jan Tue Ravnkilde, Pirmin Hermann Otto Rombach, Kurt Rasmussen
  • Publication number: 20150076632
    Abstract: The disclosure provides methods and apparatus for release-assisted microcontact printing of MEMS. Specifically, the principles disclosed herein enable patterning diaphragms and conductive membranes on a substrate having articulations of desired shapes and sizes. Such diaphragms deflect under applied pressure or force (e.g., electrostatic, electromagnetic, acoustic, pneumatic, mechanical, etc.) generating a responsive signal. Alternatively, the diaphragm can be made to deflect in response to an external bias to measure the external bias/phenomenon. The disclosed principles enable transferring diaphragms and/or thin membranes without rupturing.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 19, 2015
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Apoorva MURARKA, Vladimir BULOVIC, Sarah PAYDAVOSI
  • Patent number: 8981498
    Abstract: An electronic MEMS device is formed by a chip having with a main face and bonded to a support via an adhesive layer. A cavity extends inside the chip from its main face and is closed by a flexible film covering the main face of the chip at least in the area of the cavity. The support has a depressed portion facing the cavity and delimited by a protruding portion facing the main face of the chip. Inside the depressed portion, the adhesive layer has a greater thickness than the projecting portion so as to be able to absorb any swelling of the flexible film as a result of the expansion of the gas contained inside the cavity during thermal processes.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 17, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 8981501
    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: March 17, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Meng-Jia Lin, Chang-Sheng Hsu, Kuo-Hsiung Huang, Wei-Hua Fang, Shou-Wei Hsieh, Te-Yuan Wu, Chia-Huei Lin
  • Patent number: 8975714
    Abstract: A capacitive pressure sensor includes: a semiconductor substrate having a reference pressure chamber formed therein; a diaphragm which is formed in a front surface of the semiconductor substrate and has a ring-like peripheral through hole penetrating between the front surface of the semiconductor substrate and the reference pressure chamber and defining an upper electrode and a plurality of central through holes; a peripheral insulating layer which fills the peripheral through hole and electrically isolates the upper electrode from other portions of the semiconductor substrate; and a central insulating layer which fills the central through holes.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: March 10, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Goro Nakatani
  • Patent number: 8975118
    Abstract: An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: March 10, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Julian Gonska, Jens Frey, Heribert Weber, Eckhard Graf, Roman Schlosser
  • Patent number: 8975107
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes oxidizing a substrate to form local oxide regions that extend above a top surface of the substrate. A membrane layer is formed over the local oxide regions and the top surface of the substrate. A portion of the substrate under the membrane layer is removed. The local oxide regions under the membrane layer is removed.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: March 10, 2015
    Assignee: Infineon Techologies AG
    Inventors: Alfons Dehe, Stefan Barzen, Wolfgang Friza, Wolfgang Klein
  • Patent number: 8975096
    Abstract: A jig includes a wafer including an accommodation groove configured to accommodate a capacitive micromachined ultrasonic transducer (cMUT) when flip chip bonding is performed, and a separation groove formed in a bottom surface of the accommodation groove, the separation groove having a bottom surface that is spaced apart from thin films of the cMUT that face the bottom surface of the separation groove when the cMUT is seated on portions of the bottom surface of the accommodation groove.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 10, 2015
    Assignees: Samsung Electronics Co., Ltd., Kyungpook National University Industry-Academic Cooperation Foundation
    Inventors: Young Il Kim, Bae Hyung Kim, Jong Keun Song, Seung Heun Lee, Kyung Il Cho, Yong Rae Roh, Won Seok Lee
  • Publication number: 20150060955
    Abstract: An integrated MEMS microphone is provided, including, a bonding wafer layer, a bonding layer, an aluminum layer, CMOS substrate layer, an N+ implant doped silicon layer, a field oxide (FOX) layer, a plurality of implant doped silicon areas forming CMOS wells, a two-tier polysilicon layer with selective ion implantation forming a diaphragm, a plurality of implant doped silicon areas forming CMOS source/drain, a gate poly layer forming CMOS transistor gates, said CMOS wells, said CMOS transistor sources/drains and said CMOS gates forming CMOS transistors, an oxide layer embedded with an interconnect contact layer, a plurality of metal layers interleaved with a plurality of via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. Diaphragm is sandwiched between a small top chamber and a small back chamber, and substrate layer includes a large back chamber.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: WindTop Technology Corp.
    Inventor: Kun-Lung Chen
  • Publication number: 20150061049
    Abstract: A micromechanical component for a capacitive sensor device includes first and second electrodes. The first electrode is at least partially formed from a first semiconductor layer and/or metal layer, and at least one inner side of the second electrode facing the first electrode is formed from a second semiconductor layer and/or metal layer. A cavity is between the first and second electrodes. Continuous recesses are structured into the inner side of the second electrode and sealed off with a closure layer. At least one reinforcing layer of the second electrode and at least one contact element which is electrically connected to the first electrode, to the layer of the second electrode which forms the inner side, to at least one printed conductor, and/or to a conductive substrate area, are formed from at least one epi-polysilicon layer. Also described is a micromechanical component manufacturing method for a capacitive sensor device.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 5, 2015
    Applicant: Robert Bosch GmbH
    Inventor: Heribert WEBER
  • Publication number: 20150059485
    Abstract: A micromechanical sensor system includes a micromechanical sensor chip surrounded at least laterally by a molded housing which has a front side and a rear side. The micromechanical sensor chip includes a chip area on the rear side, which is omitted from the molded housing, and a rewiring device formed on the rear side, which, starting from the chip area, extends to the surrounding molded housing on the rear side, and from there, past at least one via from the rear side to the front side of the molded housing.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Applicant: ROBERT BOSCH GMBH
    Inventors: Frieder Haag, Hubert Benzel
  • Patent number: 8962368
    Abstract: The present invention relates to a CMOS compatible MEMS microphone, comprising: an SOI substrate, wherein a CMOS circuitry is accommodated on its silicon device layer; a microphone diaphragm formed with a part of the silicon device layer, wherein the microphone diaphragm is doped to become conductive; a microphone backplate including CMOS passivation layers with a metal layer sandwiched and a plurality of through holes, provided above the silicon device layer, wherein the plurality of through holes are formed in the portions thereof opposite to the microphone diaphragm, and the metal layer forms an electrode plate of the backplate; a plurality of dimples protruding from the lower surface of the microphone backplate opposite to the diaphragm; and an air gap, provided between the diaphragm and the microphone backplate, wherein a spacer forming a boundary of the air gap is provided outside of the diaphragm or on the edge of the diaphragm.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: February 24, 2015
    Assignee: Goertek, Inc.
    Inventor: Zhe Wang
  • Patent number: 8962367
    Abstract: The present disclosure provides a method of fabricating a micro-electro-mechanical systems (MEMS) device. In an embodiment, a method includes providing a substrate including a first sacrificial layer, forming a micro-electro-mechanical systems (MEMS) structure above the first sacrificial layer, and forming a release aperture at substantially a same level above the first sacrificial layer as the MEMS structure. The method further includes forming a second sacrificial layer above the MEMS structure and within the release aperture, and forming a first cap over the second sacrificial layer and the MEMS structure, wherein a leg of the first cap is disposed between the MEMS structure and the release aperture. The method further includes removing the first sacrificial layer, removing the second sacrificial layer through the release aperture, and plugging the release aperture. A MEMS device formed by such a method is also provided.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Lin, Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 8955212
    Abstract: A micro-electro-mechanical microphone and manufacturing method thereof are provided. The micro-electro-mechanical microphone includes a diaphragm, which is formed on a surface of one side of a semiconductor substrate, exposed to the outside surroundings, and can vibrate freely under the pressure generated by sound waves; an electrode plate with air holes, which is under the diaphragm; an isolation structure for fixing the diaphragm and the electrode plate; an air gap cavity between the diaphragm and the electrode plate, and a back cavity under the electrode plate and in the semiconductor substrate; and a second cavity formed on the surface of the same side of the semiconductor substrate and in an open manner The air gap cavity is connected with the back cavity through the air holes of the electrode plate The back cavity is connected with the second cavity through an air groove formed in the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 17, 2015
    Assignee: Lexvu Opto Microelectronics Technology (Shanghai) Ltd
    Inventors: Jianhong Mao, Deming Tang
  • Patent number: 8951819
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a split-beam laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: February 10, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, Aparna Iyer
  • Publication number: 20150035089
    Abstract: A method for forming a MEMS device is provided. The method includes the following steps of providing a substrate having a first portion and a second portion; fabricating a membrane type sensor on the first portion of the substrate; and fabricating a bulk silicon sensor on the second portion of the substrate.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: YU-CHIA LIU, CHIA-HUA CHU, JUNG-HUEI PENG, KUEI-SUNG CHANG, CHUN-WEN CHENG