Using Shadow Mask Patents (Class 438/531)
  • Patent number: 9740104
    Abstract: Systems and methods for processing a substrate include exposing a substrate to UV light from a UV light source having a predetermined wavelength range. The substrate includes a photoresist layer that has been bombarded with ions. The method includes controlling a temperature of the substrate, while exposing the substrate to the UV light, to a temperature less than or equal to a first temperature. The method includes removing the photoresist layer using plasma while maintaining a temperature of the substrate to less than or equal to a strip process temperature after exposing the substrate to the UV light.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: August 22, 2017
    Assignee: Lam Research Corporation
    Inventors: Ivan L. Berry, III, Glen Gilchrist
  • Patent number: 9029049
    Abstract: Various embodiments provide a method for processing a carrier, the method including changing the three-dimensional structure of a mask layer arranged over the carrier so that at least two mask layer regions are formed having different mask layer thicknesses; and applying an ion implantation process to the at least two mask layer regions to form at least two implanted regions in the carrier having different implantation depth profiles.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Jens Schneider, Henning Feick, Marcel Heller, Dieter Kaiser
  • Patent number: 9029249
    Abstract: Disclosed is a plasma doping apparatus provided with a plasma generating mechanism. The plasma generating mechanism includes a microwave generator that generates microwave for plasma excitation, a dielectric window that transmits the microwave generated by the microwave generator into a processing container, and a radial line slot antenna formed with a plurality of slots. The radial line slot antenna radiates the microwave to the dielectric window. A control unit controls the plasma doping apparatus such that a doping gas and a gas for plasma excitation are supplied into the processing container by a gas supply unit in a state where the substrate is placed on a holding unit, and then plasma is generated by the plasma generating mechanism to perform doping on the substrate such that the concentration of the dopant implanted into the substrate is less than 1×1013 atoms/cm2.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hirokazu Ueda, Masahiro Oka, Masahiro Horigome, Yuuki Kobayashi
  • Publication number: 20150099351
    Abstract: A method for fabricating a semiconductor device is provided. An ion implantation mask exposing a portion of a semiconductor substrate is formed on the semiconductor substrate. The implantation mask includes a second hardmask layer having a first thickness and a second hardmask layer having a second thickness. The first hardmask layer is disposed between the second hardmask layer and the semiconductor substrate. An ion implantation process is performed on the exposed portion of the semiconductor substrate using the implantation mask. The implantation mask is removed without forming an etch mask layer on the exposed portion of the semiconductor substrate.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-Hun Choi, Chan-Sam Chang
  • Publication number: 20140374819
    Abstract: An n? drift layer is a parallel pn layer having an n-type region and a p-type region are alternately arranged in the direction parallel to the main surface so as to come into contact with each other, and have a width in a direction parallel to the main surface of the substrate which is less than a length in a direction perpendicular to the main surface of the substrate. A second-main-surface-side lower end portion of the p-type region has a structure in which a high-concentration lower end portion and a low-concentration lower end portion of a p-type low-concentration region are repeated at a predetermined pitch in the direction parallel to the main surface of the substrate. It is possible to provide a super junction MOS semiconductor device which can improve a trade-off relationship between turn-off loss and turn-off dv/dt and improve avalanche resistance.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Inventors: Yasushi NIIMURA, Toshiaki SAKATA
  • Patent number: 8912082
    Abstract: Methods to form complementary implant regions in a workpiece are disclosed. A mask may be aligned with respect to implanted or doped regions on the workpiece. The mask also may be aligned with respect to surface modifications on the workpiece, such as deposits or etched regions. A masking material also may be deposited on the implanted regions using the mask. The workpiece may be a solar cell.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: December 16, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, William T. Weaver, Paul Sullivan, John W. Graff
  • Patent number: 8900982
    Abstract: Herein, an improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be achieved using a mask for processing the substrate. The mask may be incorporated into a substrate processing system such as, for example, an ion implantation system. The mask may comprise one or more first apertures disposed in a first row; and one or more second apertures disposed in a second row, each row extending along a width direction of the mask, wherein the one or more first apertures and the one or more second apertures are non-uniform.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: December 2, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin M. Daniels, Russell L. Low, Nicholas P. T. Bateman, Benjamin B. Riordon
  • Publication number: 20140231970
    Abstract: Various embodiments provide a method for processing a carrier, the method including changing the three-dimensional structure of a mask layer arranged over the carrier so that at least two mask layer regions are formed having different mask layer thicknesses; and applying an ion implantation process to the at least two mask layer regions to form at least two implanted regions in the carrier having different implantation depth profiles.
    Type: Application
    Filed: February 20, 2013
    Publication date: August 21, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Jens Schneider, Henning Feick, Marcel Heller, Dieter Kaiser
  • Patent number: 8765495
    Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Hsiu Lee, Guo-Xin Hu, Qiao-Yuan Liu, Yen-Sheng Wang
  • Patent number: 8716115
    Abstract: Dual shadow mask design can overcome the size and resolution limitations of shadow masks to provide capacitor structures with small effective areas. The capacitor structures have bottom and top electrode layers patterned using shadow masks, sandwiching a dielectric layer. The effective areas of the capacitors are the overlapping areas of the top and bottom electrodes, thus allowing small area sizes without subjected to the size limitation of the electrodes. The dual shadow mask design can be used in conjunction with high productivity combinatorial processes for screening and optimizing dielectric materials and fabrication processes.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: May 6, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Prashant B. Phatak
  • Patent number: 8716114
    Abstract: A semiconductor device manufacturing method includes exciting plasma, applying RF power onto a target substrate to generate substrate bias and performing an ion implantation plural times by applying the RF power in the form of pulses.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: May 6, 2014
    Assignees: National University Corporation Tohoku University, Tokyo Electron Limited
    Inventors: Tadahiro Ohmi, Tetsuya Goto, Akinobu Teramoto, Takaaki Matsuoka
  • Patent number: 8710633
    Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: April 29, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Hao Huang, Ying-Shiou Lin
  • Publication number: 20140061860
    Abstract: A compound semiconductor device and method of fabricating the same according to the present invention is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region, and a semiconductor layer disposed on the substrate, wherein doping conditions of said first doped region and said second doped region may be different from each other.
    Type: Application
    Filed: August 26, 2013
    Publication date: March 6, 2014
    Applicant: FORMOSA EPITAXY INCORPORATED
    Inventors: CHUN-JU TUN, YI-CHAO LIN, CHEN-FU CHIANG, CHENG-HUANG KUO
  • Patent number: 8637385
    Abstract: According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: January 28, 2014
    Assignee: Broadcom Corporation
    Inventors: Akira Ito, Henry KuoShun Chen
  • Patent number: 8569157
    Abstract: An improved method of moving a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. After the substrate is exposed to the ion beam, the mask is indexed to a new position relative to the substrate and a subsequent implant step is performed. Through the selection of the aperture size and shape, the index distance and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions. In other embodiments, the implant pattern is suitable for use with a bus-bar structure.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 29, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Benjamin B. Riordon, Nicholas P. T. Bateman, Charles T. Carlson
  • Patent number: 8524586
    Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 3, 2013
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Hao Huang, Ying-Shiou Lin
  • Patent number: 8519403
    Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: August 27, 2013
    Assignee: Altera Corporation
    Inventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
  • Patent number: 8476153
    Abstract: A method of manufacturing a semiconductor device that includes a semiconductor substrate is provided. The method includes: exposing a photoresist coated on the semiconductor substrate using a photomask including a plurality of regions having different light transmittances; developing the photoresist to form a resist pattern including a plurality of regions having different thicknesses that depend on an exposure amount of the photoresist; and implanting impurity ions into the semiconductor substrate through the plurality of regions of the resist pattern having different thicknesses to form a plurality of impurity regions whose depths from a surface of the semiconductor substrate to peak positions are different from each other. The depths to the peak positions depend on the thickness of the resist pattern through which the implanted impurity ions pass.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: July 2, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoyuki Tezuka, Mahito Shinohara, Yasuhiro Kawabata
  • Patent number: 8461553
    Abstract: An improved method of producing solar cells utilizes a mask which is fixed relative to an ion beam in an ion implanter. The ion beam is directed through a plurality of apertures in the mask toward a substrate. The substrate is moved at different speeds such that the substrate is exposed to an ion dose rate when the substrate is moved at a first scan rate and to a second ion dose rate when the substrate is moved at a second scan rate. By modifying the scan rate, various dose rates may be implanted on the substrate at corresponding substrate locations. This allows ion implantation to be used to provide precise doping profiles advantageous for manufacturing solar cells.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: June 11, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Steven M. Anella, Benjamin B. Riordon, Atul Gupta
  • Patent number: 8445384
    Abstract: Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventor: Abhisek Dixit
  • Patent number: 8372708
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: February 12, 2013
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K Lui
  • Patent number: 8372737
    Abstract: An improved method of implanting a solar cell is disclosed. A substrate is coated with a soft mask material. A shadow mask is used to perform a pattern ion implant and to set the soft mask material. After the soft mask material is set, the mask is removed and a blanket implant is performed.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: February 12, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Benjamin B. Riordon, Atul Gupta
  • Patent number: 8334193
    Abstract: Provided is a method of manufacturing a semiconductor device capable of preventing a relative displacement of the positions between a range where impurity ions are injected and a range where charged particles are injected. The method of manufacturing the semiconductor device includes: irradiating impurity ions in a state in which a mask is disposed between an impurity ion irradiation apparatus and a semiconductor substrate; and irradiating charged particles to form a short carrier lifetime region, in a state in which the mask is disposed between a charged particle irradiation apparatus and the semiconductor substrate. A relative positional relationship between the mask and the semiconductor substrate is not changed from a beginning of one of the irradiating the impurity ions and the irradiating the charged particles to a completion of both of the irradiating the impurity ions and the irradiating the charged particles.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 18, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Shinya Iwasaki, Akira Kamei
  • Patent number: 8330128
    Abstract: This apparatus has two mask segments. Each mask segment has apertures that an ion beam may pass through. These mask segments can move between a first and second position using hinges. One or more workpieces are disposed behind the mask segments when these mask segments are in a second position. The two mask segments are configured to cover the one or more workpieces in one instance. Ions are implanted into the one or more workpieces through the apertures in the mask segments.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: December 11, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Robert B. Vopat, William T. Weaver, Charles T. Carlson
  • Patent number: 8328936
    Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 11, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Publication number: 20120244692
    Abstract: An improved, lower cost method of processing substrates, such as to create solar cells is disclosed. In addition, a modified substrate carrier is disclosed. The carriers typically used to carry the substrates are modified so as to serve as shadow masks for a patterned implant. In some embodiments, various patterns can be created using the carriers such that different process steps can be performed on the substrate by changing the carrier or the position with the carrier. In addition, since the alignment of the substrate to the carrier is critical, the carrier may contain alignment features to insure that the substrate is positioned properly on the carrier. In some embodiments, gravity is used to hold the substrate on the carrier, and therefore, the ions are directed so that the ion beam travels upward toward the bottom side of the carrier.
    Type: Application
    Filed: June 5, 2012
    Publication date: September 27, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Nicholas Bateman, Kevin Daniels, Atul Gupta, Russell Low, Benjamin Riordon, Robert Mitchell, Steven Anella
  • Patent number: 8258052
    Abstract: A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 4, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Okuno, Yoichiro Tarui
  • Patent number: 8258042
    Abstract: Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: September 4, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Yin-Fu Huang, Ming Rong Chang, Shih-Chin Lien
  • Patent number: 8252670
    Abstract: The invention relates to a production method of a lateral electro-optical modulator on an SOI substrate, the modulator comprising a rib waveguide formed in the thin layer of silicon of the SOI substrate, the rib waveguide being placed between a doped region P and a doped region N formed in the thin layer of silicon, the rib waveguide occupying an intrinsic region of the thin layer, at least one doped zone P being formed in the rib and perpendicularly to the substrate. The method comprises masking steps of the thin layer of silicon to define therein the rib of the waveguide, etching of the rib, masking of the thin layer of silicon to delimit the parts to be doped P, doping of the parts to be doped P, masking of the thin layer of silicon to delimit the region to be doped N and doping of the region to be doped N.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: August 28, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Jean-Marc Fedeli
  • Patent number: 8242005
    Abstract: A first species is directed through a first mask with a first aperture and a second mask with a second aperture. The first aperture and second aperture may be different shapes or have different spacing. The first species may be implanted in pattern defining non-implanted regions surrounded by implanted regions. These implanted regions are a sum of said first ion species implanted through said first aperture and said second aperture. Thus, the non-implanted regions are surrounded by the implanted regions formed using the first mask and second mask. The first species also may deposit on or etch the workpiece.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: August 14, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Justin M. Ricci
  • Patent number: 8202789
    Abstract: Various masks for use with ion implantation equipment are disclosed. In one embodiment, the masks are formed by assembling a collection of segments and spacers to create a mask having the desired configuration. This collection of parts is held together with a carrier or frame. In another embodiment, a panel is formed by machining open-ended slots into a substrate, so as to form a comb-shaped device. Two such panels may be connected together to form a mask. In other embodiments, the panels may be used sequentially in an ion implantation process to create interdigitated back contacts. In another embodiment, multiple masks are overlaid so as to create implant patterns that cannot be created effectively using a single mask.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: June 19, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Steven M. Anella, William Weaver
  • Patent number: 8193018
    Abstract: A method of patterning a substrate that includes locating a single mask film over the substrate and forming first opening portions in first locations in the mask film. First electrical materials are deposited over the substrate and mask film to form patterned areas in the first locations. Second opening portions are formed in second locations different from the first locations in the mask film. Subsequently, second electrical materials are deposited over the substrate and mask film to form patterned areas in the first and second locations.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: June 5, 2012
    Assignee: Global OLED Technology LLC
    Inventor: Ronald S. Cok
  • Patent number: 8189634
    Abstract: Method of manufacturing a laser medium with a material having a surface and a dopant in the material distributed whereby the material has a spatially variant optical flux density profile uses tailored non-uniform gain profiles within a Yb:YAG laser component (rod, slab, disc, etc.) achieved by a spatial material modification in the spatially masked pre-forms. High temperature-assisted reduction leads to the coordinate-dependent gain profiles, which are controlled by the topology of the deposited solid masks. The gain profiles are obtained by reducing the charge state of the laser-active trivalent Yb3+ ions into inactive divalent Yb2+ ions. This valence conversion process is driven by mass transport of ions and oxygen vacancies. These processes, in turn, affect the dopant distribution throughout the surface and bulk laser crystal. By reducing proportionally more Yb3+ ions at the unmasked areas of component, than in the masked areas, the coordinate-dependent or spatially-controlled gain profiles are achieved.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: May 29, 2012
    Assignee: Raytheon Company
    Inventors: David S. Sumida, Robert W. Byren, Michael Ushinsky
  • Patent number: 8173527
    Abstract: An improved method of moving a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. After the substrate is exposed to the ion beam, the mask is indexed to a new position relative to the substrate and a subsequent implant step is performed. Through the selection of the aperture size and shape, the index distance and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions. In other embodiments, the implant pattern is suitable for use with a bus-bar structure.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: May 8, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Benjamin B. Riordon, Nicholas P. T. Bateman, Charles T. Carlson
  • Publication number: 20120100680
    Abstract: A process of forming an integrated circuit containing an npn BJT and an NMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting n-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the NMOS transistor. A process of forming an integrated circuit containing a pnp BJT and a PMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting p-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the PMOS transistor. A process of forming an integrated circuit containing an implant region by cooling the integrated circuit substrate to 5° C. or colder and implanting atoms, at a specified minimum dose according to species, into the implant region.
    Type: Application
    Filed: September 27, 2011
    Publication date: April 26, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ming-Yeh CHUANG
  • Patent number: 8008176
    Abstract: An improved method of producing solar cells utilizes a mask which is fixed relative to an ion beam in an ion implanter. The ion beam is directed through a plurality of apertures in the mask toward a substrate. The substrate is moved at different speeds such that the substrate is exposed to an ion dose rate when the substrate is moved at a first scan rate and to a second ion dose rate when the substrate is moved at a second scan rate. By modifying the scan rate, various dose rates may be implanted on the substrate at corresponding substrate locations. This allows ion implantation to be used to provide precise doping profiles advantageous for manufacturing solar cells.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: August 30, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Steven M. Anella, Benjamin B. Riordon, Atul Gupta
  • Patent number: 7977225
    Abstract: In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: July 12, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Andre Poock, Jan Hoentschel
  • Patent number: 7977126
    Abstract: A method for manufacturing an organic light emitting device including a photo diode and a transistor includes forming a first semiconductor layer and a second semiconductor layer on separate portions of a buffer layer formed on the substrate; forming a gate metal layer on the first semiconductor layer, the gate metal layer covering a central region of the first semiconductor layer; forming a high-concentration P doping region and a high-concentration N doping region in the first semiconductor layer by injecting impurities into regions of the first semiconductor layer not covered by the gate metal layer to form the photodiode; forming a source and drain region and a channel region in the second semiconductor layer; and removing the gate metal layer from the central region of the first semiconductor layer by etching and simultaneously forming a gate electrode by etching, the gate electrode being insulated from the channel region of the second semiconductor layer, to form the transistor.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: July 12, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Yun-gyu Lee, Hye-hyang Park, Ki-ju Im, Byoung-deog Choi
  • Patent number: 7955929
    Abstract: A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 7, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Evgueniy Stefanov, Ivana Deram, Jean-Michel Reynes
  • Publication number: 20110092059
    Abstract: Herein, an improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be achieved using a mask for processing the substrate. The mask may be incorporated into a substrate processing system such as, for example, an ion implantation system. The mask may comprise one or more first apertures disposed in a first row; and one or more second apertures disposed in a second row, each row extending along a width direction of the mask, wherein the one or more first apertures and the one or more second apertures are non-uniform.
    Type: Application
    Filed: April 7, 2010
    Publication date: April 21, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Kevin M. Daniels, Russell J. Low, Nicholas P.T. Bateman, Benjamin B. Riordon
  • Patent number: 7927969
    Abstract: A method and an equipment for cleaning masks used for photolithography steps, including at least one step of thermal treatment under pumping at a pressure lower than the atmospheric pressure and at a temperature greater than the ambient temperature.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: April 19, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Christophe Martin
  • Patent number: 7883909
    Abstract: A device and method for measuring ion beam angle with respect to a substrate is disclosed. The method includes forming a plurality of shadowing structures extending substantially perpendicular from an upper surface of the substrate, directing an ion beam toward the substrate, the plurality of shadowing structures interrupting an incident angle of the ion beam to define implanted and non-implanted portions of the substrate. The method further includes measuring the dose of implanted species within the substrate, determining an implanted surface area as a function of measuring the dose of implant, determining non-implanted surface area based on the implanted surface area, and obtaining the ion beam angle as a function of the non-implanted surface area.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: James David Bernstein
  • Patent number: 7884001
    Abstract: Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a gate over a semiconductor substrate, a first impurity region over the semiconductor substrate, a second impurity region over the semiconductor substrate, the second impurity region being shallower than the first impurity region, and a third impurity region formed in the first impurity region, and bent toward the gate at a predetermined angle. According to embodiments, the third impurity region may be an n-type impurity region. According to embodiments, an area of a photodiode may be increased and a transfer efficiency of electrons generated from a photodiode may be increased.
    Type: Grant
    Filed: December 27, 2008
    Date of Patent: February 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Joung-Ho Lee
  • Patent number: 7883946
    Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: February 8, 2011
    Assignee: Altera Corporation
    Inventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
  • Patent number: 7871908
    Abstract: The method of manufacturing a semiconductor device comprising: forming a first hard mask layer and a second hard mask layer on the layer to be etched (S11); a first groove-forming mask pattern forming process for forming a groove-forming mask pattern which has a first pitch, is formed of the second hard mask layer, and is used as an etching mask when forming groove patterns(S12-S14); and a first concave portion-forming mask pattern forming process for etching the first hard mask layer using the second resist pattern as an etching mask, wherein the second resist pattern is formed of the second resist layer having an opening portion that has a fourth pitch and the first organic layer having an opening portion that is connected to an opening portion of the second resist layer and has a smaller size than the opening portion of the second resist layer (S15-S18).
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: January 18, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Koichi Yatsuda, Eiichi Nishimura
  • Patent number: 7816273
    Abstract: Resist masks exposed to high-dose implantation processes may be efficiently removed on the basis of a combination of a plasma-based etch process and a wet chemical etch recipe, wherein both etch steps may include a highly selective etch chemistry in order to minimize substrate material loss and thus dopant loss in sophisticated semiconductor devices. The first plasma-based etch step may provide under-etched areas of the resist mask, which may then be efficiently removed on the basis of the wet chemical etch process.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: October 19, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christian Krueger, Volker Grimm, Lutz Eckart
  • Patent number: 7767562
    Abstract: A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: August 3, 2010
    Assignee: Qimonda AG
    Inventors: Helmut Horst Tews, Jochen Beintner
  • Publication number: 20100173462
    Abstract: A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least one trench in the gate dielectric (e.g., a back gate dielectric) and back gate adjacent to the local gate electrode. Another aspect of the invention is a nanotube field-effect transistor fabricated using such a method.
    Type: Application
    Filed: March 19, 2010
    Publication date: July 8, 2010
    Applicant: International Business Machines Corporation
    Inventors: Joerg Appenzeller, Phaedon Avouris, Yu-Ming Lin
  • Patent number: 7749874
    Abstract: A CMOS image sensor includes a pinned photodiode and a transfer gate that are formed using a thick mask that is self-aligned to at least one edge of the polysilicon gate structure to facilitate both the formation of a deep implant and to provide proper alignment between the photodiode implant and the gate. In one embodiment a drain side implant is formed concurrently with the deep n-type implant of the photodiode. After the deep implant, the mask is removed and a shallow p+ implant is formed to complete the photodiode. In another embodiment, the polysilicon is etched to define only a drain side edge, a shallow drain side implant is performed, and then a thick mask is provided and used to complete the gate structure, and is retained during the subsequent high energy implant. Alternatively, the high energy implant is performed prior to the shallow drain side implant.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: July 6, 2010
    Assignee: Tower Semiconductor Ltd.
    Inventors: Clifford I. Drowley, David Cohen, Assaf Lahav, Shai Kfir, Naor Inbar, Anatoly Sergienko, Vladimir Korobov
  • Publication number: 20100124799
    Abstract: Techniques for manufacturing solar cells are disclosed. In one particular exemplary embodiment, the technique may comprise disposing a mask upstream of the solar cell, the mask comprising a plurality of filaments spaced apart from one another to define at least one aperture; directing a ribbon ion beam of desired species toward the solar cell to ion implant a portion of the solar cell defined by the at least one aperture of the mask; and orienting the ribbon ion beam such that longer cross-section dimension of the ribbon beam is perpendicular to the aperture in one plane.
    Type: Application
    Filed: October 19, 2009
    Publication date: May 20, 2010
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Julian G. BLAKE, Kevin M. Daniels