Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1 (W2/T)<??tan?1 (W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21).

Abstract: A method for manufacturing the CMOS image sensor comprising forming an epitaxial layer provided with a plurality of photo diodes on a semiconductor substrate, coating a first photo resist on the epitaxial layer and performing a patterning process on the first photo resist using a predetermined reference value in order to form a first photo resist pattern, coating a second photo resist on the epitaxial layer and first photo resist pattern and performing a patterning process for the second photo resist in order to form the second photo resist pattern on the first photo resist pattern; and forming a well area of a pixel area by performing a dopant implantation process using a mask pattern including the first photo resist pattern and the second photo resist pattern.

Abstract: A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.

Abstract: The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

Abstract: A method of making a semiconductor device includes forming a pillar shaped semiconductor device surrounded by an insulating layer such that a contact hole in the insulating layer exposes an upper surface of the semiconductor device. The method also includes forming a shadow mask layer over the insulating layer such that a portion of the shadow mask layer overhangs a portion of the contact hole, forming a conductive layer such that a first portion of the conductive layer is located on the upper surface of the semiconductor device exposed in the contact hole and a second portion of the conductive layer is located over the shadow mask layer, and removing the shadow mask layer and the second portion of the conductive layer.

Abstract: A pattern image generation device generates a pattern image, and at least a part of the pattern image which has been generated or the pattern image which is generated and is formed on an object is photoelectrically detected by a detection system. Then, a correction device corrects design data that should be input to the pattern image generation device based on the detection results. Accordingly, a pattern image is generated on an object by the pattern image generation device corresponding to the input of the design data after the correction, and because the object is exposed using the pattern image, a desired pattern is formed on the object with good precision.

Abstract: Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a gate over a semiconductor substrate, a first impurity region over the semiconductor substrate, a second impurity region over the semiconductor substrate, the second impurity region being shallower than the first impurity region, and a third impurity region formed in the first impurity region, and bent toward the gate at a predetermined angle. According to embodiments, the third impurity region may be an n-type impurity region. According to embodiments, an area of a photodiode may be increased and a transfer efficiency of electrons generated from a photodiode may be increased.

Abstract: Methods of fabricating a semiconductor device are provided. A photoresist pattern can be formed on an implantation target layer, and conductive impurities can be implanted into the implantation target layer using the photoresist pattern as a mask. A portion of the photoresist pattern can be removed, conductive impurities implanted in the photoresist pattern can be cleaned, and the remaining portion of the photoresist pattern can be removed.

Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are applied to the device.

Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first surface and a second surface which is arranged opposite to the first surface. The semiconductor substrate includes a plurality of trench structures extending from the first surface into the semiconductor substrate. The thickness of the semiconductor substrate is then reduced by removing semiconductor material at the second surface to obtain a processed second surface with exposed bottom portions of the trench structures. At least a first mask is formed on the processed second surface in a self-aligned manner with respect to the bottom portions of the trench structures, and doping regions are formed in the semiconductor substrate between the trench structures.

Abstract: The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

Abstract: A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

Abstract: A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for forming a drain region and a source region. The two doped regions are arranged in the substrate flush with the face of the substrate on each side of a region of the substrate located under the gate for forming a channel between the drain and source regions. At least one region of doping agents of the second type of conductivity is implanted only in the channel.

Abstract: A memory structure including a substrate, dielectric patterns, spacer patterns, a first dielectric layer, a conductor pattern, a second dielectric layer and doped regions is described. The dielectric patterns are disposed on the substrate. The spacer patterns are disposed on each sidewall of each of the dielectric patterns respectively. The first dielectric layer is disposed between the spacer patterns and the substrate. The conductor pattern is disposed on the substrate and covers the spacer patterns. The second dielectric layer is disposed between the spacer patterns and the conductor pattern. The doped regions are disposed in the substrate under each of the dielectric patterns respectively.

Abstract: A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.

Abstract: A semiconductor component includes a semiconductor body having an edge with an edge zone of a first conductivity type. Charge compensation regions of a second conductivity type are embedded into the edge zone, with the charge compensation regions extending from a top side of the semiconductor component vertically into the semiconductor body. For the number Ns of charge carriers present in a volume Vs between two charge compensation regions that are adjacent in a direction perpendicular to the edge, and for the number Np of charge carriers present in a volume Vp between two charge compensation regions that are adjacent in a direction parallel to the edge, Np>Ns holds true.

Abstract: An alignment mark forming method according to the present invention includes: an alignment mark forming step of using an impurity implantation region as an alignment target layer and using, as a mask, the same resist film used for forming the impurity implantation region to form an alignment mark that is used when a patterning is performed in at least one of a subsequent impurity implantation step and a subsequent process layer forming step.

Abstract: An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar spiral. A region of the substrate below the inductor are removed to lower the inductive Q factor.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes implanting ions into an n-channel metal oxide semiconductor (NMOS) region of a semiconductor substrate so as to form a channel. The implanting can be performed by implanting boron ions at an ion implanting energy of 20 keV to 100 keV using a photoresist layer formed on the semiconductor substrate as an ion implanting mask for inhibiting ions from entering the semiconductor substrate below the photoresist layer. The photoresist layer can be a mid-ultra-violet photoresist having a reduced thickness.

Abstract: This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film.

Abstract: Provided is a method of fabricating a lateral double diffused MOSFET. In the method, ions are implanted onto a substrate to form a body region of the LDMOS transistor using a photoresist pattern as an ion implantation mask. Herein, the photoresist can be patterned to have a slope of with an angle in the range of 87° to 88°.

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

Abstract: A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.

Abstract: A method of crystallizing amorphous silicon using a mask having a transmitting portion including a plurality of stripes, wherein end lines of at least two stripes are not collinear; and a blocking portion enclosing the plurality of stripes includes the steps of setting the mask over a substrate having an amorphous silicon layer, applying a first laser beam to a first area of the amorphous silicon layer through the mask, thereby forming a first crystallization region, moving the substrate in a first direction, thereby disposing the blocking portion of the mask over the first crystallization region, and applying a second laser beam to the first area of the amorphous silicon layer through the mask, thereby forming a second crystallization region.

Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle ? of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1(W2/T)<??tan?1(W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21). When the implant angle ? is controlled within that range, impurity ions (231, 232) are implanted into a second side surface (10A2) and a fifth side surface (10A5) through a silicon oxide film (13).

Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.

Abstract: An asymmetric hetero-doped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a second polarity. A source region is disposed inside each tub region and has dopants of a first polarity opposite to the second polarity. On the other side of the gate, heterodoped buffer and drift regions are formed. The buffer regions comprise dopants of the second polarity. The drift regions are disposed inside the buffer regions and are doped with dopants of the first polarity. A drain n+ tap region is disposed in the drift region.

Abstract: The invention includes a method of patterning radiation. The radiation is simultaneously passed through a structure and through a subresolution assist feature that is transmissive of at least a portion of the radiation. The subresolution assist feature alters a pattern of radiation intensity defined by the structure relative to a pattern of radiation intensity that would be defined in the absence of the subresolution assist feature. The invention further includes methods of forming radiation-patterning tools, and the radiation-patterning tools themselves.

Abstract: A method for manufacturing a vertical Schottky diode with a guard ring on a lightly-doped N-type silicon carbide layer, including forming a P-type epitaxial layer on the N-type layer; implanting N-type dopants in areas of the P-type epitaxial layer to neutralize in these areas, across the entire thickness of the epitaxial layer, the P-type dopants to form N-type regions, of dopant concentration lower than that of the epitaxial layer, and delimiting a P-type guard ring; forming on the external periphery of the component an insulating layer partially covering the guard ring; and forming a Schottky contact with the N-type region internal to the guard ring.

Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.

Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle ? of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1(W2/T)<??tan?1(W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21). When the implant angle ? is controlled within that range, impurity ions (231, 232) are implanted into a second side surface (10A2) and a fifth side surface (10A5) through a silicon oxide film (13).

Abstract: Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.

Abstract: A mask frame assembly includes a frame having an opening and a mask having at least two unit mask elements. Both ends of each unit mask element are fixed to the frame in a state of tension. The unit mask elements include a unit masking pattern, and overlap each other on a predetermined width to form a single mask pattern block. Each unit mask element has a recessed wall in an overlapping portion thereof so as to maintain the thickness of the mask constant at an overlap between the unit mask elements. Accordingly, the mask frame assembly reduces distortion in an evaporation pattern due to an increase in the size of a mask pattern, facilitates the adjustment of a total pitch of evaporation patterns, and prevents evaporation from occurring at undesired positions.

Abstract: An embodiment of an encapsulated OLED device is described. This embodiment of the encapsulated OLED device is formed by: fabricating multiple OLED devices on a substrate; depositing at least one planarization layer on the OLED devices; hardening the at least one planarization layer in a patterned manner such that the hardened region substantially covers the OLED device; removing areas of the at least one planarization layer that are not hardened; and selectively depositing at least one barrier layer over the hardened region.

Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.

Abstract: A magnetoresistive (MR) sensor can be shaped using ion beam irradiation and/or implantation through a mask introduced between a MR structure and an ion source. The mask covers selected portions of the MR structure to define the track width of the sensor. Ion irradiation and/or implantation reduces the magnetoresistance of the unmasked portions while leaving the masked portion substantially unaltered. The mask can be a photoresist mask, an electron beam resist mask, or a stencil mask. Alternatively the mask may be part of a projection ion beam system. Track width resolution is determined at the mask production step. The edges of the sensor can be defined by a highly collimated ion beam producing an extremely straight transition edge, which reduces sensor noise and improves sensor track width control. Improved hard bias layers that directly abut the sensor may be used to achieve a suitable stability. A variety of longitudinal bias schemes are compatible with ion beam patterning.

Abstract: At the surface of a substrate a gate oxide layer is produced and is given a dual thickness. A first oxide layer is produced over the surface of a substrate by thermal oxidation and is covered by a mask layer defining suitably located openings. A material accelerating or retarding the oxidation of the substrate is ion implanted through the first oxide layer in the openings, after which the mask is removed and the thermal oxidation is continued over the now exposed total surface of the first oxide layer. The material used for ion implanting can be an oxidation rate promoting material such as chloride and bromine. The manufacturing method is simple and adds little to presently used process flows for fabricating MOS devices. The dual thickness of the gate oxide gives the manufactured MOS device a low level of total noise generated when using the device for instance in RF-circuits.

Abstract: A semiconductor device includes a gate electrode formed on a semiconductor region via a gate insulative film and an extension high concentration diffusion layer of a first conductivity type formed in the semiconductor region beside the gate electrode. A dislocation loop defect layer is formed in a region of the semiconductor region beside the gate electrode and at a position shallower than an implantation projected range of the extension high concentration diffusion layer.

Abstract: A semiconductor device includes doped regions of a substrate spaced at selected distances from features at an upper surface of the substrate. According to an example embodiment of the present invention, the doped regions are implanted and spaced apart from the features with the height of the features and the angle of an implant used for implanting the doped regions setting the space between the doped regions and the features. In one implementation, the height of the features is varied (e.g., with the features being defined using different steps, such as photolithography) to set the spacing of different doped regions. In another implementation, the angle of the implant is varied to set the spacing for different doped regions. In still another implementation, both the height of the features and angle of the implant are varied to set the spacing for different doped regions.

Abstract: When an opening diameter of a top end of a substantially column-shaped contact hole is S1, an opening diameter of a top end of a substantially column-shaped contact hole is T1, and a thickness of a silicon insulating layer is h, then contact holes are formed so as to satisfy the following conditional expression 1. T1/h<tan &thgr;1<S1/h (expression 1). With this formation method, a manufacturing method of a semiconductor device can be provided which does not need covering processing using a photolithography technique when impurity regions of different conductivity types are formed using contact holes.

Abstract: A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening to capture any implanted ions scattered in the resist and deflected out of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

Abstract: A method used during the formation of a semiconductor device reduces ion channeling during implantation of the wafer. The method comprises providing a semiconductor wafer and an unetched transistor gate stack assembly over the wafer. The unetched transistor gate stack assembly comprises a gate oxide layer, a control gate layer, a metal layer, and a dielectric capping layer. A patterned photoresist layer is formed over the unetched transistor gate stack assembly, then each of the capping layer, the metal layer, the control gate layer, and the gate oxide layer is etched to form a plurality of laterally-spaced transistor gate stacks. A screening layer is formed overlying the semiconductor wafer between the transistor gate stacks. A dopant is implanted into the semiconductor wafer through the screening layer, then the screening layer is removed.

Abstract: A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.

Abstract: A method for manufacturing an electronic device is provided. In one example of the method, the method prevents deformation of a resist mask caused by the irradiation of exposure light. The resist mask has a resist as an opaque element, and can afford mask patterns undergoing little change even with an increase in the number of wafers subjected to exposure processing. The resist mask maintains a high dimensional accuracy. A photomask pattern is formed using as an opaque element a resist comprising a base resin and Si incorporated therein or a resist with a metal such as Si incorporated thereby by a silylation process, to improve the resistance to active oxygen. The deformation of a resist opaque pattern in a photomask is prevented. The dimensional accuracy of patterns transferred onto a Si wafer is improved in repeated use of the photomask.

Abstract: A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.