By Application Of Corpuscular Or Electromagnetic Radiation (e.g., Electron, Laser, Etc.) Patents (Class 438/535)
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Patent number: 8084331Abstract: In a method of treating a semiconductor element which at least includes a semiconductor, a threshold voltage of the semiconductor element is changed by irradiating the semiconductor with light with a wavelength longer than an absorption edge wavelength of the semiconductor. The areal density of in-gap states in the semiconductor is 1013 cm?2eV?1 or less. The band gap may be 2 eV or greater. The semiconductor may include at least one selected from the group consisting of In, Ga, Zn and Sn. The semiconductor may be one selected from the group consisting of amorphous In—Ga—Zn—O (IGZO), amorphous In—Zn—O (IZO) and amorphous Zn—Sn—O (ZTO). The light irradiation may induce the threshold voltage shift in the semiconductor element, the shift being of the opposite sign to the threshold voltage shift caused by manufacturing process history, time-dependent change, electrical stress or thermal stress.Type: GrantFiled: March 2, 2009Date of Patent: December 27, 2011Assignee: Canon Kabushiki KaishaInventors: Masato Ofuji, Katsumi Abe, Hisae Shimizu, Ryo Hayashi, Masafumi Sano, Hideya Kumomi, Yasuyoshi Takai, Takehiko Kawasaki, Norio Kaneko
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Patent number: 8080467Abstract: In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns.Type: GrantFiled: May 10, 2010Date of Patent: December 20, 2011Assignee: President and Fellows of Harvard CollegeInventors: James Edward Carey, III, Eric Mazur
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Patent number: 8076226Abstract: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface of the substrate; and a light source facing a top surface of the substrate, configured to irradiate a pulsed light at a pulse width of about 0.1 ms to about 100 ms on the entire top surface of the substrate.Type: GrantFiled: September 17, 2008Date of Patent: December 13, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Takayuki Ito
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Patent number: 8067303Abstract: A solid state energy conversion device and method of making is disclosed for converting energy between electromagnetic and electrical energy. The solid state energy conversion device comprises a wide bandgap semiconductor material having a first doped region. A thermal energy beam is directed onto the first doped region of the wide bandgap semiconductor material in the presence of a doping gas for converting a portion of the first doped region into a second doped region in the wide bandgap semiconductor material. A first and a second Ohmic contact are applied to the first and the second doped regions of the wide bandgap semiconductor material. In one embodiment, the solid state energy conversion device operates as a light emitting device to produce electromagnetic radiation upon the application of electrical power to the first and second Ohmic contacts.Type: GrantFiled: September 12, 2007Date of Patent: November 29, 2011Assignee: Partial Assignment University of Central FloridaInventors: Nathaniel R. Quick, Aravinda Kar
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Patent number: 8062965Abstract: An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B2F4. Synthesis methods for such compounds, and ion implantation methods using such compounds, are described, as well as storage and dispensing vessels in which the isotopically-enriched, boron-containing compound is advantageously contained for subsequent dispensing use.Type: GrantFiled: March 15, 2011Date of Patent: November 22, 2011Assignee: Advanced Technology Materials, Inc.Inventors: Robert Kaim, Joseph D. Sweeney, Oleg Byl, Sharad N. Yedave, Edward E. Jones, Peng Zou, Ying Tang, Barry Lewis Chambers, Richard S. Ray
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Publication number: 20110269263Abstract: In a method for implanting impurities into a substrate and a method for manufacturing a solar cell using the method, a substrate is dipped into a first solution including a first impurity, and a laser is irradiated to a first region of the substrate dipped into the first solution is irradiated with laser to implant a first dopant generated from the first impurity into the first region. Accordingly, the first dopant generated from the first impurity is implanted into the substrate at room temperature to improve reliability for implanting the first dopant.Type: ApplicationFiled: December 3, 2010Publication date: November 3, 2011Inventor: Yoon-Mook KANG
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Patent number: 8040604Abstract: An imaging system is presented for imaging objects within a field of view of the system. The imaging system comprises an imaging lens arrangement, a light detector unit at a certain distance from the imaging lens arrangement, and a control unit connectable to the output of the detection unit. The imaging lens arrangement comprises an imaging lens and an optical element located in the vicinity of the lens aperture, said optical element introducing aperture coding by an array of regions differently affecting a phase of light incident thereon which are randomly distributed within the lens aperture, thereby generating an axially-dependent randomized phase distribution in the Optical Transfer Function (OTF) of the imaging system resulting in an extended depth of focus of the imaging system. The control unit is configured to decode the sampled output of the detection unit by using the random aperture coding to thereby extract 3D information of the objects in the field of view of the light detector unit.Type: GrantFiled: January 11, 2010Date of Patent: October 18, 2011Assignee: Xceed Imaging Ltd.Inventors: Zeev Zalevsky, Alex Zlotnik
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Patent number: 8030192Abstract: A process for manufacturing a MOS device and the MOS device manufactured thereby are disclosed. The process includes in a semiconductor layer forming a gate structure above the semiconductor layer; forming a first doped region within a first surface portion of the semiconductor layer; and irradiating the first doped region with electromagnetic radiation, to carry out annealing thereof. Prior to the irradiating step, a dielectric mirror is formed above a second surface portion of the semiconductor layer. The dielectric mirror, which may be of the Bragg-reflector type, reflects at least in part the electromagnetic radiation, and protects underlying regions from the electromagnetic radiation.Type: GrantFiled: November 22, 2006Date of Patent: October 4, 2011Assignees: STMicroelectronics S.R.L., Consiglio Nazionale Delle RicercheInventors: Dario Salinas, Guglielmo Fortunato, Angelo Magri′, Luigi Mariucci, Massimo Cuscuna′, Cateno Marco Camalleri
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Patent number: 8017528Abstract: A thermal cycle includes: increasing a temperature from an initial temperature to a temperature T1 at an arbitrary rate R1 (° C./sec); holding the temperature at the temperature T1 for an arbitrary period t1 (sec); increasing the temperature from the temperature T1 to a temperature T2 at a rate R2 (° C./sec) of 1.0×107 (° C./sec) or less; and holding the temperature at the temperature T2 for a period t2 (sec) of 50 msec or less. The thermal cycle thereafter includes: decreasing the temperature from the temperature T2 to the temperature T1 at a rate R1? (° C./sec) of 1.0×107 (° C./sec) or less; holding the temperature T1 for an arbitrary period t3 (sec); and decreasing the temperature from the temperature T1 to a final temperature at an arbitrary rate R2? (° C./sec). Such a thermal cycle is successively repeated in a plurality of iterations.Type: GrantFiled: January 13, 2009Date of Patent: September 13, 2011Assignee: Panasonic CorporationInventors: Kenji Yoneda, Kazuma Takahashi
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Patent number: 7994031Abstract: A method of manufacturing a semiconductor device is further described, comprising the steps of providing a supply of dopant atoms or molecules into an ionization chamber, combining the dopant atoms or molecules into clusters containing a plurality of dopant atoms, ionizing the dopant clusters into dopant cluster ions, extracting and accelerating the dopant cluster ions with an electric field, selecting the desired cluster ion by mass analysis, modifying the final implant energy of the cluster ion through post-analysis ion optics, and implanting the dopant cluster ions into a semiconductor substrate. In general, dopant clusters contain n dopant atoms where n can be 2, 3, 4 or any integer number. This method provides the advantages of increasing the dopant dose rate to n times the implantation current with an equivalent per dopant atom energy of 1/n times the cluster implantation energy.Type: GrantFiled: December 29, 2006Date of Patent: August 9, 2011Assignee: Semequip, Inc.Inventors: Thomas Neil Horsky, Dale Conrad Jacobson, Wade Allen Krull
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Patent number: 7989333Abstract: Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.Type: GrantFiled: May 19, 2009Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwa Park, Jong-Min Baek, Gil-Heyun Choi, Hee-Sook Park
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Patent number: 7981816Abstract: An impurity-activating thermal process is performed after a target is subjected to an impurity introduction step. In this thermal process, while a spike RTA process including a holding period for holding a temperature at a predetermined temperature is performed, at least one iteration of millisecond annealing at a temperature higher than the predetermined temperature is performed during the holding period of the spike RTA process.Type: GrantFiled: January 30, 2009Date of Patent: July 19, 2011Assignee: Panasonic CorporationInventors: Kazuma Takahashi, Kenji Yoneda
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Patent number: 7955938Abstract: An apparatus for supplying electrical power to a movable member. The apparatus includes a fixed member, the movable member moving relative to the fixed member, a flexible wiring member having an end connected to the movable member and another end connected to the fixed member, configured to transmit the electrical power from the fixed member to the movable member, and a cooling member configured to cool the fixed member.Type: GrantFiled: October 2, 2007Date of Patent: June 7, 2011Assignee: Canon Kabushiki KaishaInventor: Takao Ukaji
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Publication number: 20110127638Abstract: Improved complementary doping methods are described herein. The complementary doping methods generally involve inducing a first and second chemical reaction in at least a first and second portion, respectively, of a dopant source, which has been disposed on a thin film of a semiconductor or semimetal material. The chemical reactions result in the introduction of an n-type dopant, a p-type dopant, or both from the dopant source to each of the first and second portions of the thin film of the semiconductor or semimetal. Ultimately, the methods produce at least one n-type and at least one p-type region in the thin film of the semiconductor or semimetal.Type: ApplicationFiled: November 30, 2010Publication date: June 2, 2011Applicant: Georgia Tech Research CorporationInventors: Kevin Andrew Brenner, Raghunath Murali
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Patent number: 7947584Abstract: The present invention generally relates to a thermal processing apparatus and method that permits a user to index one or more preselected light sources capable of emitting one or more wavelengths to a collimator. Multiple light sources may permit a single apparatus to have the capability of emitting multiple, preselected wavelengths. The multiple light sources permit the user to utilize multiple wavelengths simultaneously to approximate “white light”. One or more of a frequency, intensity, and time of exposure may be selected for the wavelength to be emitted. Thus, the capabilities of the apparatus and method are flexible to meet the needs of the user.Type: GrantFiled: June 19, 2008Date of Patent: May 24, 2011Assignee: Applied Materials, Inc.Inventor: Stephen Moffatt
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Patent number: 7935946Abstract: Using a beam current of an ion beam, a dose amount to a substrate, and a reference scan speed, a scan number of the substrate is calculated as an integer value in which digits after a decimal point are truncated. If the scan number is smaller than 2, the process is aborted. If the scan number is equal to or larger than 2, it is determined whether the scan number is even or odd. If the scan number is even, the current scan number is set as a practical scan number. If the scan number is odd, an even scan number which is smaller by 1 than the odd scan number is obtained, and the obtained even scan number is set as a practical scan number. A practical scan speed of the substrate is calculated by using the practical scan number, the beam current, and the dose amount.Type: GrantFiled: February 11, 2009Date of Patent: May 3, 2011Assignee: Nissin Ion Equipment Co., Ltd.Inventor: Masayoshi Hino
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Patent number: 7935945Abstract: Using a beam current of an ion beam, and a dose amount to a substrate, and an initial value of a scan number of the substrate set to 1, a scan speed of the substrate is calculated. If the scan speed is within the range, the current scan number and the current scan speed are set as a practical scan number and a practical scan speed, respectively. If the scan speed is higher than the upper limit of the range, the calculation process is aborted. If the scan speed is lower than the lower limit of the range, the scan number is incremented by one to calculate a corrected scan number. A corrected scan speed is calculated by using the corrected scan number, etc. The above steps are repeated until the corrected scan speed is within the allowable scan speed range.Type: GrantFiled: February 11, 2009Date of Patent: May 3, 2011Assignee: Nissin Ion Equipment Co., Ltd.Inventor: Masayoshi Hino
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Patent number: 7915153Abstract: A passivation film and a method of forming the same are provided, the passivation film being used in a plasma display panel etc. In the passivation film, a first MgO layer, an intervening layer, and a second MgO layer are laminated and a laser is then irradiated to oxidize the intervening layer. Simultaneously, defects are formed at the interfaces of the first and second MgO layers. Accordingly, a plasma discharge firing voltage greatly decreases, and the total power consumption of the plasma display panel is significantly reduced.Type: GrantFiled: December 2, 2008Date of Patent: March 29, 2011Assignee: LG Electronics Inc.Inventors: Jong Lam Lee, Hak Ki Yu
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Patent number: 7906405Abstract: Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.Type: GrantFiled: March 13, 2008Date of Patent: March 15, 2011Assignee: Texas Instruments IncorporatedInventors: Joe W. McPherson, Ajit Shanware
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Publication number: 20110045244Abstract: Methods and apparatus for processing a substrate (e.g., a semiconductor substrate) is disclosed that includes irradiating at least a portion of the substrate surface with a plurality of short radiation pulses while the surface portion is exposed to a dopant compound. The pulses are selected to have a fluence at the substrate surface that is greater than a melting fluence threshold (a minimum fluence needed for the radiation pulse to cause substrate melting) and less than an ablation fluence threshold (a minimum fluence needed for the radiation pulse to cause substrate ablation). In this manner a quantity of the dopant can be incorporated into the substrate while ensuring that the roughness of the substrate's surface is significantly less than the wavelength of the plied radiation pulses.Type: ApplicationFiled: February 2, 2009Publication date: February 24, 2011Inventors: Eric Mazur, Mark Winkler
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Patent number: 7888251Abstract: Apparatus and method are provided for hydrogenating semiconductor or other materials by ultraviolet (UV) radiation in the presence of hydrogen. Hydrogen uptake may be optimized by selection of temperature and wavelength of the UV radiation. Patterned areas may be selectively hydrogenated, such as mesas in Avalanche Photodiode Arrays.Type: GrantFiled: April 19, 2007Date of Patent: February 15, 2011Assignee: Amethyst Research, Inc.Inventors: Terry D. Golding, Ronald Paul Hellmer
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Patent number: 7867868Abstract: The present invention generally provides an absorber layer using carbon based materials with increased and stabled thermal absorption coefficient and economical methods to produce such an absorber layer. One embodiment of the present invention provides a method for processing a substrate comprising depositing an absorber layer on a top surface of the substrate, wherein the substrate is maintained under a first temperature, annealing the substrate in a thermal processing chamber, wherein the substrate is heated to a second temperature, and the second temperature is higher than the first temperature, and removing the absorber layer from the substrate.Type: GrantFiled: March 2, 2007Date of Patent: January 11, 2011Assignee: Applied Materials, Inc.Inventors: Joseph M. Ranish, Bruce E. Adams
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Patent number: 7851318Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.Type: GrantFiled: October 16, 2008Date of Patent: December 14, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaki Koyama, Fumito Isaka, Akihisa Shimomura, Junpei Momo
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Patent number: 7846804Abstract: A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.Type: GrantFiled: June 5, 2007Date of Patent: December 7, 2010Assignee: United Microelectronics Corp.Inventors: Hsiu-Lien Liao, Neng-Kuo Chen, Teng-Chun Tsai, Yi-Wei Chen
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Patent number: 7846803Abstract: A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time.Type: GrantFiled: May 31, 2007Date of Patent: December 7, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Gregory S. Spencer, Vishal P. Trivedi
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BACK CONTACT SOLAR CELLS WITH EFFECTIVE AND EFFICIENT DESIGNS AND CORRESPONDING PATTERNING PROCESSES
Publication number: 20100294349Abstract: Laser based processes are used alone or in combination to effectively process doped domains for semiconductors and/or current harvesting structures. For example, dopants can be driven into a silicon/germanium semiconductor layer from a bare silicon/germanium surface using a laser beam. Deep contacts have been found to be effective for producing efficient solar cells. Dielectric layers can be effectively patterned to provide for selected contact between the current collectors and the doped domains along the semiconductor surface. Rapid processing approaches are suitable for efficient production processes.Type: ApplicationFiled: May 20, 2009Publication date: November 25, 2010Inventors: Uma Srinivasan, Xin Zhou, Henry Hieslmair, Neeraj Pakala -
Patent number: 7838402Abstract: A method of manufacturing an electronic apparatus having a resist pattern provided over a substrate provided with a thin film transistor, the method includes the steps of forming by application a resist film over the substrate in the state of covering the thin film transistor, forming a resist pattern by subjecting the resist film to exposure to light and a developing treatment, and irradiating the resist pattern with at least one of ultraviolet light and visible light in a dry atmosphere in the condition where a channel part of the thin film transistor is prevented from being irradiated with light having a wavelength of shorter than 260 nm, wherein a step of heat curing the resist pattern is conducted after the irradiation with at least one of ultraviolet light and visible light.Type: GrantFiled: November 21, 2008Date of Patent: November 23, 2010Assignee: Sony CorporationInventors: Koichi Nagasawa, Takashi Yamaguchi, Nobutaka Ozaki, Yasuhiro Kanaya, Hirohisa Takeda, Yasuo Mikami, Yoshifumi Mutoh
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Patent number: 7829446Abstract: A method for dividing a wafer into a plurality of chips is provided. The method includes providing recesses in a surface of the wafer at positions along boundaries between regions to become the individual chips, providing fragile portions having a predetermined width inside the wafer at positions along the boundaries by irradiation of the other surface of the wafer with a laser beam whose condensing point is placed inside the wafer, the fragile portions including connected portions at least at one of the surfaces of the wafer, and dividing the wafer at the fragile portions into the individual chips by applying an external force to the wafer.Type: GrantFiled: November 8, 2007Date of Patent: November 9, 2010Assignee: Seiko Epson CorporationInventors: Wataru Takahashi, Yoshinao Miyata, Kazushige Umetsu, Yutaka Yamazaki
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Publication number: 20100264423Abstract: A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness; laser processing the back side of the thinned substrate to form at least one lasered feature on the back side; and dicing the substrate into a plurality of components having the lasered feature. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate. A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate.Type: ApplicationFiled: April 16, 2009Publication date: October 21, 2010Inventors: Alan G. Wood, Tim Corbett
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Patent number: 7811914Abstract: An apparatus and method is disclosed for increasing the thermal conductivity in a substrate of a non-wide bandgap material comprising the steps of directing a thermal energy beam onto the substrate in the presence of a first doping gas for converting a region of the substrate into a wide bandgap material to enhance the thermal conductivity of the substrate for cooling the non-wide bandgap material. In one example, the invention is incorporated into a carbon rich layer formed within the wide bandgap material. In another example, the invention is incorporated into a carbon rich layer formed within the wide bandgap material having basal planes disposed to extend generally outwardly relative to an external surface of the substrate to enhance the cooling of the substrate.Type: GrantFiled: April 20, 2006Date of Patent: October 12, 2010Inventors: Nathaniel R. Quick, Aravinda Kar
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Publication number: 20100240203Abstract: In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns.Type: ApplicationFiled: May 10, 2010Publication date: September 23, 2010Inventors: James E. Carey, III, Eric Mazur
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Patent number: 7799666Abstract: A method utilizing spatially selective laser doping for irradiating predetermined portions of a substrate of a semiconductor material is disclosed. Dopants are deposited onto the surface of a substrate. A pulsed, visible beam is directed to and preferentially absorbed by the substrate only in those regions requiring doping. Spatial modes of the incoherent beam are overlapped and averaged, providing uniform irradiation requiring fewer laser shots. The beam is then focused to the predetermined locations of the substrate for implantation or activation of the dopants. The method provides for scanning and focusing of the beam across the substrate surface, and irradiation of multiple locations using a plurality of beams. The spatial selectivity, combined with visible laser wavelengths, provides greater efficiency in doping only desired substrate regions, while reducing the amount of irradiation required.Type: GrantFiled: July 27, 2009Date of Patent: September 21, 2010Assignee: Potomac Photonics, Inc.Inventors: Nicholas A. Doudoumopoulos, C. Paul Christensen, Paul Wickboldt
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Patent number: 7745297Abstract: The substrate with electrodes is formed of a transparent material onto which is deposited a film (1) of a transparent conductive material of thickness e1 and of refractive index n1, said film being structured to form a set of electrodes (1a) whose contours (8) delimit insulating spaces (3), wherein the insulating spaces (3) are filled with a transparent dielectric material of thickness e2 and of refractive index n2 so that the respective thicknesses of the conductive material and the dielectric material are inversely proportional to the values of the refractive indices of said materials and said dielectric material forms neither depressions nor beads at the contour (8) of the electrodes. A hardcoating layer (7) may be disposed between the substrate (5) and the electrodes and a protective film (9) added. The substrate with electrodes is obtained by UV irradiation through a single mask.Type: GrantFiled: January 24, 2008Date of Patent: June 29, 2010Assignee: Asulab S.A.Inventors: Joachim Grupp, Gian-Carlo Poli, Pierre-Yves Baroni, Estelle Wagner, Patrik Hoffmann
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Publication number: 20100144079Abstract: The invention relates to a method for the precision processing of substrates, in particular for the microstructuring of thin layers, local dopant introduction and also local application of a metal nucleation layer in which a liquid-assisted laser, i.e. laser irradiation of a substrate which is covered in the regions to be processed by a suitable reactive liquid, is implemented.Type: ApplicationFiled: March 6, 2008Publication date: June 10, 2010Applicants: Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung e.V., ALBERT-LUDWIGS-UNIVERSITÄT FREIBURGInventors: Kuno Mayer, Monica Aleman, Daniel Kray, Stefan Glunz, Ansgar Mette, Ralf Preu, Andreas Grohe
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Patent number: 7732311Abstract: In a method of manufacturing a semiconductor device, a conductive layer pattern may be formed on a substrate. An oxide layer may be formed on the substrate to cover the conductive layer pattern. A diffusion barrier layer may be formed by treating the oxide layer to increase an energy required for a diffusion of impurities. An impurity region may be formed on the substrate by implanting impurities into the conductive layer pattern and a portion of the substrate adjacent to the conductive layer pattern, through the diffusion barrier. The impurities in the conductive layer pattern and the impurity region may be prevented or reduced from diffusing, and therefore, the semiconductor device may have improved performance.Type: GrantFiled: June 20, 2008Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Suk Shin, Joo-Won Lee, Tae-Gyun Kim
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Publication number: 20100090347Abstract: The present disclosure is directed to the preparation of a semiconductor substrate, and metallization of a contact area on the substrate to produce a contact in a semiconductor device. The method includes pre-treating the substrate by ultra fast laser treatment of a contact area, and depositing an interconnect metal layer on the contact area to create a contact. The process may include depositing a layer of dielectric-forming material on the substrate and removing a portion of the dielectric material from the substrate to reveal a contact area, prior to laser treating and metallization.Type: ApplicationFiled: October 9, 2008Publication date: April 15, 2010Inventors: Stephen D. Saylor, Susan Alie
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Publication number: 20100093164Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: ApplicationFiled: October 8, 2009Publication date: April 15, 2010Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventors: Haruo NAKAZAWA, Kazuo SHIMOYAMA, Manabu TAKEI
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Publication number: 20100087053Abstract: A method for fabricating a semiconductor body is presented. The semiconductor body includes a p-conducting zone, an n-conducting zone and a pn junction in a depth T1 in the semiconductor body between the p-conducting zone and the n-conducting zone. The method includes providing the semiconductor body, producing the p-doped zone by the diffusion of an impurity that forms an acceptor in a first direction into the semiconductor body, and producing the n-conducting zone by the implantation of protons in the first direction into the semiconductor body into a depth T2>T1 and the subsequent heat treatment of the semiconductor body in order to form hydrogen-induced donors.Type: ApplicationFiled: September 30, 2009Publication date: April 8, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Frank Hille, Franz Josef Niedernostheide, Hans-Joachim Schulze, Holger Schulze
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Publication number: 20100055887Abstract: A method of semiconductor junction formation in Laser diffusion process for fabrication of solar cells provides for delivery of inert gases in the vicinity of the Si wafer while dopant species are being diffused form a dopant source into the surface of the wafer irradiated by a laser beam. The laser beam is emitted by CW- or pulsed operated lasers including fiber lasers. Optionally, the passivation of the surface and formation of the antireflection coating are performed simultaneously with the diffusion of the dopant species.Type: ApplicationFiled: September 2, 2009Publication date: March 4, 2010Inventor: Bernhard P. Piwczyk
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Patent number: 7666772Abstract: A heat treatment apparatus which enables a heating process for a short time with high reproducibility in a manufacturing process of a MOS transistor manufactured using a semiconductor substrate, and a method of manufacturing a semiconductor device using the heat treatment apparatus are provided. The heat treatment apparatus of the present invention which enables the above heat treatment method is characterized by comprising: a light source; a power supply for turning the light source on and off in a pulse shape; a processing chamber in which the substrate can be irradiated with light from the light source; and a unit for supplying a coolant to the processing chamber and also increasing and decreasing the supply amount.Type: GrantFiled: January 11, 2007Date of Patent: February 23, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koji Dairiki, Shunpei Yamazaki
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Publication number: 20100025694Abstract: A method is disclosed for forming a layer of a wide bandgap material in a non-wide bandgap material. The method comprises providing a substrate of a non-wide bandgap material and converting a layer of the non-wide bandgap material into a layer of a wide bandgap material. An improved component such as wide bandgap semiconductor device may be formed within the wide bandgap material through a further conversion process.Type: ApplicationFiled: October 6, 2009Publication date: February 4, 2010Inventor: Nathaniel R. Quick
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Patent number: 7646549Abstract: An imaging system is presented for imaging objects within a field of view of the system. The imaging system comprises an imaging lens arrangement, a light detector unit at a certain distance from the imaging lens arrangement, and a control unit connectable to the output of the detection unit. The imaging lens arrangement comprises an imaging lens and an optical element located in the vicinity of the lens aperture, said optical element introducing aperture coding by an array of regions differently affecting a phase of light incident thereon which are randomly distributed within the lens aperture, thereby generating an axially-dependent randomized phase distribution in the Optical Transfer Function (OTF) of the imaging system resulting in an extended depth of focus of the imaging system. The control unit is configured to decode the sampled output of the detection unit by using the random aperture coding to thereby extract 3D information of the objects in the field of view of the light detector unit.Type: GrantFiled: December 18, 2007Date of Patent: January 12, 2010Assignee: Xceed Imaging LtdInventors: Zeev Zalevsky, Alex Zlotnik
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Patent number: 7629275Abstract: A method of forming an integrated circuit is provided. The method includes performing a multiple-time flash anneal process to a wafer, wherein the multiple-time flash anneal process comprises preheating the wafer to a first preheat temperature; performing a first flash on the wafer with a first flash energy; preheating the wafer to a second preheat temperature; and performing a second flash on the wafer with a second flash energy.Type: GrantFiled: January 25, 2007Date of Patent: December 8, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jennifer Chen, Chi-Chun Chen, Hun-Jan Tao
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Publication number: 20090283143Abstract: A semiconductor component comprises a semiconductor substrate comprising a front surface, a back surface which is opposite thereto, and a surface normal which is perpendicular to the front and back surfaces, a first contact structure which is electrically conductive and is electrically connected to the front surface of the semiconductor substrate via at least one point-shaped front contact, and a second contact structure which is electrically conductive and is electrically connected to the back surface of the semiconductor substrate.Type: ApplicationFiled: May 13, 2009Publication date: November 19, 2009Inventors: Andreas Krause, Bernd Bitnar, Holger Neuhaus, Frederick Bamberg
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Patent number: 7605064Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated.Type: GrantFiled: May 22, 2006Date of Patent: October 20, 2009Assignee: Agere Systems Inc.Inventors: Isik C. Kizilyalli, Joseph Rudolph Radosevich, Pradip Kumar Roy
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Patent number: 7582541Abstract: A wafer laser processing method for forming a groove along streets in a wafer by moving the wafer at a predetermined feed rate while a laser beam whose focal spot is elliptic is applied along the streets formed on the wafer, comprising: a groove forming step for forming a groove along the streets by applying a first laser beam whose elliptic focal spot has a ratio of the long axis to the short axis of 30 to 60:1, along the streets formed on the wafer; and a debris removing step for removing debris accumulated in the groove by applying a second laser beam whose elliptic focal spot has a ratio of the long axis to the short axis of 1 to 20:1, along the groove formed by the groove forming step; the groove forming step and the debris removing step being repeated alternately.Type: GrantFiled: May 4, 2007Date of Patent: September 1, 2009Assignee: Disco CorporationInventors: Noboru Takeda, Yukio Morishige
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Patent number: 7569458Abstract: A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10-25 ?m and more particularly 15-18 ?m, or a frequency ranging from 12-30 THz and more particularly 16.5-20 THz.Type: GrantFiled: February 12, 2007Date of Patent: August 4, 2009Assignee: Atmel CorporationInventors: Bohumil Lojek, Michael D. Whiteman
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Patent number: 7547619Abstract: A method of introducing an impurity and an apparatus for introducing the impurity forms an impurity layer easily in a shallower profile. Component devices manufactured taking advantage of these method or apparatus are also disclosed. When introducing a material to a solid substance which has an oxidized film or other film sticking at the surface, the present method and apparatus first removes the oxidized film and other film using at least one means selected from among the group consisting of a means for irradiating the surface of solid substance with plasma, a means for irradiating the surface of solid substance with gas and a means for dipping the surface of solid substance in a reductive liquid; and then, attaches or introduces a certain desired particle. The way of attaching, or introducing, a particle is bringing a particle-containing gas to make contact to the surface, which surface has been made to be free of the oxidized film and other film.Type: GrantFiled: September 19, 2003Date of Patent: June 16, 2009Assignee: Panasonic CorporationInventors: Yuichiro Sasaki, Bunji Mizuno, Ichiro Nakayama
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Patent number: 7485554Abstract: A method of selectively heating a predetermined region of a semiconductor substrate includes providing a semiconductor substrate, selectively focusing a free carrier generation light on only a predetermined region of the semiconductor substrate, irradiating the free carrier generation light on the predetermined region of the semiconductor substrate to increase a free carrier concentration within the predetermined region of the semiconductor substrate, wherein the free carrier generation light causes the predetermined region to increase in temperature by less than a temperature necessary to change the solid phase of the predetermined region, and irradiating the semiconductor substrate with a heating light to selectively heat the predetermined region of the semiconductor substrate.Type: GrantFiled: January 22, 2007Date of Patent: February 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Gyoung Ho Buh, Ji-Sang Yahng, Yu Gyun Shin, Guk-Hyon Yon, Sangjin Hyun
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Patent number: 7465921Abstract: An apparatus for producing analyte ions for detection by a mass spectrometer is described. The apparatus includes an ion source in which the surface of a target substrate for holding an analyte sample includes structured carbon nanotube material. The structured carbon nanotube material is structured in terms of being situated on a selected portion of the target support surface an/or in terms of being aligned in a selected orientation.Type: GrantFiled: March 2, 2006Date of Patent: December 16, 2008Assignee: Agilent Technologies, Inc.Inventors: Timothy H. Joyce, Dan-Hul Dorothy Young, Jennifer Lu