By Application Of Corpuscular Or Electromagnetic Radiation (e.g., Electron, Laser, Etc.) Patents (Class 438/535)
  • Publication number: 20040038503
    Abstract: A method of disordering a quantum well heterostructure, including the step of irradiating the heterostructure with a particle beam, wherein the energy of the beam is such that the beam creates a substantially constant distribution of defects within the heterostructure. The irradiating particles can be ions or electrons, and the energy is preferably such that the irradiating particles pass through the heterostructure. Light ions such as hydrogen ions are preferred because they are readily available and produce substantially uniform distributions of point defects at relatively low energies. The method can be used to tune the wavelength range of an optoelectronic device including such a heterostructure, such as a photodetector.
    Type: Application
    Filed: September 8, 2003
    Publication date: February 26, 2004
    Inventors: Lan Fu, Hark Toe Tan, Chennupati Jagadish
  • Publication number: 20040033679
    Abstract: A technique for forming nanostructures including a definition of a charge pattern on a substrate and introduction of charged molecular scale sized building blocks (MSSBBs) to a region proximate the charge pattern so that the MSSBBs adhere to the charge pattern to form the feature.
    Type: Application
    Filed: May 23, 2003
    Publication date: February 19, 2004
    Applicant: Massachusetts Institute of Technology
    Inventors: Joseph M. Jacobson, David Kong, Vikas Anant, Ashley Salomon, Saul Griffith, Will DelHagen, Vikrant Agnihotri
  • Publication number: 20040014261
    Abstract: Prior to converting a non-single crystal material of a semiconductor film into a single crystal material through the use of a laser beam, at least one dopant is introduced into whole of the semiconductor film. Then, the non-single crystal semiconductor film is irradiated with a laser beam to crystallize the semiconductor film. In this case, a ratio between quasi-fermi level of the single crystal material within one of transistor formation regions used to form transistors of different conductivity types and quasi-fermi level of the single crystal material within the other thereof is made to be between 0.5:1 and 2.0:1. Thus, transistors of different conductivity types are formed in the crystallized semiconductor film.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 22, 2004
    Applicant: NEC LCD Technologies, Ltd.
    Inventor: Mitsuasa Takahashi
  • Patent number: 6645837
    Abstract: A polycrystalline silicon layer is formed on a substrate. An insulating layer and a gate electrode are formed on the polycrystalline silicon layer. Then, a channel region, a source region and a drain region are formed in a self-aligned manner by doping an impurity in the polycrystalline silicon layer using the gate electrode as a mask. Then, an energy absorption layer is formed so as to cover the entire substrate and a pulsed laser beam is irradiated from the energy absorption layer side. The energy of the pulsed laser beam is almost completely absorbed in the energy absorption layer and a heat treatment is indirectly performed on the underlying layers by radiating the heat. In other words, activation of the impurity and removal of defects in the insulating layer are performed at the same time without damaging the substrate by the heat.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: November 11, 2003
    Assignee: Sony Corporation
    Inventors: Dharam Pal Gosain, Kazumasa Nomoto, Akio Machida, Miyako Nakagoe, Setsuo Usui
  • Patent number: 6645838
    Abstract: A process for activating a doped region (80) or amorphized doped region (34) in a semiconductor substrate (10). The process includes the steps of doping a region of the semiconductor substrate, wherein the region is crystalline or previously amorphized. The next step is forming a conformal layer (40) atop the upper surface (11) of the substrate. The next step is performing at least one of front-side and backside irradiation of the substrate to activate the doped region. The activation may be achieved by heating the doped region to just below the melting point of the doped region, or by melting the doped region but not the crystalline substrate. An alternative process includes the additional step of forming the doped region (amorphized or unamorphized) within or adjacent a deep dopant region (60) and providing sufficient heat to the deep dopant region through at least one of front-side and backside irradiation so that the doped region is activated through explosive recrystallization.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: November 11, 2003
    Assignee: Ultratech Stepper, Inc.
    Inventors: Somit Talwar, Yun Wang, Michael O. Thompson
  • Patent number: 6639229
    Abstract: A method of aluminum ion generation for an implantation in a semiconductor wafer, including using nitrogen trifluoride as a gas for ionizing a solid alumina element.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: October 28, 2003
    Assignee: STMicroelectronics, S.A.
    Inventor: Hamou Chakor
  • Patent number: 6632729
    Abstract: A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a surface; (b) forming a gate oxide layer on at least a portion of the surface and including an interface therewith, the gate oxide layer comprising a high-k dielectric oxide including a plurality of interface traps at the interface; (c) forming a gate electrode layer on at least a portion of the gate oxide layer; and (d) laser thermal annealing the high-k gate oxide layer to de-activate the interface traps without incurring formation of a low-k dielectric oxide layer at the interface.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: October 14, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Eric N. Paton
  • Publication number: 20030181026
    Abstract: Accelerators and implanters of nowadays are simply wasting too much energy on excitation of lattice electrons, rather than using energy on the desired nuclear scatterings. This current invention suppresses the undesired electronic stopping loss via causing effective neutralizing screening of the particles during their penetration through the target, using parallel speedy conduction electrons induced by assistant radiations. The assistant radiation beam of this invention can take the form of energetic electrons, X ray or &ggr; ray, for example. One great advantage of the present invention is to further expand the application domains of existing accelerators and implanters, using readily available, relatively cheap and easy-to-implement radiation sources. The then saved particle energy will be redirected to reaching more depth or to rendering more defects within the target as desired. This invention is expected to bring great impacts on various application domains.
    Type: Application
    Filed: June 18, 2002
    Publication date: September 25, 2003
    Inventors: Chungpin Liao, Tsing-Tyan Yang
  • Patent number: 6624442
    Abstract: The present invention discloses a method of forming a p-n junction on a ZnO thin film and a p-n junction thin film. The object of the present invention is to provide a method of forming a p-n junction on a ZnO thin film and a p-n junction thin film which deposits Zn3P2 on a ZnO thin film and forms a p-type material constituting a device by using thermal diffusion for the Zn3P2 in order to fabricate an effective p-type material. The method of forming a p-n junction on a ZnO thin film, in a light emitting device having a sapphire substrate as a base substrate, comprises the steps of: cladding the sapphire substrate with a n-type ZnO thin film; depositing a Zn3P2 thin film on the n-type ZnO thin film; forming a p-type ZnO thin film by irradiating a laser on the upper surface of the Zn3P2 thin film, decomposing the Zn3P2 thin film and diffusing the same on the n-type ZnO thin film; and forming an electrode on the n-type ZnO thin film and the p-type ZnO thin film respectively.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: September 23, 2003
    Inventors: Young-Chang Kim, Sang-Yeol Lee
  • Patent number: 6586318
    Abstract: An improved method and system for laser doping a semiconductor material is described. In the invention, phosphorous nitride is used as a dopant source. The phosphorous nitride is brought into close proximity with a region of the semiconductor to be doped. A pulse of laser light decomposes the phosphorous nitride and briefly melts the region of semiconductor to be doped to allow incorporation of dopant atoms from the phosphorous nitride into the semiconductor.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: July 1, 2003
    Assignee: Xerox Corporation
    Inventors: Jeng Ping Lu, Ping Mei, James B. Boyce
  • Publication number: 20030119287
    Abstract: A laser-irradiation method which comprises a process for fabricating a semiconductor device, comprising:
    Type: Application
    Filed: December 10, 2002
    Publication date: June 26, 2003
    Applicant: Semiconductor Energy Laboratory Co. Ltd., a Japan corporation
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Naoto Kusumoto, Takeshi Fukunaga, Setsuo Nakajima, Tadayoshi Miyamoto, Atsushi Yoshinouchi
  • Patent number: 6562705
    Abstract: A laser heating apparatus for forming an electrode on one surface of an Si chip provided on an Si wafer, thereby producing a semiconductor element, comprises a high vacuum chamber having a light transmission window, an XY table contained in the high vacuum chamber for mounting the Si wafer thereon, heater contained in the high vacuum chamber for heating and evaporating an impurity in a solid state, and laser beam applying means for applying a laser beam to the Si chip placed on the XY table from the outside of the high vacuum chamber through the light transmission window, thereby implanting the impurity into the Si in chip and activating the implanted impurity.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: May 13, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Obara, Hideki Nozaki, Motoshige Kobayashi
  • Patent number: 6555423
    Abstract: In manufacturing a thin-film transistor the condition of a polysilicon film is evaluated, a manufacture margin for the film is determined from the condition evaluated, and the power of an excimer laser annealing apparatus is set based on the manufacture margin. The annealing apparatus anneals an amorphous silicon film, converting the same to a polysilicon film. The surface spatial structure of the polysilicon film thus formed exhibits linearity or periodicity, or both, depending on the energy applied to the amorphous silicon film during the annealing. The image data of the polysilicon film is processed, thereby determining the linearity and/or periodicity in numerical values, by utilizing the auto-correlation function of the surface image of the polysilicon film.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: April 29, 2003
    Assignee: Sony Corporation
    Inventors: Hiroyuki Wada, Makoto Takatoku
  • Publication number: 20030077886
    Abstract: A lower concentration impurity diffusion region can be formed under excellent control, even when a low heat-resistant substrate is used. At the time of doping a semiconductor layer, a mask such as sidewalls (24) where an energy beam passes through, is formed on a part of a surface of a semiconductor layer (21), dopant ions (25) are adsorbed on the surface of the semiconductor layer (21) except a region in which the mask is formed, and an energy beam EBL is irradiated onto the semiconductor layer (21) having the formed mask to introduce the dopant ions into the semiconductor layer (21). In the lower part of the mask such sidewalls (24), diffusion in transverse direction occurs and lower concentration impurity diffusion regions can be formed in excellent reproducibility under excellent control.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 24, 2003
    Inventors: Akio Machida, Setsuo Usui, Dharam Pal Gosain
  • Patent number: 6551903
    Abstract: A thin film photovoltaic devices is described, having a glass substrate 11 over which is formed a thin film silicon device having an n++ layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a connection through the p layer 13 to the underlying n++ layer 12, a column of semi-conductor material is heated, the column passing through the various doped layers and the material in the column being heated or melted to allow migration of dopant between layer of the device in the region of the column.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: April 22, 2003
    Assignee: Pacific Solar Pty. Limited
    Inventors: Zhengrong Shi, Paul Alan Basore, Stuart Ross Wenham, Guangchun Zhang, Shijun Cai
  • Patent number: 6551888
    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, introducing dopants into the substrate, forming a tuning layer over at least a portion of the substrate, and activating the dopants using laser thermal annealing. The tuning layer causes an increase or a decrease in the amount of fluence absorbed by the portion of substrate below the tuning layer in comparison to an amount of fluence absorbed by a portion of substrate not covered by the tuning layer. Additional tuning layers can also be formed over the substrate.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: April 22, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Cyrus E. Tabery, Eric N. Paton, Bin Yu, Qi Xiang, Robert B. Ogle
  • Patent number: 6544868
    Abstract: The present invention provides a method of manufacturing a low resistivity p-type compound semiconductor material over a substrate. The method of the present invention comprises the steps of forming a p-type impurity doped compound semiconductor layer on the substrate by either HVPE, OMVPE or MBE and applying a microwave treatment over the p-type impurity doped compound semiconductor layer for a period of time. The high resistivity p-type impurity doped compound semiconductor layer is converted into a low resistivity p-type compound semiconductor material according to the present invention.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: April 8, 2003
    Assignee: United Epitaxy Company, Ltd.
    Inventors: Tzong-Liang Tsai, Chung-Ying Chang
  • Patent number: 6544853
    Abstract: A process of fabricating a p-type metal oxide semiconductor to affect reduction of negative bias temperature instability (NBTI) in the formed p-type metal oxide semiconductor structure by: a) forming a gate on a gate oxide in a substrate; b) forming a spacer on a sidewall of the gate; c) forming a source/drain extension beside the gate oxide in the substrate or forming a lightly doped drain (LDD) implantation into the gate oxide; and d) implanting F2 between the gate oxide and the source drain extension at a sufficiently large tilted angle and in sufficient amount to affect reduction of negative bias temperature instability characteristics lower than without F2 implantation.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: April 8, 2003
    Assignee: Infineon Technologies AG
    Inventor: Chuan Lin
  • Publication number: 20030008481
    Abstract: An improved dopant application system and method for the manufacture of microelectronic devices accurately places dopant on and within a dielectric or semiconductor surface. Diffusing and activating p-type and n-type dopants in dielectric or semiconductor substrates is achieved by means of electron beam irradiation.
    Type: Application
    Filed: August 2, 2002
    Publication date: January 9, 2003
    Inventors: Matthew F. Ross, Charles Hannes, William R. Livesay
  • Publication number: 20030001229
    Abstract: A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal, mass outer surfaces and diffuse at least some of the projecting metal, mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices.
    Type: Application
    Filed: August 23, 2002
    Publication date: January 2, 2003
    Inventors: John T. Moore, Terry L. Gilton
  • Patent number: 6489225
    Abstract: An improved dopant application system and method for the manufacture of microelectronic devices accurately places dopant on and within a dielectric or semiconductor surface. Diffusing and activating p-type and n-type dopants in dielectric or semiconductor substrates is achieved by means of electron beam irradiation.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: December 3, 2002
    Assignee: Electron Vision Corporation
    Inventors: Matthew F. Ross, Charles Hannes, William R. Livesay
  • Patent number: 6475886
    Abstract: Disclosed is a method for forming a nano-crystal. In the above method, there is prepared a substrate having a metal film or a semiconductor film formed thereon. A focused-ion beam is irradiated onto a plurality of positions on a surface of the metal film or the semiconductor film, whereby the metal film or the semiconductor film is removed at a focal portion of the focused-ion beam but an atomic bond in the metal film or the semiconductor film is broken at an overlapping region of the focused-ion beams due to an radiation effect of the focused-ion beam to form the nano-crystal. The method allows a few nm or less-sized nano-crystals to be formed with ease and simplicity using the focused-ion beam. As a result, the formed nano-crystals come to have a binding energy capable of restraining thermal fluctuation phenomenon at room temperature and thereby it becomes possible to fabricate a tunneling transistor capable of being operated at room temperature.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: November 5, 2002
    Assignee: Korea Institute of Science and Technology
    Inventors: Eun Kyu Kim, Young Ju Park, Tae Whan Kim, Seung Oun Kang, Dong Chul Choo, Jae Hwan Shim
  • Patent number: 6475888
    Abstract: A method for forming an ultra-shallow junction using laser annealing wherein an amorphous carbon layer is used as an energy absorber layer comprises the steps of preparing a silicon substrate having isolation layers; forming a gate having a stacked structure of a gate insulating layer, a polysilicon layer and a metal layer on the silicon substrate; forming a sacrificial spacer on the sidewalls of the gate; forming source and drain regions on the silicon substrate regions at both sides of the gate including on the sacrificial spacer; removing the sacrificial spacer; doping impurities to form source/drain extension doping layers on the silicon substrate regions at both sides of the gate; depositing sequentially a reaction preventing layer and an amorphous carbon layer as a laser absorber layer on the resulting structure; forming source/drain extension doping layers on inner sides of the source and drain regions by performing laser annealing in an atmosphere of inert gas or under vacuum; and removing the amorpho
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: November 5, 2002
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong Sun Sohn
  • Patent number: 6475839
    Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film on a semiconductor layer, forming a gate electrode on the insulating film, pattering the first insulating film into a second insulating film so that a portion of the semiconductor layer is exposed while the second insulating film has extensions which extend beyond the side edges of the gate electrode, and performing ion introduction for forming impurity regions using the gate electrode and extensions of the gate insulating film as a mask. The condition of the ion introduction is varied in order to control the regions of the semiconductor layer to be added with the impurity and the concentration of the impurity therein.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: November 5, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoaki Yamaguchi, Yasuhiko Takemura
  • Publication number: 20020160592
    Abstract: A method for forming an ultra-shallow junction using laser annealing wherein an amorphous carbon layer is used as an energy absorber layer comprises the steps of preparing a silicon substrate having isolation layers; forming a gate having a stacked structure of a gate insulating layer, a polysilicon layer and a metal layer on the silicon substrate; forming a sacrificial spacer on the sidewalls of the gate; forming source and drain regions on the silicon substrate regions at both sides of the gate including on the sacrificial spacer; removing the sacrificial spacer; doping impurities to form source/drain extension doping layers on the silicon substrate regions at both sides of the gate; depositing sequentially a reaction preventing layer and an amorphous carbon layer as a laser absorber layer on the resulting structure; forming source/drain extension doping layers on inner sides of the source and drain regions by performing laser annealing in an atmosphere of inert gas or under vacuum; and removing the amorpho
    Type: Application
    Filed: December 10, 2001
    Publication date: October 31, 2002
    Inventor: Yong Sun Sohn
  • Patent number: 6451636
    Abstract: Regarding an element having a channel width W greater than a pitch P of a pulse laser beam, a direction of the channel width W of a channel region CH is inclined with respect to a direction of a major axis of a line beam LB. Consequently, even if a defective crystallization region R is caused by an nonuniform intensity of an irradiated region in laser annealing forming p-Si of a p-Si TFT LCD, the whole channel width W of the channel region CH does not overlap the defective crystallization region R. Therefore, even if the defective crystallization region R is generated, element characteristics are not affected. Thus, the manufacturing yield of an excellent p-Si LCD can be enhanced.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: September 17, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuo Segawa, Ryoichi Yokoyama, Kiyoshi Yoneda, Tsutomu Yamada
  • Patent number: 6444550
    Abstract: A semiconductor device having a retrograde channel profile is achieved by forming a retrograde impurity region in the surface portion of a semiconductor substrate, and subsequently forming a semiconductor layer on the retrograde impurity region at a predetermined thickness. The thickness of the semiconductor layer is controlled to localize the retrograde impurity region and its impurity concentration peak at a predetermined depth, thereby reducing the device's susceptibility to “reverse short channel effects.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: September 3, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ming-Yin Hao, Emi Ishida
  • Patent number: 6429102
    Abstract: The present invention provides a method of manufacturing a low resistivity p-type compound semiconductor material over a substrate. The method of the present invention comprises the steps of forming a p-type impurity doped compound semiconductor layer on the substrate by either HVPE, OMVPE or MBE and applying a microwave treatment over the p-type impurity doped compound semiconductor layer for a period of time. The high resistivity p-type impurity doped compound semiconductor layer is converted into a low resistivity p-type compound semiconductor material according to the present invention.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: August 6, 2002
    Assignee: United Epitaxy Company, Ltd.
    Inventors: Tzong-Liang Tsai, Chung-Ying Chang
  • Patent number: 6395624
    Abstract: The present invention provides a novel method of forming implants with Projection Gas-Immersion Laser Doping (PGILD) process that overcomes the disadvantages of the prior art methods. In particular, the preferred method applies a reflective coating over features before the application of the PGILD laser. The reflective coating lowers the amount of heat absorbed by the features, improving the reliability of the fabrication process. The preferred method is particularly applicable to the fabrication of field effect transistors (FETs). In this application, a gate stack is formed, and a reflective coating is over the gate stack. An anti-reflective coating (ARC) is then applied over the reflective coating. The anti-reflective coating reduces variability of the photolithographic process used to pattern the gate stack. After the gate stack is patterned, the anti-reflective coating is removed, leaving the reflective coating on the gate stack.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: May 28, 2002
    Assignee: International Business Machines Corporation
    Inventors: James A. Bruce, Randy W. Mann
  • Publication number: 20020061613
    Abstract: An anode lead 17 extending from a capacitor body 18 of a capacitor element 14 is mounted on a connecting portion 21 of an anode terminal 12 and the anode lead 17 and the connecting portion 21 are welded together by laser light B. The welding operation is performed by laser light B in a state where the anode lead 17 is urged to the connecting portion 21 in a region between said anode lead and said connecting portion. Alternatively, the welding operation is performed by laser light B in a state where a reflection plate having a slot and functioning to reflect reflected laser light is arranged in a region between the connecting portion and the capacitor body while the anode lead is received in said slot.
    Type: Application
    Filed: November 14, 2001
    Publication date: May 23, 2002
    Applicant: NEC CORPORATION
    Inventors: Mitsunori Sano, Takashi Kono, Kazunori Watanabe
  • Patent number: 6376276
    Abstract: There is provided a method of reliably preparing a diamond semiconductor by irradiating diamond with a corpuscular ray. In this method, when a diamond substrate is irradiated with a corpuscular ray, the diamond substrate is maintained at a temperature of 300° C. to 2000° C., the angle of the surface of the diamond substrate irradiated is set within −20° to +20° to the (001) crystal plane of the diamond substrate, and the angle of the direction of the corpuscular ray is set within −20° to +20° to the <001> crystal orientation of the diamond substrate. Preferably, the direction of the corpuscular ray forms an angle of 3° to 10° with the <001> crystal orientation.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: April 23, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ryuichi Oishi, Yoshinobu Nakamura
  • Patent number: 6365476
    Abstract: A simplified and cost reduced process for fabricating a field-effect transistor semiconductor device (104) using laser radiation is disclosed. The process includes the step of forming removable first dielectric spacers (116R) on the sides (120a, 120b) of the gate (120). Dopants are implanted into the substrate (100) and the substrate is annealed to form an active deep source (108) and an active deep drain (110). The sidewall spacers are removed, and then a blanket pre-amorphization implant is performed to form source and drain amorphized regions (200a, 200b) that include respective extension regions (118a, 118b) that extend up to the gate. A layer of material (210 is deposited over the source and drain extensions, the layer being opaque to a select wavelength of laser radiation (220). The layer is then irradiated with laser radiation of the select wavelength so as to selectively melt the amorphized source and drain extensions, but not the underlying substrate.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: April 2, 2002
    Assignee: Ultratech Stepper, Inc.
    Inventors: Somit Talwar, Yun Wang
  • Patent number: 6358784
    Abstract: A process for laser processing an article, which comprises: heating the intended article to be doped with an impurity to a temperature not higher than the melting point thereof, said article being made from a material selected from a semiconductor, a metal, an insulator, and a combination thereof; and irradiating a laser beam to the article in a reactive gas atmosphere containing said impurity, thereby allowing the impurity to physically or chemically diffuse into, combine with, or intrude into said article.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: March 19, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 6355543
    Abstract: A method for making a ULSI MOSFET chip includes forming a transistor gate on a substrate and defining the contours of shallow source/drain extensions by implanting a first pre-amorphization (PAI) substance into the substrate. A sidewall spacer is then formed on the substrate next to the gate, and a second PAI substance is implanted into the substrate to defame the contours of a deep source/drain junction. Then, a dopant is provided on the surface of the substrate, and the portions of the substrate that contain PAI substances are silicidized to render the portions relatively more absorbing of laser energy. These pre-amorphized portions are then annealed by laser to melt only the pre-amorphized portions. During melting, the dopant is driven from the surface of the substrate into the pre-amorphized portions to thereby establish source/drain regions below the gate.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: March 12, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bin Yu
  • Patent number: 6355544
    Abstract: Extremely high dopant concentrations are uniformly introduced into a semiconductor material by laser annealing aided by an anti-reflective coating (ARC). A spin-on-glass (SOG) film containing dopant is formed on top of the semiconductor material. An ARC is then formed over the doped SOG layer. Application of radiation from an excimer laser to the ARC heats and melts the doped SOG film and the underlying semiconductor material. During this melting process, dopant from the SOG film diffuses uniformly within the semiconductor material. Upon removal of the laser radiation, the semiconductor material cools and crystallizes, evenly incorporating the diffused dopant within its lattice structure. The ARC suppresses reflection of the laser by the doped material, promoting efficient transfer of energy from the laser to heat and melt the underlying doped layer and semiconductor material.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: March 12, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Stepan Essaian, Abdalla A. Naem
  • Patent number: 6306694
    Abstract: A semiconductor device having high operating performance and reliability is disclosed, and its fabrication process is also disclosed. In an n-channel type TFT 302, an Lov region 207 is disposed, whereby a TFT structure highly resistant to hot carriers is realized. Further, in an n-channel type TFT 304 forming a pixel portion, Loff regions 217 to 220 are disposed, whereby a TFT structure having a low OFF-current value is realized. In this case, in the Lov region, the n-type impurity element exists at a concentration higher than that of the Loff regions, and the whole of the n-type impurity region (b) which constitutes the Lov region is sufficiently activated by optical annealing, so that a good junction portion is formed between the n-type impurity region and the channel forming region.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: October 23, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hidehito Kitakado
  • Patent number: 6303476
    Abstract: A method, apparatus and system for controlling the amount of heat transferred to a process region (30) of a workpiece (W) from exposure with laser radiation (10) using a thermally induced reflectivity switch layer (60). The apparatus of the invention is a film stack (6) having an absorber layer (50) deposited atop the workpiece, such as a silicon wafer. A portion of the absorber layer covers the process region. The absorber layer absorbs laser radiation and converts the absorbed radiation into heat. A reflective switch layer (60) is deposited atop the absorber layer. The reflective switch layer may comprise one or more thin film layers, and preferably includes a thermal insulator layer and a transition layer. The portion of the reflective switch layer covering the process region has a temperature that corresponds to the temperature of the process region.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: October 16, 2001
    Assignee: Ultratech Stepper, Inc.
    Inventors: Andrew M. Hawryluk, Somit Talwar, Yun Wang, Michael O. Thompson
  • Patent number: 6300228
    Abstract: A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: October 9, 2001
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, James A. Bruce, John J. Ellis-Monaghan, Randy W. Mann, Edward J. Nowak, Kirk D. Peterson
  • Publication number: 20010027001
    Abstract: An impurity doped SiC substrate 1 and SiC thin film 2 are irradiated with a laser light 5 having a wavelength longer than such a wavelength that a band edge absorption of a semiconductor is caused. The wavelength of the laser light 5 may be such a wavelength that an absorption is caused by a vibration by the bond of an impurity element and an element constituting the semiconductor, for example, a wavelength of 9 &mgr;m to 11 &mgr;m. Specifically, in the case where Al is doped in SiC, the wavelength of the laser light 5 may be within the range of 9.5 &mgr;m to 10 &mgr;m.
    Type: Application
    Filed: May 11, 2001
    Publication date: October 4, 2001
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Akihisa Yoshida, Masatoshi Kitagawa, Masao Uchida, Makoto Kitabatake, Tsuneo Mitsuyu
  • Patent number: 6287889
    Abstract: An improved gas phase synthesized diamond, CBN, BCN, or CN thin film having a modified region in which strain, defects, color and the like are reduced and/or eliminated. The thin film can be formed on a substrate or be a free-standing thin film from which the substrate has been removed. The thin film can be stably and reproducibly modified to have an oriented polycrystal structure or a single crystal structure. The thin film is modified by being subjected to and heated by microwave irradiation in a controlled atmosphere. The thin film has a modified region in which a line width of the diamond spectrum evaluated by Raman spectroscopy of 0.1 microns or greater is substantially constant along a film thickness direction of the thin film, and the line width of the modified region is 85% or less of a maximum line width of the residual portion of the film thickness.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: September 11, 2001
    Assignee: Applied Diamond, Inc.
    Inventors: Shoji Miyake, Shu-Ichi Takeda
  • Publication number: 20010018258
    Abstract: The present invention discloses a method for fabricating a semiconductor device which can form a MOSFET device according to a laser doping method. When junctions of the MOSFET device are formed, the MOSFET device has various junction depths by region, by using a doping difference according to the heat and time of a laser irradiation process. As compared with a two-dimensional method for controlling a property of the transistor by a channel width and length, the present invention provides a method for exercising three-dimensional control over the formation of transistors and other junctions in a semiconductor device.
    Type: Application
    Filed: January 2, 2001
    Publication date: August 30, 2001
    Inventor: Kyeong Yoon
  • Patent number: 6255201
    Abstract: An impurity doped SiC substrate 1 and SiC thin film 2 are irradiated with a laser light 5 having a wavelength longer than such a wavelength that a band edge absorption of a semiconductor is caused. The wavelength of the laser light 5 may be such a wavelength that an absorption is caused by a vibration by the bond of an impurity element and an element constituting the semiconductor, for example, a wavelength of 9 &mgr;m to 11 &mgr;m. Specifically, in the case where Al is doped in SiC, the wavelength of the laser light 5 may be within the range of 9.5 &mgr;m to 10 &mgr;m.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: July 3, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihisa Yoshida, Masatoshi Kitagawa, Masao Uchida, Makoto Kitabatake, Tsuneo Mitsuyu
  • Patent number: 6221726
    Abstract: Silicon device structures designed to allow measurement of important doping process parameters immediately after the doping step has occurred. The test structures are processed through contact formation using standard semiconductor fabrication techniques. After the contacts have been formed, the structures are covered by an oxide layer and an aluminum layer. The aluminum layer is then patterned to expose the contact pads and selected regions of the silicon to be doped. Doping is then performed, and the whole structure is annealed with a pulsed excimer laser. But laser annealing, unlike standard annealing techniques, does not effect the aluminum contacts because the laser light is reflected by the aluminum. Once the annealing process is complete, the structures can be probed, using standard techniques, to ascertain data about the doping step.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: April 24, 2001
    Assignee: The Regents of the University of Claifornia
    Inventor: Kurt H. Weiner
  • Patent number: 6172380
    Abstract: A semiconductor material having more excellent electric characteristics than polycrystalline semiconductor materials and readily formed on various kinds of substrates is provided. The semiconductor material is made of substantially single crystalline semiconductor crystal grains 3a. These crystal grains 3a are preferentially oriented in a common surface orientation, such as {100}, {111} or {110}-orientation, and grain boundaries 3b of adjacent ones of the crystal grains 3a are in substantial lattice matching with each other at least in a part thereof. In case of {100} orientation, each crystal grain 3a has an approximately square shape, and they are regularly aligned in rows and columns. In case of {111} orientation, each crystal grain 3a has an approximately equilateral hexagonal shape, and they are aligned in an equilateral turtle shell pattern.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: January 9, 2001
    Assignee: Sony Corporation
    Inventors: Takashi Noguchi, Yuji Ikeda
  • Patent number: 6169004
    Abstract: A P-type impurity layer, a silicon monocrystal film, a silicon oxide film and a crystal silicon film are successively formed on a semiconductor substrate by introducing appropriate functional gases on the semiconductor substrate, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250° C. After forming a photoresist on the crystal silicon film at a temperature lower than 250° C., the resultant semiconductor substrate is subjected to etching by using the photoresist as a mask, so as to form a gate electrode B out of the silicon oxide film and a gate insulating film out of the silicon oxide film. Then, the resultant semiconductor substrate is subjected to etching again by using the gate electrode as a mask, so as to form a channel region out of the P-type impurity layer. A source electrode and a drain electrode are formed on the respective sides of the gate electrode on the semiconductor substrate by introducing an appropriate functional.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Bunji Mizuno, Kenji Okada, Ichirou Nakayama
  • Patent number: 6156629
    Abstract: A method of etching polysilicon using an oxide hard mask using a three step etch process. Steps one and two are performed insitu in a high density plasma (e.g., TCP--transformer coupled plasma) oxide etcher. Step 3, the polysilicon etch is performed in a different etcher (e.g., poly RIE etcher). A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: December 5, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hun-Jan Tao, Yuan-Chang Huang
  • Patent number: 6130120
    Abstract: A method and structure for crystallizing film is disclosed. The method includes the steps of forming a film on a substrate, forming a lens on the film to focus an electro-magnetic wave on the film and directing the electro-magnetic wave on the film inclusive of the lens to crystallize the film.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: October 10, 2000
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Min Hwa Park
  • Patent number: 6124175
    Abstract: Rapid thermal anneal with a gaseous dopant species is disclosed. In one embodiment, a method includes three steps. In the first step, at least one gate is formed over a semiconductor substrate. In the second step, at least one spacer for each of the gates is formed, where each spacer is adjacent to an edge of its corresponding gate. In the third step, a rapid thermal anneal with a gaseous dopant species is performed to form source and drain regions within the substrate. Desirably, the source and drain regions meet the substrate underneath the gate at shallow junctions.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: September 26, 2000
    Assignee: Advanced Micro Devices Inc.
    Inventors: Mark I. Gardner, H. James Fulford
  • Patent number: 6100171
    Abstract: In one embodiment, the present invention relates to a method of removing fluorine from a gate conductor involving the steps of providing a semiconductor device containing a substrate, a gate insulator layer overlying a portion of the substrate, a gate conductor containing fluorine overlying the gate insulator layer, and a source and a drain region adjacent the gate insulator layer; and laser annealing the semiconductor device at an energy level sufficient to melt at least a portion of the gate conductor thereby inducing the removal of fluorine from the gate conductor. In another embodiment, the present invention relates to a method of making a transistor involving the steps of forming a gate conductor overlying a gate insulator layer, wherein the gate conductor and the gate insulator layer overlie a portion of a substrate, doping the substrate and gate conductor with BF.sub.2.sup.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: August 8, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Emi Ishida
  • Patent number: 6086726
    Abstract: The present invention provides a surface modification method that provides beneficial changes in surface properties, can modify a surface to a greater depth than previous methods, and that is suitable for industrial application. The present method comprises applying a thin-film coating to a surface of a substrate, then subjecting the coated surface to an ion beam. The ion beam power pulse heats the coated surface, leading to alloying between the material in the coating and the material of the substrate. Rapid cooling of the alloyed layer after an ion beam pulse can lead to formation of metastable alloys and microstructures not accessible by conventional alloying methods or intense ion beam treatment of the substrate alone.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: July 11, 2000
    Assignee: Sandia Corporation
    Inventors: Timothy J. Renk, Neil R. Sorensen, Donna Cowell Senft, Rudolph G. Buchheit, Jr., Michael O. Thompson, Kenneth S. Grabowski