Forming Partially Overlapping Regions Patents (Class 438/545)
  • Patent number: 9236522
    Abstract: A method of fabricating a semiconductor device includes forming an absorber on a substrate, and supporting a cap layer over the substrate to define a cavity between the substrate and the cap layer in which the absorber is located. The method further includes forming a lens layer on the cap layer. The lens layer is spaced apart from the cavity and defines a plurality of grooves and an opening located over the absorber.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: January 12, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Ashwin K. Samarao, Gary O'Brien, Ando Feyh, Fabian Purkl, Gary Yama
  • Patent number: 9029226
    Abstract: The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The mechanisms overcome the limitation by shadowing effects of ion implantation for advanced finFET devices. The highly doped source and drain regions are formed by epitaxial growing one or more doped silicon-containing materials from recesses formed in the fins. The dopants are then driven into the LDD regions by advanced annealing process, which can achieve targeted dopant levels and profiles in the LDD regions.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Tsan-Chun Wang, Su-Hao Liu
  • Patent number: 8921938
    Abstract: Some of the embodiments of the present disclosure provide a transistor comprising a p-type well; and an n-type well; wherein at least a part of one of the p-type well and the n-type well overlaps with at least a part of another of the p-type well and the n-type well. Other embodiments are also described and claimed.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 30, 2014
    Assignee: Marvell International Ltd.
    Inventors: Xin Yi Zhang, Weidan Li, Chuan-Cheng Cheng, Jian-Hung Lee, Chung Chyung (Jason) Han
  • Patent number: 8697559
    Abstract: One method of implanting a workpiece involves implanting the workpiece with an n-type dopant in a first region with center and a periphery. The workpiece also is implanted with a p-type dopant in a second region complementary to the first region. This second region also has a center and a periphery. The periphery of the first region and the periphery of the second region at least partially overlap. A dose at the periphery of the first region or second region is less than a dose at the center of the first region or second region. The region of overlap may function as a junction where charge carriers cannot pass.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 15, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Peter L. Kurunczi, Benjamin B. Riordon, John W. Graff
  • Patent number: 8637955
    Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion, implantation.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: January 28, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lingquan Wang, Teymur Bakhishev, Dalong Zhao, Pushkar Ranade, Sameer Pradhan, Thomas Hoffmann, Lucian Shifren, Lance Scudder
  • Patent number: 8629026
    Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8587015
    Abstract: Disclosed herein is a light-emitting element including: a first conductivity type semiconductor layer; a light-emitting functional layer formed on the first conductivity type semiconductor layer; a second conductivity type semiconductor layer formed on the light-emitting functional layer; a first conductivity type electrode which has continuity with the exposed portion of the first conductivity type semiconductor layer; a second conductivity type electrode which has continuity with the second conductivity type semiconductor layer; an insulating layer which lies between the light-emitting functional layer, second conductivity type semiconductor layer and second conductivity type electrode on one part and the first conductivity type electrode on the other part; and an annex insulating layer annexed to the insulating layer to form a virtual diode having rectifying action in the opposite direction to that of a diode made up of the second conductivity type semiconductor layer, light-emitting functional layer and f
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: November 19, 2013
    Assignee: Sony Corporation
    Inventor: Hidekazu Aoyagi
  • Patent number: 8497205
    Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Mitsuaki Izuha
  • Patent number: 8420495
    Abstract: This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: April 16, 2013
    Assignee: Shanghai Hua Hong Nec Electronics Company, Limited
    Inventors: Tzuyin Chiu, TungYuan Chu, YungChieh Fan, Wensheng Qian, Fan Chen, Jiong Xu, Haifang Zhang
  • Publication number: 20120211747
    Abstract: A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.
    Type: Application
    Filed: August 28, 2009
    Publication date: August 23, 2012
    Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Paul Ronald Stribley, Soon Tat Kong
  • Patent number: 8222114
    Abstract: This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: July 17, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Company, Limited
    Inventors: Tzuyin Chiu, TungYuan Chu, YungChieh Fan, Wensheng Qian, Fan Chen, Jiong Xu, Haifang Zhang
  • Patent number: 8017488
    Abstract: A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations mainly implants both phosphorous and arsenic ions on a drain area of a transistor memory unit, and controls specific energy and dosage for the implantation to reduce the defects of a memory device and improve the yield rate of the NOR flash memory.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: September 13, 2011
    Assignee: EON Silicon Solutions Inc.
    Inventors: Sheng-Da Liu, Yider Wu
  • Patent number: 7972948
    Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 5, 2011
    Assignee: Spansion LLC
    Inventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
  • Patent number: 7955929
    Abstract: A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 7, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Evgueniy Stefanov, Ivana Deram, Jean-Michel Reynes
  • Patent number: 7897497
    Abstract: A light-generating semiconductor region is grown by epitaxy on a silicon substrate. The light-generating semiconductor region is a lamination of layers of semiconducting nitrides containing a Group III element or elements. The silicon substrate has a p-type impurity-diffused layer formed therein by thermal diffusion of the Group III element or elements from the light-generating semiconductor region as a secondary product of the epitaxial growth of this region on the substrate. The p-type impurity-diffused layer is utilized as a part of overvoltage protector diodes which are serially interconnected with each other and in parallel with the LED section of the device between a pair of electrodes.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: March 1, 2011
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Yasuhiro Kamii, Arei Niwa, Junji Sato, Mikio Tazima
  • Patent number: 7875517
    Abstract: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: January 25, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Cai
  • Patent number: 7863170
    Abstract: A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried zone, a second zone having a second conductivity type that is different from the first conductivity type and above the first zone, and a third zone having the first conductivity type that is above the second zone. The buried zone includes first and second implantation regions that are formed via first and second implantations that are performed using a mask. The buried zone, the first zone, the second zone and the third zone are parts of a first transistor structure.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: January 4, 2011
    Assignee: Austriamicrosystems AG
    Inventors: Georg Röhrer, Bernard Löffler, Jochen Kraft
  • Patent number: 7811915
    Abstract: A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: October 12, 2010
    Assignee: Spansion LLC
    Inventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
  • Patent number: 7759210
    Abstract: A method for forming a MOS device on a semiconductor substrate includes steps of: forming a gate structure on the semiconductor substrate; implanting ions into the semiconductor substrate for forming one or more lightly doped drain structures adjacent to the gate structure; thermally treating the semiconductor substrate at a first temperature lower than a threshold temperature, below which no substantial transient enhanced diffusion of the lightly doped drain structures occurs, for repairing damage to the semiconductor substrate caused by the ion implantation; forming sidewall spacers to sidewalls of the gate structure on the semiconductor substrate; and forming source and drain regions adjacent to the gate structure in the semiconductor substrate.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 20, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Tsung Huang, Fung Ka Hing
  • Publication number: 20100154877
    Abstract: A cane having optical properties includes: a core formed of a semiconductor material; and a transparent cladding formed of glass, glass-ceramic, or polymer coaxially oriented about the core, the cane may be used to produce a photovoltaic device, including: a semiconductor core including at least one p-n junction, defined by respective n-type and p-type regions; a substantially transparent cladding in coaxial relationship with the semiconductor core, forming a longitudinally oriented cane; and first and second electrodes, each being electrically coupled to a respective one of the n-type and p-type regions.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 24, 2010
    Inventors: Venkata Adiseshaiah Bhagavatula, David John McEnroe
  • Patent number: 7727831
    Abstract: The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in the cell region 60. Therefore, the depleted layer extending from the cell region 60 along the direction toward the gate pad portion 50 or the direction toward the circumference portion 70 is blocked by the presence of the trench 112. In other words, an extending of the depleted layer can be terminated by disposing the trench 112, so as to avoid reaching the depleted layer to the end of the semiconductor chip. Accordingly, a leakage current generated from the cell region 60 along the direction toward the end of the semiconductor chip can be reduced.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: June 1, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kinya Ohtani
  • Patent number: 7645665
    Abstract: A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of the semiconductor substrate into which ions were implanted; and (d) after the step (c) is performed, executing second annealing with a heating time longer than the heating time of the first annealing, relative to the region of the semiconductor substrate into which ions were implanted. The method for manufacturing a semiconductor device is provided which can dope boron (B) shallowly and at a high concentration.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: January 12, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tomohiro Kubo, Kenichi Okabe, Tomonari Yamamoto
  • Patent number: 7485947
    Abstract: A zener diode circuit includes a semiconductor substrate having an N-doped region and a P-doped region that form a PN junction. The N-doped region and the P-doped region have areas with widths that decrease as the N-doped region and the P-doped region approach the PN junction. The zener diode circuit also includes a transistor that provides current to the zener diode, and circuitry that detects a state of the zener diode.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: February 3, 2009
    Assignee: Austriamicrosystems AG
    Inventor: Franz Unterleitner
  • Patent number: 7144796
    Abstract: A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least one trench and active regions are formed in the substrate. The trench may be a shallow drift zone trench of a DMOS-transistor, and/or a deep isolation trench. The thermal diffusion of the well dopants includes at least one first diffusion step during a first high temperature drive before forming the trench, and at least one second diffusion step during a second high temperature drive after forming the trench. Dividing the thermal diffusion steps before and after the trench formation achieves an advantageous balance between reducing or avoiding lateral overlapping diffusion of neighboring wells and reducing or avoiding thermally induced defects along the trench boundaries.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: December 5, 2006
    Assignee: Atmel Germany GmbH
    Inventors: Franz Dietz, Volker Dudek, Michael Graf
  • Patent number: 6936527
    Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: August 30, 2005
    Assignee: Xilinx, Inc.
    Inventor: Kevin T. Look
  • Patent number: 6756270
    Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: June 29, 2004
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Chang Soo Lee
  • Patent number: 6727527
    Abstract: A power device includes a semiconductor substrate of first conductivity type. The semiconductor substrate includes a front-side surface, a backside surface, and a scribe region. The substrate has a first well of second conductivity type whereon an active cell is defined. The first well has a first impurity type of a first mobility. A continuous diffusion region of second conductivity type extends from the front-side surface to the backside surface. The continuous diffusion region includes a second impurity type of a second mobility that has been diffused vertically into the substrate from a selected location of the backside surface. The second mobility is higher than the first mobility. A lower portion of the continuous diffusion region corresponds to the selected location of the continuous diffusion region.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: April 27, 2004
    Assignee: IXYS Corporation
    Inventor: Nathan Zommer
  • Patent number: 6706606
    Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: March 16, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory G. Romas, Jr., Darrel C. Oglesby, Jr.
  • Patent number: 6696335
    Abstract: For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantially directed form, in particular in substantially a preferential direction, by interaction of a provided dopant with a transforming interfacial region.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: February 24, 2004
    Assignee: Infineon Technologies AG
    Inventors: Dietrich Bonart, Peter Voigt
  • Patent number: 6635505
    Abstract: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: October 21, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio Tanaka, Shou Nagao
  • Patent number: 6579782
    Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: June 17, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Mathieu Roy
  • Patent number: 6569691
    Abstract: A method and apparatus for measuring the concentration of different mobile ions in the oxide layer of a semiconductor wafer from the contact potential shift caused by different ions drifting across the oxide that includes depositing charge (e.g., using a corona discharge device) on the surface of the oxide and heating the wafer to allow different mobile ions in the oxide to drift. The difference in the contact potential measured before and after heating provides an indication of the different mobile ion concentration in the oxide layer.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: May 27, 2003
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Lubomir L. Jastrzebski, Alexander Savtchouk, Marshall D. Wilson
  • Patent number: 6559019
    Abstract: An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conductivity type and a lightly doped region of opposite conductivity type between the highly doped region and the surface of tank. The lightly doped region in the tank is doped both the predetermined conductivity type and the opposite conductivity type with a resulting net lightly opposite conductivity type doping. A drain region of opposite conductivity type is disposed in the region of the tank between the highly doped region and the surface and disposed at the surface and a source region of opposite conductivity type is disposed in the well and spaced from the tank.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: May 6, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Baoson Nguyen
  • Patent number: 6475861
    Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: November 5, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Chang Soo Lee
  • Patent number: 6455380
    Abstract: A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: September 24, 2002
    Assignee: LG Semicon Co., Ltd
    Inventor: Gyu Han Yoon
  • Patent number: 6444522
    Abstract: There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a break down voltage between wells is reduced and an insulating characteristic between the wells is lowered due to degraded barrier characteristic between the wells, in a flash memory device employing a triple well structure, the present invention forms an anti-diffusion region for preventing diffusion of dopants between a P-well region and a N-well region by nitrogen ion implantation, thus improving the electrical characteristic of the device.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: September 3, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Byung Hee Cho, Noh Yeal Kwak
  • Patent number: 6436769
    Abstract: The present invention provides a flash memory having a split gate structure and virtual ground array structure, wherein a high impurity concentration region of a first conductivity type is provided in a drain adjacent region of a channel region under a floating gate electrode, and the high impurity concentration region has a highest impurity concentration in the channel region, and wherein a low impurity concentration region of a first conductivity type is provided in the channel region but at a part not covered by the floating gate.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: August 20, 2002
    Assignee: NEC Corporation
    Inventor: Kohji Kanamori
  • Publication number: 20020105055
    Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.
    Type: Application
    Filed: March 28, 2002
    Publication date: August 8, 2002
    Inventors: Walter R. Buchanan, Roman J. Hamerski
  • Patent number: 6429077
    Abstract: The present invention provides a method of forming a lateral diffused metal-oxide semiconductor (LD MOS) transistor on a semiconductor wafer. An ion implantation process is performed on a predetermined area of the silicon substrate so as to form a p-well adjacent to an n-well. An insulation layer is then formed on a predetermined area of the n-well. A gate layer is formed on a portion of the p-well and the n-well, and one side of the gate layer is positioned on the surface of the insulation layer. Finally, an ion implantation process is performed to form two n-type doped regions on the p-well and the n-well. The two doped regions are used as the source and the drain of the LD MOS transistor.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: August 6, 2002
    Assignee: United Microelectronics Corp.
    Inventor: Ming-Tsung Tung
  • Patent number: 6391689
    Abstract: A semiconductor substrate having a doped well region is provided. A gate stacking structure is formed on the doped well region. The gate stacking structure divides the doped well region into a first area and a second area. The second area is masked. The first area is masked. A spacer is formed on each side wall of the gate stacking structure. A dielectric layer is formed on the semiconductor substrate to cover the gate stacking structure, the spacer, the first doped area, and the second doped area. A via is formed on the dielectric layer. An in-situ doped poly-silicon is utilized to fill the via.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: May 21, 2002
    Assignee: United Microelectronics Corp.
    Inventor: Chin-Yang Chen
  • Patent number: 6368928
    Abstract: A method of forming an implanted pocket region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an initial indium pocket region, with an initial indium profile, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, a low temperature anneal procedure is used to activate indium ions in the initial indium pocket region, and to create a final indium pocket region, featuring a final indium profile. The final indium profile remains unchanged after experiencing subsequent high temperature procedures, such as a post-heavily doped, source/drain anneal. The narrow channel length NMOS devices, fabricated using the low temperature anneal procedure described in this invention, resulted in a reduced Vt roll-off phenomena, when compared to counterpart, narrow channel length NMOS, formed without the benefit of the low temperature anneal procedure.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: April 9, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Howard Chih-Hao Wang, Su-Yu Lu, Mu-Chi Chiang, Yu-Sen Chu, Chao-Jie Tsai, Carlos H. Diaz
  • Publication number: 20020037636
    Abstract: An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in accordance with the principle of lateral charge compensation. The edge termination is formed in the base material wafer by implanting a rapidly diffusing dopant. Preferred dopants are selenium and sulfur. The high-voltage withstand strength is effected by a resulting doping profile which increases towards the edge termination.
    Type: Application
    Filed: October 10, 2001
    Publication date: March 28, 2002
    Inventors: Hans-Joachim Schulze, Gerald Deboy
  • Patent number: 6345399
    Abstract: The propagation of microfissures from a photoresist to an underlying material layer during lithography and etching can be substantially prevented by placing a hard mask between the photoresist and the material layer to be etched. Specifically, the microfissure propagation is substantially prevented by (a) forming a compressive hard mask on a surface of a non-compressive material layer that is to be patterned by lithography and etching; (b) forming a patterned photoresist on said hard mask, wherein a portion of said hard mask is exposed; (c) removing said exposed portion of said hard mask so as to expose a portion of said non-compressive material layer; and (d) transferring said pattern from said patterned photoresist to said exposed portion of said material layer by etching, wherein said hard mask is selective to said etching and thus substantially prevents the propagation of photoresist microfissures to said material layer.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: February 12, 2002
    Assignee: International Business Machines Corporation
    Inventors: Paul C. Jamison, Tina Wagner, Richard S. Wise, Hongwen Yan
  • Patent number: 6329272
    Abstract: The invention relates to a method of iteratively, selectively tuning the impedance of integrated semiconductor devices, by modifying the dopant profile of a region of low dopant concentration by controlled diffusion of dopants from one or more adjacent regions of higher dopant concentration through the melting action of a focussed heating source, for example a laser. In particular the method is directed to increasing the dopant concentration of the region of lower dopant concentration, but may also be adapted to decrease the dopant concentration of the region.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: December 11, 2001
    Assignee: Technologies LTrim Inc.
    Inventors: Yves Gagnon, Michel Meunier, Yvon Savaria
  • Patent number: 6238985
    Abstract: A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: May 29, 2001
    Assignee: LG Semicon Co., Ltd.
    Inventor: Gyu Han Yoon
  • Patent number: 6232182
    Abstract: A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region with a first insulating film interposed therebetween and including a laminate of a floating gate electrode, a second insulating film and a control gate electrode; a gate electrode of the selection transistor formed on the surface of the semiconductor substrate at its second region close to the first region with a third insulating film interposed therebetween; and an impurity diffusion layer formed in the semiconductor substrate at its region between the first and second regions and functioning as a drain of the memory transistor, common to a source of the selection transistor, the impurity diffusion layer having at least an extension region extending to a part of the semiconductor substrate disposed under the composite gate structure, the extension region hav
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: May 15, 2001
    Assignee: Nippon Steel Corporation
    Inventor: Fumitaka Sugaya
  • Patent number: 6207540
    Abstract: A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, William H. Ma, Jack A. Mandelman
  • Patent number: 6180442
    Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: January 30, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Yvon Gris
  • Patent number: 6169001
    Abstract: In this invention a current block is implanted into the drain of a transistor to provide for ESD protection and allow the shrinking of the transistor. The block increases the current path into the semiconductor bulk and increases heat dissipation capability. The current block is created by implanting P+ into a region in an N+ drain, and through the drain into an N-well laying below the drain. A high resistance of the block forces drain current flowing from the channel to the drain contact into the semiconductor bulk. The block is the full width of the drain spreading out the current from an ESD and forcing current from the channel down into the N-well, under the block, and back up to the drain contact area. The increased path and the spreading of the drain current through the semiconductor bulk enhances heat dissipation, and allows smaller devices and layout area with ESD protection.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: January 2, 2001
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Geeng-Lih Lin, Ming-Dou Ker
  • Patent number: 6156594
    Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: December 5, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Yvon Gris