Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

Abstract: A transistor of SiC having a drain and a highly doped substrate layer is formed on the drain. A highly n type buffer layer may optionally be formed on the substrate layer. A low doped n-type drift layer, a p-type base layer, a high doped n-type source region layer and a source are formed on the substrate layer. An insulating layer with a gate electrode is arranged on top of the base layer and extends substantially laterally from at least the source region layer to a n-type layer. When a voltage is applied to the gate electrode, a conducting inversion channel is formed extending substantially laterally in the base layer at an interface of the p-type base layer and the insulating layer. The p-type base layer is low doped in a region next to the interface to the insulating layer at which the inversion channel is formed and highly doped in a region thereunder next to the drift layer.

Abstract: A process for device fabrication in which transient enhanced diffusion (TED) is used to obtain a desired distribution of dopants in a crystalline substrate is disclosed. In the process, at least two dopants and a non-dopant are introduced into the same region of a substrate. The diffusion of the dopants in the substrate during a subsequent thermal anneal is affected by the non-dopant. The amount of non-dopant introduced into the substrate is selected to obtain, in conjunction with the subsequent thermal anneal, the desired distribution of dopants in the substrate. The concentration of the non-dopant is in the range of about 6.times.10.sup.16 atoms/cm.sup.3 to about 3.times.10.sup.21 atoms/cm.sup.3. The substrate is then annealed at a temperature in the range of about 700.degree. C. to about 950.degree. C. to obtain the desired dopant profile.

Abstract: A method for fabricating an interconnect with high aspect ratio contact members is provided. The interconnect is adapted to make electrical connections with a semiconductor component, such as a die, a wafer, or a chip scale package for testing. The method includes providing a substrate with projections, and forming a first conductive layer on the projections and substrate. The first conductive layer is then patterned using a resist mask having a thickness greater than a height of the projections. The resist mask can be a thick film resist that includes an epoxy resin, an organic solvent and a photo initiator. A second conductive layer is then formed on the projections, and patterned using a second resist mask having a thickness less than the height of the projections. Each contact member includes a projection with a tip portion having an exposed portion of the first conductive layer, and with a portion of the second conductive layer providing an electrical path to the projection.

Abstract: A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide region may overlie at least a portion of the first and second active regions. The apparatus further includes a gate positioned over the channel region and having a first end and a second end respectively associated with the first and second active regions. The gate includes a first low conductive region and a second low conduction region at said first and second ends, respectively.A method for making the transistor structure of the present invention is also provided.

Abstract: On the surface of a semiconductor substrate there are formed a silicon oxide film, silicon nitride film and resist, whereby a groove is formed in the semiconductor substrate through an opening portion by chemical dry etching. An oxide film is formed on the inner surface of the groove by wet oxidation and, further, this oxide film is removed by wet etching, after which the surface of the semiconductor substrate located on the outer-peripheral side of the groove from an angular portion defined between a side surface of the groove and the surface of the semiconductor substrate is exposed. Then, the inner surface of the groove and the exposed surface of the semiconductor substrate are oxidized to thereby form a LOCOS oxide film, and thereafter this LOCOS oxide film is removed. As a result of this, the angular portion is made round, thereby enabling the avoidance of the concentration of an electric field on the angular portion of the groove.

Abstract: A silicon on insulator (SOI) process is disclosed which includes the steps of forming an etch stop layer in a starting wafer, forming an insulating layer on the etch stop layer, bonding this wafer to a handle wafer, thinning the start wafer down to the etch stop and then recovering a device layer from the etch stop layer by outgassing dopants from the etch stop layer.

Abstract: An insulated gate field effect transistor is manufactured according to a process in which an insulated gate structure is formed along a semiconductor chip. Dopant is introduced into the chip to form a body region, semiconductor material outside the body region forming a drain region. Dopant is introduced into the chip at the location of part of the body region to form a source region spaced apart from the drain region by a channel region. Dopant of the same conductivity type as the body-region dopant is introduced through a dopant-introducing section of the chip's upper surface and into the chip at the location of part of the body region to form a sub-surface peaked portion of the body region, the dopant-introducing section being spaced laterally apart from the channel and source regions. The sub-surface peaked portion reaches a peak net dopant concentration below the chip's upper surface so as to improve the transistor's ruggedness under drain avalanche conditions.

Abstract: A process for manufacturing an integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active elements of the power device are present. The chip portion has at least one second sub-portion wherein no functionally active elements of the power device are present. The top surface of the at least one second sub-portion is elevated with respect to the first sub-portion to form at least one protrusion which forms a support surface for a wire.

Abstract: A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.

Abstract: A semiconductor device and fabrication method therefor which improve device operation of a CMOS device. The semiconductor device and fabrication method therefor prevent the deterioration of short channel properties of a PMOS device and improve current driving capability of an NMOS device. The semiconductor device has halo impurity regions formed in either the NMOS region or the PMOS region such that a channel length of the PMOS device. Also, the source channel length of the PMOS device. Also, the source and drain regions of the PMOS device are prevented from forming deep source and drain regions, thus, preventing deterioration of the short channel properties for the PMOS device.

Abstract: A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the s