Abstract: The present invention provides a method for producing a bonded wafer comprising at least an ion implantation process where at least either hydrogen ions or rare gas ions are implanted into a first wafer from its surface to form a micro bubble layer (implanted layer) in the first wafer, a bonding process where the surface subjected to the ion implantation of the first wafer is bonded to a surface of a second wafer, and a delamination process where the first wafer is delaminated at the micro bubble layer, wherein the ion implantation process is performed in divided multiple steps, and a bonded wafer. Thus, there are provided a method for producing a bonded wafer, which is for reducing micro-voids generated in the ion implantation and delamination method and a bonded wafer free from micro-voids.

Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.

Abstract: A polysilicon thin film transistor and a method of forming the same is provided. A poly-island layer is formed over a substrate. A gate insulation layer is formed over the poly-island layer. A gate is formed over the gate insulation layer. Using the gate as a mask, an ion implantation of the poly-island layer is carried out to form a source/drain region in the poly-island layer outside the channel region. An oxide layer and a silicon nitride layer, together serving as an inter-layer dielectric layer, are sequentially formed over the substrate. Thickness of the oxide layer is thicker than or the same as (thickness of the nitride layer multiplied by 9000 ?)1/2 and maximum thickness of the nitride layer is smaller than 1000 ?.

Abstract: A process for fabricating an electro-optic device is decribed that includes: a) providing a substrate comprising at least two polymer micro-ridges, where each polymer micro-ridge comprises an upper surface and two walls, and the two walls form an angle with a lower surface; b) depositing a metal thin film on the upper surface, the two walls, and the lower surface; c) etching a predetermined amount of the deposited metal thin film on the lower surface, thereby forming two electrodes separated by a gap; d) depositing a nonlinear optical polymer in the gap between the two electrodes; and e) poling the nonlinear optical polymer to induce electro-optic activity.

Abstract: A process for fabricating power semiconductor devices involving preparation of a silicon wafer by epitaxial formation of an intrinsic silicon layer on a silicon substrate and high energy implantation to form channel and drift regions in the intrinsic epitaxial silicon.

Abstract: The present invention provides a highly doped semiconductor layer.

Abstract: The invention relates to a process for treating a portion of the surface of a substrate according to a first and second surface treatments which are different from each other and are intended respectively for a first group of regions and for a second group of regions of the surface portion, the two groups of regions being mutually complementary with respect to the surface portion, the process making it possible to use only a single operation of positioning a mask which differentiates the regions of the first and second groups of regions, using the same protective materials for the regions of each group of regions against the effects of the treatment intended for the regions of the other group of regions. Application to the fabrication of semiconductor products.

Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.

Abstract: A method for applying a passivation layer selectively on an exposed silicon surface from a liquid phase solution supersaturated in silicon dioxide. The immersion is conducted at substantially atmospheric temperature and pressure and achieves an effective passivation layer in an abbreviated immersion time, and without subsequent heat treatment. In one embodiment, rapid coating of a wafer back side with silicon dioxide permits the use of a high-speed electroless process for plating the bond pad with a solder-enhancing material. In another embodiment, the walls of via holes and microvia holes in a silicon body may be passivated by immersion in the supersaturated solution prior to plugging the holes with conductive material.

Abstract: An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.

Abstract: P-type and n-type regions are defined in the first surface of a substrate upon which is formed an epitaxial layer of preferably Si—Ge material, preferably capped by Si material. During epitaxy formation, dopant in the defined regions diffuses down to form p-type and n-type junctions in the Si material, and diffuses up to form p-type and n-type junctions in the Si—Ge epitaxial material. Si junctions are buried beneath the surface and are surface recombination velocity effects are reduced. Photon energy striking the second substrate surface generates electron-hole pairs that experience the high bandgap of the Si materials and the low bandgap of the Si—Ge epitaxy. The tandem structure absorbs photon energy from about 0.6 eV to about 3.5 eV and exhibits high conversion efficiency.

Abstract: Methods and apparatus are provided for forming ultrashallow junctions in semiconductor wafers. The method includes the step of introducing into a shallow surface layer of a semiconductor wafer a dopant material that is selected to form charge carrier complexes, such as exciton complexes, which produce at least two charge carriers per complex. The semiconductor wafer containing the dopant material may be processed, such as by thermal processing, to form the charge carrier complexes. The charge carrier complexes are interstitial and therefore are not subject to the limitations imposed by the electrical solubility limits resulting from incorporation into substitutional sites. Thus, low sheet resistance can be obtained.

Abstract: A method for depositing doped polycrystalline or amorphous silicon film. The method includes placing a substrate onto a susceptor. The susceptor includes a body having a resistive heater therein and a thermocouple in physical contact with the resistive heater. The susceptor is located in the process chamber such that the process chamber has a top portion above the susceptor and a bottom portion below the susceptor. The method further includes heating the susceptor. The method further includes providing a process gas mix into the process chamber through a shower head located on the susceptor. The process gas mix includes a silicon source gas, a dopant gas, and a carrier gas. The carrier gas includes nitrogen. The method further includes forming the doped silicon film from the silicon source gas.

Abstract: A method for producing a semiconductor temperature sensor comprises the steps of forming PNP bipolar transistors and PMOS transistors so that a base region of each of the PNP bipolar transistors and a corresponding N-well region of each of the PMOS transistors are formed at the same time, and connecting the PNP bipolar transistors in a Darlington connection.

Abstract: A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the step of providing a semiconductor wafer including a dielectric layer formed on the wafer. The dielectric layer has vias formed therein. The wafer is placed in a deposition chamber wherein the wafer has a first temperature achieved without preheating. A metal is deposited on the wafer which fills the vias wherein the metal depositing is initiated at a substantially same time as heating the wafer from the first temperature.

Abstract: An impurity concentration profile that improves pn junction breakdown voltage and mitigates the electric field, and that does not adversely affect the characteristics of a field effect transistor is realized. An n type source/drain region is formed at a silicon substrate. A p type impurity concentration profile. includes respective peak concentrations at a dope region for forming a p type well, a p type channel cut region, and a p type channel dope region. An impurity concentration profile of the n type source/drain region crosses the p type impurity concentration profile at a low concentration, and includes phosphorus implantation regions indicating impurity concentrations respectively higher than those of the p type channel cut region and the p type channel dope region and respective peaks in impurity concentration at the neighborhood of respective depth thereof.

Abstract: A tantalum oxide film is formed on a lower conductive film by vapor-deposition, and then is treated with active oxygen species. The treated film is annealed at a temperature lower than the crystallization temperature of tantalum oxide by 10 to 80° C. in an inert atmosphere. Subsequently, an upper conductive film is formed on the annealed tantalum oxide film.

Abstract: Within a method for fabricating a microelectronic device there is first provided a silicon substrate. There is then formed upon the silicon substrate a first series of structures having a comparatively narrow spacing which leaves exposed a first series of comparatively narrow portions of the silicon substrate, and where the first series of structures is separated from a second series of structures also formed upon the silicon substrate, the second series of structures having a comparatively wide spacing which leaves exposed a second series of comparatively wide portions of the silicon substrate. There is then masked one of the first series of comparatively narrow portions of the silicon substrate and the second series of comparatively wide portions of the silicon substrate.

Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.

Abstract: A method for fabricating a type of Trench Mask ROM cell comprises steps including: providing a substrate doped lightly with p-type dopant, sequentially forming a pad oxide layer and a nitride layer on the substrate; etching back the pad oxide layer, the nitride layer and the substrate to form plural trenches; a gate oxide layer being formed on surfaces of each trench; then, implanting n+-type ions into the substrate beneath the pad oxide layer and between each two adjacent trenches; and, forming a polysilicon layer on the gate oxide and pad oxide; finally, implanting n+-type ions into the substrate beneath the gate oxide layer on bottoms of selected trenches. And, it is appreciated that the sequence of the formation of plural trenches and implanting n+-type ions into substrate between each trench can be reversed in the embodiment without affecting subsequent steps.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: An ESD protection circuit (11) includes a low capacitance diode (26), a voltage divider, a trigger transistor (16), and an SCR. Reducing the capacitance associated with the diode (26) makes the ESD protection circuit particularly suitable for RF applications. To form a low capacitance diode, the parasitic junction capacitance of the diode (26) is hidden in a like-doped well; for example, an N+ cathode (54) of the diode (26) may be folded or formed partially in an N-well (53). Because the N-well (53) does not form a junction with the N+ cathode, the junction capacitance associated with the portion of the N+ well lying inside the N-well is hidden or canceled by the N-well (53), thereby reducing the overall capacitance of the diode (26).

Abstract: A method and structure providing a dual layer silicon gate film having a uniform boron distribution therein and an ordered, uniform grain structure. Rapid thermal annealing is used to cause the diffusion of boron from an originally doped film to an originally undoped film, resulting in a uniform boron distribution within the structure, thereby rendering the structure resistant to vertical and lateral diffusion of the boron during subsequent processing at elevated temperatures.

Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

Abstract: Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on the side surfaces of the gate electrode. Dopant atoms are subsequently introduce to transform the spacers into solid dopant sources. Dopant atoms are diffused from the spacers into the semiconductor substrate to form first doped regions.

Abstract: A method for making n-type semiconducting diamond by use of CVD in which n-type impurities are doped simultaneously with the deposition of diamond. As the n-type impurities, an Li compound and a B compound, both, are used at once. After doping, a diamond film thus obtained is etched to peel off its surface. The n-type semiconducting diamond is superior in specific resistivity, 10.sup.-2 .OMEGA.cm or less.

Abstract: A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

Abstract: Methods of forming semiconductor switching devices having trench-gate electrodes include the steps of implanting base region dopants of second conductivity type into a semiconductor substrate to define a preliminary base region therein. A step is then performed to form a trench having sidewalls which extend through the preliminary base region. A sacrificial insulating layer is then formed on the sidewalls of the trench while the implanted base region dopants are simultaneously diffused into the region of first conductivity type. The sacrificial insulating layer is then removed. Next, a gate electrode insulating layer is formed on the sidewalls and on a bottom of the trench. A gate electrode is then formed on the gate electrode insulating layer. Dopants of first conductivity type are then implanted into the semiconductor substrate to define a preliminary source region, which forms a P-N junction with the implanted base region dopants, and into the gate electrode to improve the conductivity thereof.

Abstract: A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors. One embodiment includes introducing a diffusion-retarding material, such as nitrogen, into the first gate electrode before the dopant is diffused into the respective channel regions, and without introducing a significant amount of the diffusion-retarding material into the second gate electrode. Advantageously, a single dopant implant can provide both threshold voltage values. The two threshold voltages may be chosen to provide various combinations of enhancement mode and depletion mode IGFETs.

Abstract: A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings.

Abstract: In semiconductor device fabrication process, an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. In the fabrication process, a gate electrode having a sidewall adjacent an active region is formed on a substrate and a doped spacer layer having a dopant disposed therein is formed over the substrate and gate electrode. A portion of the spacer layer is then removed to form a spacer on the sidewall of the gate electrode. The dopant in the spacer is diffused into the substrate to form a lightly-doped region in the active region of the substrate. The lightly-doped region may form an LDD region of an LDD structure.

Abstract: The device comprises a layer of silicon separated from a substrate by a layer of insulating material. A rib having an upper surface and two side surfaces is formed in the layer of silicon to provide a waveguide for the transmission of optical signals. A lateral doped junction is formed between the side surfaces of the rib such that an electrical signal can be applied across the junction to control the density of charge carriers across a substantial part of the cross-sectional area of the rib thereby actively altering the effective refractive index of the waveguide.

Abstract: A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings.

Abstract: A pn-diode of SiC has a first emitter layer part doped with first dopants having a low ionization energy and a second part designed as a grid and having portions extending vertically from above and past the junction between the drift layer and the first part and being laterally separated from each other by drift layer regions for forming a pn-junction by the first part and the drift layer adjacent such portions at a vertical distance from a lower end of the grid portions. The different parameters of the device are selected to allow a depletion of the drift layer in the blocking state form a continuous depleted region between the grid portions, to thereby screen off the high electric field at the pn-junction so that it will not be exposed to high electrical fields.

Abstract: A method for forming N- and P-channel transistors having shallow junctions in an integrated circuit device is described. A semiconductor substrate is provided having active regions separated from one another by isolation regions wherein there is a N-channel active region and a P-channel active region and wherein gate electrodes and associated lightly doped source and drain regions have been formed in each of the active regions. A layer of borosilicate glass is deposited overlying the semiconductor substrate. A photoresist mask is formed over the P-channel active region. The borosilicate glass layer is etched away where it is not covered by the photoresist mask thereby leaving the borosilicate glass layer only overlying the P-channel region. The photoresist mask is removed. A layer of phosphosilicate glass is deposited overlying the semiconductor substrate.

Abstract: An ultrahigh speed bipolar transistor has a base region which is formed from a P.sup.+ base polysilicon sidewall using a self-alignment method, and a base junction window which is formed in order to minimize the collector-base junction capacity. In the method for fabricating this transistor, an insulation layer of oxide silicon or nitrogen silicon is formed under the base polysilicon layer. Accordingly, impurities from the base polysilicon layer do not diffuse into the epitaxial layer during the diffusion process. Instead, the extrinsic base region is formed by the diffusion of impurities from the polysilicon sidewall which is connected to the base polysilicon layer. Therefore the length of the entire base region is shortened. Furthermore, the junction area between the collector region is also lowered. Thus, the collector-base junction capacity is decreased and a higher operating speed is obtained.

Abstract: A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.

Abstract: A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings.

Abstract: A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings.

Abstract: The instant invention teaches a novel method for fabricating silicon solar cells utilizing concentrated solar radiation. The solar radiation is concentrated by use of a solar furnace which is used to form a front surface junction and back-surface field in one processing step. The present invention also provides a method of making multicrystallline silicon from amorphous silicon. The invention also teaches a method of texturing the surface of a wafer by forming a porous silicon layer on the surface of a silicon substrate and a method of gettering impurities. Also contemplated by the invention are methods of surface passivation, forming novel solar cell structures, and hydrogen passivation.