Using Capping Layer Over Dopant Source To Prevent Out-diffusion Of Dopant Patents (Class 438/559)
  • Patent number: 11373871
    Abstract: Methods and apparatus for forming doped material layers in semiconductor devices using an integrated selective monolayer doping (SMLD) process. A concentration of dopant is deposited on a material layer using the SMLD process and the concentration of dopant is then annealed to diffuse the concentration of dopant into the material layer. The SMLD process conforms the concentration of dopant to a surface of the material layer and may be performed in a single CVD chamber. The SMLD process may also be repeated to further alter the diffusion parameters of the dopant into the material layer. The SMLD process is compatible with p-type dopant species and n-type dopant species.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: June 28, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Benjamin Colombeau, Wolfgang R. Aderhold, Andy Lo, Yi-Chiau Huang
  • Patent number: 11319332
    Abstract: A process including bringing a solid substrate in contact with a compound of general formula (I), (II), (III), or (IV) in the gaseous state where A is NR2 or OR with R being an alkyl group, an alkenyl group, an aryl group, or a silyl group, E is NR or O, n is 0, 1 or 2, m is 0, 1 or 2, and R? is hydrogen, an alkyl group, an alkenyl group, an aryl group, or a silyl group.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: May 3, 2022
    Assignees: BASF SE, Wayne State University
    Inventors: David Dominique Schweinfurth, Lukas Mayr, Sinja Verena Klenk, Sabine Weiguny, Charles Hartger Winter, Kyle Blakeney, Nilanka Weerathunga Sirikkathuge, Tharindu Malawara Arachchige Nimanthaka Karunaratne
  • Patent number: 11227996
    Abstract: A resistive element in an artificial neural network, the resistive element includes a Silicon-on-insulator (SOI) substrate, and a Silicon layer formed on the Silicon-on-insulator substrate. The Silicon layer includes dopants derived from a thin film dopant layer, and the thin film dopant layer includes a programmed amount of dopant including at least one of Boron and Phosphorus.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Matthew Warren Copel, James Bowler Hannon, Satoshi Oida
  • Patent number: 9640400
    Abstract: Embodiments described herein generally relate to doping of three dimensional (3D) structures on a substrate. In one embodiment, a conformal dopant containing film may be deposited over the 3D structures. Suitable dopants that may be incorporated in the film may include boron, phosphorous, and other suitable dopants. The film may be subsequently annealed to diffuse the dopants into the 3D structures.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: May 2, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rui Cheng, Abhijit Basu Mallick, Srinivas Gandikota, Pramit Manna
  • Patent number: 9218973
    Abstract: Provided are methods of doping substrates and making doped semiconductor features. An exemplary method includes providing a substrate having at least one feature having an aspect ratio; depositing a layer of dopants onto the substrate, the layer of dopants having a shape conforming to the at least one feature. A dielectric layer is deposited onto the layer of dopants, the dielectric layer having a shape conforming to the layer of dopants. The dielectric layer is annealed to diffuse the dopants into the substrate.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: December 22, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Aneesh Nainani, Mathew Abraham, Er-Xuan Ping
  • Publication number: 20150118834
    Abstract: The present invention includes methods directed to improved processes for producing a monolayer of sulfur or selenium on the surface of a semiconductor. As a surface layer, it functions to passivate the surface; if annealed, it provides a doping element.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 30, 2015
    Applicant: Sematech, Inc.
    Inventors: Wei-Yip LOH, Robert TIECKELMANN
  • Publication number: 20150111372
    Abstract: Provided are methods for preparing a doped silicon material. The methods include contacting a surface of a silicon material with a dopant solution comprising a dopant-containing compound selected from a phosphorus-containing compound and an arsenic-containing compound, to form a layer of dopant material on the surface; and diffusing the dopant into the silicon material, thereby forming the doped silicon material, wherein the doped silicon material has a sheet resistance (Rs) of less than or equal to 2,000 ?/sq.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Applicant: SEMATECH, INC.
    Inventors: Robert TIECKELMANN, Wei-Yip LOH, Rinus Tek Po LEE
  • Patent number: 9012316
    Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: April 21, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Patent number: 8980719
    Abstract: An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Yu-Lien Huang, De-Wei Yu
  • Patent number: 8912083
    Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: December 16, 2014
    Assignee: NanoGram Corporation
    Inventors: Guojun Liu, Uma Srinivasan, Shivkumar Chiruvolu
  • Patent number: 8871120
    Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Publication number: 20140264497
    Abstract: A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including depositing a dopant-containing layer, such that the surround gate prevents the dopant-containing layer from contacting the channel region of the FET, the dopant-containing layer including a dopant. The dopant then diffuses the dopant from the dopant-containing layer into at least one of the drain region and source region of the FET.
    Type: Application
    Filed: September 25, 2013
    Publication date: September 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Chung H. Lam, Jing Li
  • Patent number: 8836009
    Abstract: A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1 V 10-year extrapolated retention window at 125° C. and excellent 106 endurance at a fast 100 ?s and ±16 V program/erase. This is achieved using As+-implanted higher ? trapping layer with deep 5.1 eV work-function of As. In contrast, the un-implanted device only has a small 10-year retention window of 1.9 V at 125° C. A MoN—[SiO2—LaAlO3]—[Ge—HfON]—[LaAlO3—SiO2]—Si CTF device is also provided with record-thinnest 2.5-nm Equivalent-Si3N4-Thickness (ENT) trapping layer, large 4.4 V initial memory window, 3.2 V 10-year extrapolated retention window at 125° C., and 3.6 V endurance window at 106 cycles, under very fast 100 ?s and low ±16 V program/erase. These were achieved using Ge reaction with HfON trapping layer for better charge-trapping and retention.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: September 16, 2014
    Assignee: National Chiao Tung University
    Inventors: Albert Chin, Chun-Yang Tsai
  • Patent number: 8822317
    Abstract: A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8765617
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Inc.
    Inventor: Takeyoshi Masuda
  • Publication number: 20140179091
    Abstract: A method for forming ultra-shallow dopant regions in a substrate is provided. One embodiment includes depositing a first dopant layer containing a first dopant in direct contact with the substrate, patterning the first dopant layer, depositing a second dopant layer containing a second dopant in direct contact with the substrate adjacent the patterned first dopant layer, the first and second dopant layers containing an oxide, a nitride, or an oxynitride, where the first and second dopant layers contain an n-type dopant or a p-type dopant with the proviso that the first or second dopant layer do not contain the same dopant, and diffusing the first dopant from the first dopant layer into the substrate to form a first ultra-shallow dopant region in the substrate, and diffusing the second dopant from the second dopant layer into the substrate to form a second ultra-shallow dopant region in the substrate.
    Type: Application
    Filed: October 29, 2013
    Publication date: June 26, 2014
    Applicant: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 8728922
    Abstract: A method for producing monocrystalline n-silicon solar cells having a rear-side passivated p+ emitter and rear-side, spatially separate heavily doped n++-base regions near the surface, as well as an interdigitated rear-side contact finger structure, which is in conductive connection with the p+-emitter regions and the n++-base regions. An aluminum thin layer or an aluminum-containing thin layer is first deposited on the rear side of the n-silicon wafer, and the thin layer is subsequently structured so that openings are obtained in the region of the future base contacts. In a further process step, the aluminum is then diffused into the n-silicon wafer in order to form a structured emitter layer.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: May 20, 2014
    Assignee: SolarWorld Industries-Thueringen GmbH
    Inventors: Hans-Joachim Krokoszinski, Jan Lossen
  • Publication number: 20140004689
    Abstract: Provided are methods of doping substrates and making doped semiconductor features. An exemplary method includes providing a substrate having at least one feature having an aspect ratio; depositing a layer of dopants onto the substrate, the layer of dopants having a shape conforming to the at least one feature. A dielectric layer is deposited onto the layer of dopants, the dielectric layer having a shape conforming to the layer of dopants. The dielectric layer is annealed to diffuse the dopants into the substrate.
    Type: Application
    Filed: June 13, 2013
    Publication date: January 2, 2014
    Inventors: Aneesh Nainani, Mathew Abraham, Er-Xuan Ping
  • Patent number: 8580664
    Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of boron amide precursor or an organoboron precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: November 12, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Publication number: 20130295754
    Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.
    Type: Application
    Filed: June 21, 2013
    Publication date: November 7, 2013
    Inventors: Ali Afzali-Ardakani, Damon Farmer, Lidija Sekaric
  • Patent number: 8569158
    Abstract: A method for forming an ultra-shallow dopant region in a substrate is provided. In one embodiment, the method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 29, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 8563403
    Abstract: A method includes forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer; forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer; bonding the first bonding layer of first IC device to the second bonding layer of second IC device; thinning a backside of the first IC device so as to expose the alignment via; and using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Spyridon Skordas, Richard P. Volant, Kevin R. Winstel
  • Patent number: 8561003
    Abstract: A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: October 15, 2013
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Victor Moroz, Deepak Sherlekar
  • Patent number: 8501605
    Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of doping a substrate may include forming a dopant region on a substrate by implanting one or more dopant elements into the dopant region of the substrate using a plasma doping process; forming a cap layer atop the dopant region; annealing the dopant region after forming the cap layer; and removing the cap layer after annealing the dopant region.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Santhanam, Martin A. Hilkene, Manoj Vellaikal, Mark R. Lee, Matthew D. Scotney-Castle, Peter I. Porshnev
  • Publication number: 20120302050
    Abstract: Disclosed herein is a method of manufacturing a semiconductor device. The method comprises forming a first silicon film on a semiconductor substrate, forming a second silicon film on the first silicon film, forming a third silicon film on the second silicon film, and forming a first diffusion barrier film on the third silicon film. The method further comprises performing a thermal treatment to diffuse an impurity included in the second silicon film into at least the first silicon film and the semiconductor substrate, respectively.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 29, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Takayuki MATSUI
  • Patent number: 8293553
    Abstract: In a method for producing at least at least one area (8) with reduced electrical conductivity within an electrically conductive III-V semiconductor layer (3), a ZnO layer (1) is applied to the area (8) of the semiconductor layer (3) and subsequently annealed at a temperature preferably between 300° C. and 500° C. The ZnO layer (1) is preferably deposited on the III-V semiconductor layer (3) at a temperature of less than 150° C., preferably at a temperature greater than or equal to 25° C. and less than or equal to 120° C. The area (8) with reduced electrical conductivity is preferably located in a radiation emitting optoelectronic device between the active zone (4) and a connecting contact (7) in order to reduce current injection into the areas of the active zone (4) located opposite to the connecting contact (7).
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: October 23, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Stefan Illek, Wilhelm Stein, Robert Walter, Ralph Wirth
  • Publication number: 20120252197
    Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of boron amide precursor or an organoboron precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Publication number: 20120193769
    Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.
    Type: Application
    Filed: May 23, 2011
    Publication date: August 2, 2012
    Inventors: Guojun Liu, Uma Srinivasan, Shivkumar Chiruvolu
  • Publication number: 20120187539
    Abstract: A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JOEL P. DE SOUZA, Marinus Hopstaken, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 8222129
    Abstract: A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: July 17, 2012
    Assignees: Samsung Electronics Co., Ltd., Samsung SDI Co., Ltd.
    Inventors: Young Su Kim, Doo-Youl Lee
  • Patent number: 8163639
    Abstract: A method of fabricating a photo diode includes sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a semiconductor substrate; forming a doped oxide film, including impurities of the second conductivity type, on the second epitaxial layer; forming a silicon nitride film on the oxide film; and patterning the oxide film and the silicon nitride film to sequentially form an oxide film pattern of the second conductivity type and a silicon nitride film pattern, respectively. The second conductivity type impurities are diffused from the oxide film pattern into the second epitaxial layer using a heat diffusion process to form a doped shallow junction layer of the second conductivity type, which converts the oxide film pattern into a non-conductive oxide film pattern.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kye-wong Maeng, Sung-ryoul Bae
  • Patent number: 8124502
    Abstract: A semiconductor device manufacturing method is provided, including: providing a semiconductor substrate, forming on the semiconductor substrate a layer including a semiconductor compound and a dope additive, and thereafter forming an emitter region and gettering impurities by annealing the semiconductor substrate including the layer.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: February 28, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Rafel Ferre i Tomas
  • Publication number: 20120009770
    Abstract: A method of forming the conductive lines of a semiconductor memory device comprises forming a first polysilicon layer over an underlying layer, forming first polysilicon patterns by patterning the first polysilicon layer, filling the space between the first polysilicon patterns with an insulating layer, etching a top portion of the first polysilicon patterns to form recess regions, forming spacers on the sidewalls of the recess regions, filling the recess regions with a second polysilicon layer to form second polysilicon patterns, and performing a metal silicidation process to convert the second polysilicon patterns to metal silicide patterns.
    Type: Application
    Filed: December 17, 2010
    Publication date: January 12, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Won Sic Woo
  • Publication number: 20110223751
    Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 15, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Damon B. Farmer, Lidija Sekaric
  • Patent number: 7989329
    Abstract: A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 2, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Kenneth S. Collins, Biagio Gallo, Hiroji Hanawa, Majeed A. Foad, Martin A. Hilkene, Kartik Santhanam, Matthew D. Scotney-Castle
  • Patent number: 7947585
    Abstract: Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: May 24, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: In Bok Baek, Seong Jae Lee, Jong Heon Yang, Chang Geun Ahn, Han Young Yu, Ki Ju Im
  • Patent number: 7754551
    Abstract: This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-? CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: July 13, 2010
    Assignee: National Chiao Tung University
    Inventor: Albert Chin
  • Patent number: 7737014
    Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Frederick William Buehrer, Dureseti Chidambarrao, Bruce B. Doris, Hsiang-Jen Huang, Haining Yang
  • Patent number: 7732311
    Abstract: In a method of manufacturing a semiconductor device, a conductive layer pattern may be formed on a substrate. An oxide layer may be formed on the substrate to cover the conductive layer pattern. A diffusion barrier layer may be formed by treating the oxide layer to increase an energy required for a diffusion of impurities. An impurity region may be formed on the substrate by implanting impurities into the conductive layer pattern and a portion of the substrate adjacent to the conductive layer pattern, through the diffusion barrier. The impurities in the conductive layer pattern and the impurity region may be prevented or reduced from diffusing, and therefore, the semiconductor device may have improved performance.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: June 8, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Joo-Won Lee, Tae-Gyun Kim
  • Patent number: 7709365
    Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Haensch, Terence B. Hook, Louis C. Hsu, Rajiv V. Joshi, Werner Rausch
  • Patent number: 7696037
    Abstract: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventor: Anthony C. Speranza
  • Patent number: 7282428
    Abstract: In order to form a p-region in an InP-based photodiode, zinc doping must be performed. Due to the current trend toward the implementation of larger-sized InP wafers, there is a need for a solid phase diffusion method in which a ZnO thin film is applied to an epitaxial wafer, the wafer is heated, such that zinc is diffused from the ZnO thin film into the InP epitaxial layers. A mask having an upper layer made of a-Si is used as a diffusion mask. Since a-Si does not dissolve in hydrofluoric acid, the a-Si remains without dissolving when the ZnO is removed with hydrofluoric acid. Since the a-Si film remains, the edge of the pn junction is not exposed. The pn junction does not become degraded because the edge of the pn junction is covered and protected by the diffusion mask at all times.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: October 16, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiroshi Inada
  • Patent number: 7109100
    Abstract: To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in yield and a method of producing the same. The device has a channel layer 16 formed on a substrate 12, a diffusion stop layer 17 formed on the top surface of the channel layer 16, a diffusion layer 18 formed on the top surface of the diffusion stop layer, and a doping region 25 formed adjoining the diffusion stop layer 17 at least at part of the diffusion layer 18 and having an impurity diffused in it, the diffusion stop layer 17 having a slower diffusion rate of the impurity than the diffusion rate of the diffusion layer 18 and stopping diffusion of the impurity from the diffusion layer 18.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: September 19, 2006
    Assignee: Sony Corporation
    Inventor: Mitsuhiro Nakamura
  • Patent number: 6930007
    Abstract: The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 16, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Shashank Ekbote, Rajesh Khamankar, Shaoping Tang, Freidoon Mehrad
  • Patent number: 6893947
    Abstract: A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: May 17, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marino J. Martinez, Ernest Schirmann, Olin L. Hartin, Colby G. Rampley, Mariam G. Sadaka, Charles E. Weitzel, Julio Costa
  • Patent number: 6806173
    Abstract: A method is proposed for producing semiconductor components, in which at least one doped region is introduced in a wafer, a solid glass layer provided with dopant being applied on at least one of the two sides of a semiconductor wafer, in another step, the wafer being heated to high temperatures so that the dopant from the glass layer penetrates deep into the wafer to produce the at least one doped region; and in a further step, the glass layer being removed. The method is used for producing homogeneous, heavily doped regions, it also being possible to introduce these regions in the wafer on both sides and for the regions to be of different doping type.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: October 19, 2004
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Barbara Will, Helga Uebbing, Roland Riekert, Christian Adamski
  • Patent number: 6743704
    Abstract: A CMOSFET in which a p-type gate electrode and an n-type gate electrode are formed on a silicon substrate. The p-type gate electrode includes, in order, a p-type polycrystalline silicon layer and a tungsten silicide layer. The n-type gate electrode includes, in order, an n-type polycrystaline silicon layer and a tungsten silicide layer. A carbon-containing polycrystalline silicon layer, which is an impurity thermal diffusion prevention layer to suppress the interdiffusion of impurities, is provided between the p-type polycrystalline silicon layer and the tungsten silicide layer.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: June 1, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Masashi Takahashi
  • Patent number: 6723587
    Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: April 20, 2004
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Won-Ju Cho, Jong-Heon Yang, Moon-Gyu Jang, Seong-Jae Lee, Kyoung-Wan Park, Ki-Ju Im, Ji-Hun Oh
  • Patent number: 6695903
    Abstract: The invention relates to novel boron, phosphorus or boron-aluminium dopant pastes for the production of p, p+ and n, n+ regions in monocrystalline and polycrystalline Si wafers, and of corresponding pastes for use as masking pastes in semiconductor fabrication, power electronics or in photovoltaic applications.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: February 24, 2004
    Assignee: Merck Patent GmbH
    Inventors: Armin Kübelbeck, Claudia Zielinski, Lilia Heider, Werner Stockum
  • Patent number: 6642119
    Abstract: The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: November 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mario M. Pelella, Shankar Sinha, Simon S. Chan