From Solid Dopant Source In Contact With Semiconductor Region Patents (Class 438/558)
  • Patent number: 10504732
    Abstract: A diffusion agent composition that can be evenly applied onto the whole area of an inner surface of the fine voids, whereby boron can be well and uniformly diffused into the semiconductor substrate even by heating at a low temperature, and a method for manufacturing a semiconductor substrate using the diffusion agent composition. In a diffusion agent composition including an impurity diffusion component, the impurity diffusion component, which can be applied onto a surface of a semiconductor substrate to form a diffusion layer, and which is a boron compound including a nitrogen atom, is used.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 10, 2019
    Assignee: TOKYO OHKA KOGYO CO, LTD.
    Inventors: Yoshihiro Sawada, Yu Takahashi
  • Patent number: 10446698
    Abstract: A photoelectric conversion device includes, on one principal surface of a semiconductor substrate, a first conductivity-type region, a second conductivity-type region, and a boundary region which is in contact with each of the first conductivity-type region and the second conductivity-type region to separate these two regions. A first conductivity-type semiconductor layer is disposed over the entire first conductivity-type region and extending over the boundary region. A second conductivity-type semiconductor layer is disposed over the entire second conductivity-type region and extending over the boundary region. An insulating layer is disposed over the entire boundary region. A first electrode is disposed over the entire first conductivity-type region and extending over the boundary region, and a second electrode is disposed over the second conductivity-type region.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 15, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Katsunori Konishi, Kunta Yoshikawa, Hayato Kawasaki, Kunihiro Nakano
  • Patent number: 10145011
    Abstract: A system for depositing a layer on a substrate includes a processing chamber including a gas inlet, a plurality of gas flow controllers connected in fluid communication with a gas supply source, a gas distribution plate disposed between the plurality of gas flow controllers and the gas inlet, and a gas injection cap connected in fluid communication between the plurality of gas flow controllers and the gas distribution plate. The gas distribution plate defines a plurality of holes, and the gas injection cap defines a plurality of gas flow passages, each extending from an inlet connected to one of the gas flow controllers to an outlet connected in fluid communication with at least one of the holes in the gas distribution plate. Each of the gas flow controllers is disposed proximate to the gas injection cap.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 4, 2018
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Arash Abedijaberi, John A. Pitney, Shawn George Thomas
  • Patent number: 9870925
    Abstract: A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 16, 2018
    Inventor: Anatoly Feygenson
  • Patent number: 9608079
    Abstract: A semiconductor device includes a source finger electrode coupled to a source region in a semiconductor die, a drain finger electrode coupled to a drain region in the semiconductor die, where the source finger electrode includes at least one isolated segment and a main segment having a first portion and a second portion narrower than the first portion, whereby the source finger electrode reduces a drain-to-source capacitance of the semiconductor device. A common source rail is electrically coupled to the at least one isolated segment and the main segment of the source finger electrode. The drain finger electrode includes at least one isolated segment and a main segment having a first portion and a second portion narrower than the first portion. A common drain rail is electrically coupled to the at least one isolated segment and the main segment of the drain finger electrode.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: March 28, 2017
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Roda Kanawati
  • Patent number: 9577050
    Abstract: Provided is a method for manufacturing a semiconductor device. Also provided are: a semiconductor device which can be obtained by the method; and a dispersion that can be used in the method. A method for manufacturing a semiconductor device (500a) of the present invention comprises the steps (a)-(c) described below and is characterized in that the crystal orientation of a first dopant implanted layer (52) is the same as the crystal orientation of a semiconductor layer or a base (10) that is formed of a semiconductor element. (a) A dispersion which contains doped particles is applied to a specific part of a layer or a base. (b) An unsintered dopant implanted layer is obtained by drying the applied dispersion. (c) The specific part of the layer or the base is doped with a p-type or n-type dopant by irradiating the unsintered dopant implanted layer with light, and the unsintered dopant implanted layer is sintered, thereby obtaining a dopant implanted layer that is integrated with the layer or the base.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: February 21, 2017
    Assignee: TEIJIN LIMITED
    Inventors: Yuka Tomizawa, Yoshinori Ikeda, Tetsuya Imamura
  • Patent number: 9478423
    Abstract: A method of vapor-diffusing impurities into a diffusion region of a target substrate to be processed using a dummy substrate is provided. The method includes loading the target substrate and the dummy substrate in a substrate loading jig, accommodating the substrate loading jig loaded with the target substrate and the dummy substrate in a processing chamber of a processing apparatus, and vapor-diffusing impurities into the diffusion region of the target substrate in the processing chamber having the accommodated substrate loading jig. The vapor-diffused impurities are boron, an outer surface of the dummy substrate includes a material having properties not allowing boron adsorption.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: October 25, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuya Takahashi, Yoshikazu Furusawa, Mitsuhiro Okada
  • Patent number: 9368352
    Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 14, 2016
    Assignee: ASM INTERNATIONAL N.V.
    Inventors: Noboru Takamure, Atsuki Fukazawa, Hideaki Fukuda, Antti Niskanen, Suvi Haukka, Ryu Nakano, Kunitoshi Namba
  • Patent number: 9318318
    Abstract: A method for fabricating a semiconductor device includes receiving a gated finned substrate comprising an isolation layer with a semiconductor fin formed thereon and a gate formed over the semiconductor fin, depositing an atomic layer of dopant on a portion of the semiconductor fin that is laterally adjacent to the gate, forming a lateral spacer on a sidewall of the gate and above a gate extension portion of the atomic layer of dopant, and epitaxially growing a raised source or drain region on the semiconductor fin, that is laterally adjacent to the lateral spacer, from the atomic layer of dopant. The method may also include conducting a low temperature annealing process to diffuse the atomic layer of dopant to the raised source or drain region of the semiconductor fin. A corresponding apparatus is also disclosed herein.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: April 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Effendi Leobandung, Dae-Gyu Park, Min Yang
  • Patent number: 9299564
    Abstract: Various methods for implanting dopant ions into a three dimensional feature of a semiconductor wafer are disclosed. The implant temperature may be varied to insure that the three dimensional feature, after implant, has a crystalline inner core, which is surrounded by an amorphized surface layer. The crystalline core provides a template from which the crystalline structure for the rest of the feature can be regrown. In some embodiments, the implant energy and the implant temperature may each be modified to achieve the desired crystalline inner core with the surrounding amorphized surface layer.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: March 29, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Andrew M. Waite, Stanislav S. Todorov
  • Patent number: 9171722
    Abstract: A method of vapor-diffusing impurities into a diffusion region of a target substrate to be processed using a dummy substrate is provided. The method includes loading the target substrate and the dummy substrate in a substrate loading jig, accommodating the substrate loading jig loaded with the target substrate and the dummy substrate in a processing chamber of a processing apparatus, and vapor-diffusing impurities into the diffusion region of the target substrate in the processing chamber having the accommodated substrate loading jig. The vapor-diffused impurities are boron, an outer surface of the dummy substrate includes a material having properties not allowing boron adsorption.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: October 27, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuya Takahashi, Yoshikazu Furusawa, Mitsuhiro Okada
  • Patent number: 9093598
    Abstract: A method is provided for the simultaneous diffusion of dopants of different types on respective sides of a solar cell wafer in a single stage process. The dopants are applied to respective sides of the wafer in wet chemical form preferably by pad printing. The doping materials can be applied to the entire wafer surface or effective area thereof, or can be applied in a pattern to suit the intended solar cell configuration. In a typical embodiment, the dopants are boron and phosphorus.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: July 28, 2015
    Assignee: BTU International, Inc.
    Inventors: Paul J. Richter, Frank Bottari
  • Patent number: 9048261
    Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
  • Publication number: 20150147875
    Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.
    Type: Application
    Filed: September 30, 2014
    Publication date: May 28, 2015
    Inventors: Noboru Takamure, Atsuki Fukazawa, Hideaki Fukuda, Antti Niskanen, Suvi Haukka, Ryu Nakano, Kunitoshi Namba
  • Publication number: 20150132931
    Abstract: A method for thermal processing of a silicon substrate wherein first a silicon substrate is heated to an idle load temperature in the range of approximately 700° to 900° C. The silicon substrate is then heated to a temperature in the range of approximately 975° to 1200° C. in less than approximately 20 minutes. After thermal processing, the silicon substrate is cooled to an idle unload temperature in the range of approximately 700° to 900° C. in less than approximately 20 minutes.
    Type: Application
    Filed: July 1, 2014
    Publication date: May 14, 2015
    Inventors: Pawan Kapur, Mehrdad M. Moslehi, Sean M. Seutter, Mohammed Islam, Anand Deshpande
  • Publication number: 20150118833
    Abstract: A method of depositing a contact layer material includes sputtering a target including a metal and a dopant. The contact layer material is conductive and may be used in a transistor device to connect a conductive region, such as a source region or a drain region of metal-oxide semiconductor field effect transistor, to a contact plug. The contact plug is used to connect the source/drain region formed in a semiconducting substrate to metal wiring layers formed above the gate level of a semiconductor device. The resulting contact layer may be a metal silicide including the dopant. In some embodiments, the sputtered metal may be nickel and the dopant may be phosphorous and the resulting contact layer a nickel silicide doped with phosphorous. Embodiments described, in general, can provide reduced contact resistance and thus improved performance in semiconductor devices.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Inventors: Jianxin LEI, Jothilingam RAMALINGAM, Chi-Nung NI
  • Patent number: 9012316
    Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: April 21, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Patent number: 8987073
    Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
  • Publication number: 20150072510
    Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.
    Type: Application
    Filed: November 15, 2014
    Publication date: March 12, 2015
    Inventor: Robert D Clark
  • Patent number: 8975662
    Abstract: Source zones of a first conductivity type and body zones of a second conductivity type are formed in a semiconductor die. The source zones directly adjoin a first surface of the semiconductor die. A dielectric layer adjoins the first surface. Polysilicon plugs extend through the dielectric layer and are electrically connected to the source and the body zones. An impurity source containing at least one metallic recombination element is provided in contact with deposited polycrystalline silicon material forming the polysilicon plugs and distant to the semiconductor die. Atoms of the metallic recombination element, for example platinum atoms, may be diffused out from the impurity source into the semiconductor die to reliably reduce the reverse recovery charge.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Ralf Siemieniec, Oliver Blank
  • Patent number: 8975717
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 10, 2015
    Assignee: SunPower Corporation
    Inventor: David D. Smith
  • Patent number: 8969186
    Abstract: A method for manufacturing a photovoltaic cell with a selective emitter, including the steps of: depositing an antireflection layer including n-type dopants on an n- or p-type silicon substrate, said deposition being, performed in the presence of a chemical compound that accelerates the diffusion of n-type dopant atoms in said substrate; overdoping at least one area of the substrate to form at least one n++ overdoped emitter by local diffusion of the n dopants of at least one area of the antireflection layer; depositing at least one n-type conductive material on the at least one n++ overdoped emitter; and at least one p-type conductive material on the surface of the substrate opposite to that including the antireflection layer; forming the n contacts and the p contacts simultaneously to the forming of an n+ emitter by an anneal capable of diffusing within the substrate n dopants from the antireflection layer.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: March 3, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Bertrand Paviet-Salomon, Samuel Gall, Sylvain Manuel
  • Patent number: 8951850
    Abstract: A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Publication number: 20150037967
    Abstract: Methods of processing a silicon wafer for an electronic circuit, substrates for an electronic circuit, and device manufacturing methods are disclosed. According to an embodiment the method of processing a silicon wafer comprises impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: said impregnating step is performed in such a way that the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1.
    Type: Application
    Filed: April 4, 2012
    Publication date: February 5, 2015
    Inventors: Peter Wilshaw, Kanad Mallik, Doug Jordan, Peter Ashburn
  • Publication number: 20150017794
    Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.
    Type: Application
    Filed: February 19, 2014
    Publication date: January 15, 2015
    Applicant: ASM International. N.V.
    Inventors: Noboru Takamure, Atsuki Fukazawa, Hideaki Fukuda, Antti Niskanen, Suvi Haukka, Ryu Nakano, Kunitoshi Namba
  • Patent number: 8912083
    Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: December 16, 2014
    Assignee: NanoGram Corporation
    Inventors: Guojun Liu, Uma Srinivasan, Shivkumar Chiruvolu
  • Patent number: 8912038
    Abstract: Methods of forming emitters for back-contact solar cells are described. In one embodiment, a method includes forming a first solid-state dopant source above a substrate. The first solid-state dopant source includes a plurality of regions separated by gaps. Regions of a second solid-state dopant source are formed above the substrate by printing.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: December 16, 2014
    Assignee: SunPower Corporation
    Inventors: Bo Li, Peter J. Cousins, David D. Smith
  • Patent number: 8895420
    Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 25, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Daniel-Camille Bensahel, Yves Morand
  • Patent number: 8877620
    Abstract: A method for forming ultra-shallow dopant regions in a substrate is provided. One embodiment includes depositing a first dopant layer containing a first dopant in direct contact with the substrate, patterning the first dopant layer, depositing a second dopant layer containing a second dopant in direct contact with the substrate adjacent the patterned first dopant layer, the first and second dopant layers containing an oxide, a nitride, or an oxynitride, where the first and second dopant layers contain an n-type dopant or a p-type dopant with the proviso that the first or second dopant layer do not contain the same dopant, and diffusing the first dopant from the first dopant layer into the substrate to form a first ultra-shallow dopant region in the substrate, and diffusing the second dopant from the second dopant layer into the substrate to form a second ultra-shallow dopant region in the substrate.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: November 4, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 8871620
    Abstract: Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of SixGe1-x passivated by amorphous SiyGe1-y:H.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Publication number: 20140306347
    Abstract: A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a pitch. Each of the at least one of recesses and openings has a lateral width, wherein at least one of the pitch and the lateral width varies in a lateral direction. The plurality of the at least one of recesses and openings defines a given region in the insulation layer. The insulation layer having the plurality of the at least one of the recesses and openings is tempered at elevated temperatures so that the insulation layer at least partially diffluences to provide the insulation layer with a laterally varying thickness at least in the given region.
    Type: Application
    Filed: April 12, 2013
    Publication date: October 16, 2014
    Inventor: INFINEON TECHNOLOGIES AG
  • Patent number: 8846512
    Abstract: Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a mask.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jaydeb Goswami
  • Patent number: 8846511
    Abstract: One illustrative method disclosed herein includes forming an initial nanowire structure having an initial cross-sectional size, performing a doping diffusion process to form an N-type doped region in the initial nanowire structure and performing an etching process to remove at least a portion of the doped region and thereby define a final nanowire structure having a final cross-sectional size, wherein the final cross-sectional size is smaller than the initial cross-sectional size.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas V. LiCausi, Jeremy A. Wahl
  • Patent number: 8835264
    Abstract: A substrate having thereon an epitaxial layer is provided. A hard mask having an opening is formed on the epitaxial layer. A sidewall spacer is formed within the opening. A first trench is etched into the epitaxial layer through the opening. A dopant source layer is formed on the surface of the first trench. The dopants are driven into the epitaxial layer to form a doped region within the first trench. The doped region includes a first region adjacent to the surface of the first trench and a second region farther from the surface. The entire dopant source layer and the spacer are removed. A sacrificial layer is then filled into the first trench. The sacrificial layer and the epitaxial layer within the first region are etched away to form a second trench.
    Type: Grant
    Filed: May 26, 2013
    Date of Patent: September 16, 2014
    Assignee: Anpec Electronics Corporation
    Inventor: Yung-Fa Lin
  • Patent number: 8822317
    Abstract: A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8822318
    Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: September 2, 2014
    Assignee: Inernational Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Damon Farmer, Lidija Sekaric
  • Patent number: 8802486
    Abstract: Methods of forming emitters for back-contact solar cells are described. In one embodiment, a method includes forming a first solid-state dopant source above a substrate. The first solid-state dopant source includes a plurality of regions separated by gaps. Regions of a second solid-state dopant source are formed above the substrate by printing.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 12, 2014
    Assignee: SunPower Corporation
    Inventors: Bo Li, Peter J. Cousins, David D. Smith
  • Patent number: 8790957
    Abstract: Methods of fabricating back-contact solar cells and devices thereof are described. A method of fabricating a back-contact solar cell includes forming an N-type dopant source layer and a P-type dopant source layer above a material layer disposed above a substrate. The N-type dopant source layer is spaced apart from the P-type dopant source layer. The N-type dopant source layer and the P-type dopant source layer are heated. Subsequently, a trench is formed in the material layer, between the N-type and P-type dopant source layers.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 29, 2014
    Assignee: SunPower Corporation
    Inventors: Bo Li, David Smith, Peter Cousins
  • Patent number: 8778787
    Abstract: Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: July 15, 2014
    Assignee: SunPower Corporation
    Inventor: Jane Manning
  • Patent number: 8772143
    Abstract: A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8772068
    Abstract: A method of forming contacts on a surface emitter of a silicon solar cell is provided. In the method an n-type diffusion of a surface is performed to form a doped emitter surface layer that has a sheet resistance of 10-40 ?/?. The emitter surface layer is then etched back to increase the sheet resistance of the emitter surface layer. Finally the surface is selectively plated. A method of fabrication of a silicon solar cell includes performing a front surface emitter diffusion of n-type dopant and then performing a dielectric deposition on the front surface by PECVD. The dielectric deposition comprises: a. growth of a thin silicon oxide; b. PECVD deposition of silicon nitride to achieve a silicon nitride. The silicon is then annealed to drive hydrogen from the silicon nitride layer into the silicon to passivate the silicon.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: July 8, 2014
    Assignee: Newsouth Innovations PTY Limited
    Inventors: Stuart Ross Wenham, Budi Santoso Tjahjono, Nicole Bianca Kuepper, Alison Joan Lennon
  • Patent number: 8772910
    Abstract: A method and an apparatus for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Bhupesh Chandra, George Stojan Tulevski
  • Patent number: 8772141
    Abstract: A method for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Bhupesh Chandra, George Stojan Tulevski
  • Patent number: 8728922
    Abstract: A method for producing monocrystalline n-silicon solar cells having a rear-side passivated p+ emitter and rear-side, spatially separate heavily doped n++-base regions near the surface, as well as an interdigitated rear-side contact finger structure, which is in conductive connection with the p+-emitter regions and the n++-base regions. An aluminum thin layer or an aluminum-containing thin layer is first deposited on the rear side of the n-silicon wafer, and the thin layer is subsequently structured so that openings are obtained in the region of the future base contacts. In a further process step, the aluminum is then diffused into the n-silicon wafer in order to form a structured emitter layer.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: May 20, 2014
    Assignee: SolarWorld Industries-Thueringen GmbH
    Inventors: Hans-Joachim Krokoszinski, Jan Lossen
  • Patent number: 8703593
    Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
  • Publication number: 20140094025
    Abstract: A method for processing a semiconductor assembly is presented. The method includes: (a) contacting at least a portion of a semiconductor assembly with a chalcogen source, wherein the semiconductor assembly comprises a semiconductor layer comprising a semiconductor material disposed on a support; (b) introducing a chalcogen from the chalcogen source into at least a portion of the semiconductor material; and (c) disposing a window layer on the semiconductor layer after the step (b).
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Bastiaan Arie Korevaar, Faisal Razi Ahmad
  • Patent number: 8673673
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. An interrupted trench structure separates the P-type doped region from the N-type doped region in some locations but allows the P-type doped region and the N-type doped region to touch in other locations. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. Among other advantages, the resulting solar cell structure allows for increased efficiency while having a relatively low reverse breakdown voltage.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: March 18, 2014
    Assignee: SunPower Corporation
    Inventors: Denis De Ceuster, Peter John Cousins, David D. Smith
  • Publication number: 20140073122
    Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.
    Type: Application
    Filed: November 12, 2013
    Publication date: March 13, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Robert D Clark
  • Patent number: 8659110
    Abstract: A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Devendra Sadana, Davood Shahrjerdi, Norma E. Sosa Cortes, Brent A. Wacaser
  • Patent number: 8647939
    Abstract: A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pranita Kerber, Ali Khakifirooz, Douglas C. La Tulipe, Jr.