Abstract: The disclosed technology includes systems, devices, and methods associate with producing an organic semiconductor film having electrical dopant molecules distributed to a controlled depth. In an example implementation, a semiconductor device is provided. The semiconductor device can include a first substrate and an organic semiconductor film disposed on the first substrate. The organic semiconductor film includes a first region characterized by electrical dopant molecules distributed to a controlled depth with respect to a first surface of the organic semiconductor film. The semiconductor device further can include an electrode in contact with at least a portion of the first region of the organic semiconductor film.

Abstract: [Object] To provide a method for manufacturing a solar cell element including a semiconductor substrate that includes a high-concentration dopant layer located near the surface of the semiconductor substrate and a low-concentration dopant layer located more inside the semiconductor substrate than the high-concentration dopant layer. [Solving Means] A method includes heating a semiconductor substrate having a first conductivity type in a first atmosphere which contains a dopant having a second conductivity type and which has a first dopant concentration; heating in a second atmosphere the semiconductor substrate heated in the first atmosphere, the second atmosphere having a second dopant concentration less than the first dopant concentration; and heating in a third atmosphere the semiconductor substrate heated in the second atmosphere, the third atmosphere having a third dopant concentration greater than the second dopant concentration.

Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.

Abstract: A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.

Abstract: Methods of improving the anti-reflection properties of one or more dielectric layers and reducing surface recombination of generated carriers of a solar cell are disclosed. In some embodiments, dopants are introduced into the dielectric layers to improve their anti-reflection properties. In other embodiments, species are introduced into the dielectric layers to create electrical fields which repel the minority carriers away from the surface and toward the contacts. In another embodiment, mobiles species are introduced to the anti-reflective coating, which cause carrier to be repelled from the surface of the solar cell. By creating a barrier at the surface of the solar cell, undesired recombination at the surface may be reduced.

Abstract: A method of forming the conductive lines of a semiconductor memory device comprises forming a first polysilicon layer over an underlying layer, forming first polysilicon patterns by patterning the first polysilicon layer, filling the space between the first polysilicon patterns with an insulating layer, etching a top portion of the first polysilicon patterns to form recess regions, forming spacers on the sidewalls of the recess regions, filling the recess regions with a second polysilicon layer to form second polysilicon patterns, and performing a metal silicidation process to convert the second polysilicon patterns to metal silicide patterns.

Abstract: The method described herein enables the introduction of external impurities into Silicon Carbide (SiC) to be conducted at a temperature between 1150-1400° C. Advantages include: a) low temperature diffusion procedure with greater control of the doping process, b) prevent roughness of SiC surface, c) less surface defects and d) better device performance and higher yield. The method described herein involves depositing a ceramic layer that contains the desired impurity and a certain element such as oxygen (in the form of oxide), or other elements/compounds that draw out the silicon and carbon atoms from the surface region of the SiC leaving behind carbon and silicon vacancies which then allow the external impurity to diffuse into the SiC more easily. In another embodiment, the deposited layer also has carbon atoms that discourage carbon from escaping from the SiC, thus generating a surface region of excess carbon in addition to the silicon vacancies.

Abstract: A semiconductor device has a semiconductor body with a semiconductor device structure including at least a first electrode and a second electrode. Between the two electrodes, a drift region is arranged, the drift region including charge compensation zones and drift zones arranged substantially parallel to one another. At least one charge carrier storage region which is at least partially free of charge compensation zones is arranged in the semiconductor body.

Abstract: Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

Abstract: A method for forming a high voltage semiconductor power device comprises providing a first dopant source of first conductivity on an upper surface of a substrate of second conductivity. A second dopant source of first conductivity is provided on a lower surface of the substrate. The substrate is annealed for a first given time to drive the dopants from the first and second dopants sources into the substrate. The first and second dopant sources are removed from the upper and lower surfaces of the substrate. The substrate is annealed for a second given time to homogenize dopant concentration within the substrate after the first and second dopant sources have been removed, where the annealing the substrate for the second given time results in out-diffusion of dopants proximate the upper and lower surfaces of the substrate.

Abstract: The present invention is a method for fabricating a memory device. In one embodiment, an impurity concentration is created in a semiconductor substrate of a memory device. An annealing process is then performed. A second impurity concentration is created in a second region of the semiconductor substrate and a second annealing process is performed.

Abstract: A first insulating film is formed on a base substrate, then a second insulating film is formed on the first insulating film, the second insulating film having a relative permittivity higher than that of the first insulating film. A gate electrode is formed on the second insulating film. The second insulating film forming includes first to sixth steps, and a cycle consisting of the first to sixth steps is repeated.

Abstract: A highly localized diffusion barrier is incorporated into a polysilicon line to allow the doping of the polysilicon layer without sacrificing an underlying material layer. The diffusion barrier is formed by depositing a thin polysilicon layer and exposing the layer to a nitrogen-containing plasma ambient. Thereafter, the deposition is resumed to obtain the required final thickness. Moreover, a polysilicon line is disclosed, having a highly localized barrier layer.

Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate; step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate, the dopant from said solids-based dopant source diffusing directly into said substrate to form a first diffusion region and, at the same time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate to form a second diffusion region in at least some areas of said substrate to form a second diffusion region in at least some areas of said substrate not covered by said pattern; and step 3) forming a metal contact pattern substantially in alignment with

Abstract: In a method for forming a contact on semiconductor surface, a crystalline silicon surface is first oxidized, following which an aluminium layer is deposited onto the oxide layer. A layer of amorphous silicon is then deposited onto the aluminium layer. The structure is then heated to a temperature below the aluminium/silicon eutectic temperature to locally reduce the oxide layer in regions where the quality/density of the oxide layer is lower. Simultaneously, the amorphous silicon penetrates into the aluminium layer, in which it has a high mobility. With continued heating, the aluminium penetrates completely through the oxide layer in localized regions, exposing the crystalline silicon surface. The exposed silicon surface provides a sight for nucleating epitaxial growth, which occurs rapidly as silicon within the aluminium continuously feeds the solid phase epitaxial growth process.

Abstract: A system and method for analyzing sheet resistivity of a layer on a wafer employing electrical methods and for controlling rapid thermal annealing (RTA) of the layer is provided. The system includes components for performing RTA on the layer and components for analyzing the sheet resistivity of one or more portions of the layer upon which RTA was performed. The system further includes a feedback generator adapted to accept sheet resistivity data and to produce feedback information that can be used to control the RTA components. The system further includes a data store that can be employed in machine learning and/or to facilitate generating feedback information that can be employed to control RTA and a monitoring application that can be employed to schedule maintenance on the various components in the system.

Abstract: The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.

Abstract: To form an impurity diffusion layer on only one side of a semiconductor substrate at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is perfomed on them, or at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is performed on them and then the semiconductor substrate and the diffusion protecting plate are arranged such that those sides on which the impurity diffusion has been performed face each other and a second impurity diffusion is performed. The diffusion protecting plate may be replaced by a semiconductor substrate. The first and second impurity diffusions may be performed using an impurity of the same conductivity type.

Abstract: A semiconductor device which can reduce contact resistance, is disclosed. A semiconductor device according to the present invention includes a lower conductor pattern and an upper conductor pattern. The lower conductor pattern is in contact with the upper conductor pattern. The lower conductor pattern includes a first doped polysilicon layer, a first tungsten silicide layer and a cap layer formed sequentially. Here, the cap layer is formed to a doped polysilicon layer containing a small amount of tungsten and has stoichiometrical equivalent ratio x of Si higher than the first tungsten silicide layer. The upper conductor pattern includes a second doped polysilicon layer and a second tungsten layer formed sequentially. The contact of lower conductor pattern and the upper conductor pattern is substantially formed between the cap layer and the second doped polysilicon layer. Preferably, stoichiometrical equivalent ratio x of Si for the first tungsten silicide layer is 2.3 to 2.

Abstract: A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer.

Abstract: A method for doping crystals is disclosed. The method includes a receiver for receiving semiconductor spheres and doping powder. The semiconductor spheres and dopant powder are then directed to a chamber defined within an enclosure. The chamber maintains a heated, inert atmosphere with which to diffuse the dopant to the semiconductor spheres.

Abstract: This invention relates to a method for the heat treatment of a ZnSe crystal substrate to dope it with Al as a donor impurity, a ZnSe crystal substrate prepared by this heat treatment and a light-emitting device using the ZnSe crystal substrate, in particular, the method for the heat treatment of a ZnSe crystal substrate comprising previously forming an Al film on the substrate, first subjecting the substrate to a heat treatment in a Se atmosphere and then subjecting to a heat treatment in a Zn atmosphere.

Abstract: A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer.

Abstract: A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by minimally oxidizing the gate stack and exposed surface of the substrate, anisotropically etching the layer of oxide from the substrate, forming a doped solid source material on portions of the substrate in which source regions are to be formed and diffusing the dopants from the solid source material into the substrate.

Abstract: A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.

Abstract: High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. A layer of cobalt and a cap layer of titanium or titanium nitride are deposited on a substrate above intended source/drain regions, followed by silicidation. Embodiments include low-temperature rapid thermal annealing to form a high-resistivity phase cobalt silicide, removing the cap layer, depositing a doped film on the first phase cobalt silicide, and heating, as by high-temperature rapid thermal annealing, to form a low-resistance cobalt silicide during which impurities from the doped film diffuse through the cobalt silicide into the substrate to form source/drain regions having junctions extending into the substrate a constant depth below the cobalt silicide/silicon substrate interface. In another embodiment, impurities are diffused from the doped film to form source/drain regions and self-aligned junctions following formation of the low-resistance phase cobalt silicide.

Abstract: A purchased silicon substrate 10 is subjected to D-HF treatment, SC-1 treatment, etc. to expose the surface of the silicon substrate 10. Then, the silicon substrate 10 having the surface exposed and containing grown-in defects 12 and micro oxygen precipitates 14 is subjected to oxygen out-diffusion annealing in an argon gas ambient. The annealing is performed, e.g., in an argon gas ambient, at a temperature of about 1000 to about 1300° C. for about 1 hour. Thus, the defects 12, 14 which are near the surface of the silicon substrate 10 are reduced, and the defects in the substrate surface can be decreased.

Abstract: A method of manufacturing a non-volatile memory device is provided. According to an aspect of this method, an isolation layer is formed on a semiconductor substrate including a cell array part and a peripheral circuit part. A floating gate pattern is formed exposing the semiconductor substrate in the peripheral circuit part with a tunnel oxide layer interposed between the floating gate pattern and the semiconductor substrate in the cell array part, and an interlayer insulating layer covering the floating gate pattern is formed. A control gate layer is formed, which covers the interlayer insulating layer and the semiconductor substrate in the peripheral circuit part while interposing a gate oxide layer between the control gate layer and the semiconductor substrate.

Abstract: A method of removing vacancies in the crystal lattice of silicon wafers is provided. In particular, silicon wafers obtained from drawn rods have significantly higher defect densities in the central region as compared to the outer peripheries of the wafers. Before the diffusion of doping materials, the wafers are oxidized at a temperature that is generally lower than the diffusion temperature. As a result, the vacancies in the crystal lattice are filled with silicon which prevents the accumulation of heavy metals into the vacancies during the doping process. The performance and lifespan of the carrier in the central region of the wafers is thereby significantly increased.

Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

Abstract: A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.

Abstract: A low temperature process for forming palladium silicided shallow junctions in which ions are implanted into a palladium or a palladium silicide layer over a silicon substrate. The impurities are driven into the silicon substrate during the formation or recrystallization of the palladium silicide layer, and a diffusion region with shallow junction is formed in the substrate.