Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminating portion side.

Abstract: A method of providing a region of doped semiconductor (40) which is buried below the surface of a semiconductor substrate (10) without the requirement of epitaxially deposited layers is provided. The method includes the steps of forming first and second trench portions (26,28) in a semiconductor substrate and then introducing dopant (100) into the trench portions and diffusing the dopant into the semiconductor substrate such that a region of doped semiconductor (40) is formed extending from the first trench portion to the second trench portion. A diffusion barrier, for example formed of two barrier trenches (16, 18), is provided in the substrate adjacent the doping trenches to inhibit lateral diffusion of dopant from the doping trenches so as to maintain an undoped region (30) above the region of doped semiconductor.

Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.

Abstract: A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

Abstract: A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substrate with a selectively grown epitaxial layer. The selection transistor is formed in the selectively grown epitaxial layer, comprises a source region connected to the trench capacitor and a drain region connected to a bit line. The junction depth of the source region is chosen so that the source region reaches as far as the insulating covering layer. Optionally, the thickness of the epitaxial layer can be reduced to a thickness by oxidation and a subsequent etching. Afterwards, a contact trench is etched through the source region down to the conductive trench filling, which trench is filled with a conductive contact and electrically connects the conductive trench filling to the source region.

Abstract: A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having first and second main surfaces. The substrate has a heavily doped region of a first conductivity at the second main surface and has a lightly doped region of the first conductivity at the first main surface. The method includes providing trenches and mesas in the substrate, implanting, at an angle, a dopant of the first conductivity into a sidewall of a mesa and implanting, at an angle, a dopant of a second conductivity into the mesa at another sidewall. The method includes oxidizing the sidewalls and bottoms of each trench and tops of the mesas to create a top oxide layer, etching back the top oxide layer to expose a portion of the mesa, depositing an oxide layer to cover the etched back top layer and mesa and planarizing the top surface of the device.

Abstract: To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in yield and a method of producing the same. The device has a channel layer 16 formed on a substrate 12, a diffusion stop layer 17 formed on the top surface of the channel layer 16, a diffusion layer 18 formed on the top surface of the diffusion stop layer, and a doping region 25 formed adjoining the diffusion stop layer 17 at least at part of the diffusion layer 18 and having an impurity diffused in it, the diffusion stop layer 17 having a slower diffusion rate of the impurity than the diffusion rate of the diffusion layer 18 and stopping diffusion of the impurity from the diffusion layer 18.

Abstract: The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (NSG) layer is deposited to fill the shallow trench, and is then etched back to a depth of the shallow trench, thereby exposing a portion of the semiconductor substrate at an upper portion of the shallow trench. A doped dielectric layer is deposited over the remaining NSG layer to cover the exposed semiconductor substrate. A thermal process is then carried out to diffuse dopants of the doped dielectric layer into the semiconductor substrate, thereby forming a doped region at the periphery of the active area in a channel width direction.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern.

Abstract: An object of the present invention is to provide an ion implantation method for shortening a down time of an ion implantation apparatus after exposure of a chamber and for improving throughput and a method for manufacturing a semiconductor device. Specifically, the object of the invention is to provide an ion implantation method that can improve throughput during an ion implantation step of B and a method for manufacturing a semiconductor device. The ion implantation method comprises the steps of: introducing an impurity imparting p-type conductivity and H2O in an ion source; ionizing the impurity imparting p-type conductivity; and implanting into a semiconductor film.

Abstract: In one embodiment, a transistor is formed to have alternating depletion and conduction regions that are formed by doping the depletion and conduction regions through an opening in a substrate of the transistor.

Abstract: A method for fabricating a buried plate of a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped layer is formed on the surface of the deep trench and a material layer is formed on the doped layer. A passivation layer is formed on the sidewall of the deep trench that is not covered by the material layer. After removing the material layer, a thermal process is conducted to drive-in the dopants in the doped layer to the substrate to form a doped region, wherein the doped region serves as a buried plate of the deep trench capacitor. The doped layer also reacts with the substrate to form an oxide layer. After removing the oxide layer, a bottle-shaped deep trench is formed.

Abstract: A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

Abstract: A two-stage method for making buried strap out-diffusions is disclosed. A substrate having a deep trench is provided. A first conductive layer is deposited at the bottom of the deep trench. A collar oxide is formed on sidewalls of the deep trench. A second conductive layer is deposited within the deep trench atop the first conductive layer. The collar oxide is then etched back to a predetermined depth. A third conductive layer is deposited directly on the second conductive layer. A trench top oxide (TTO) layer is formed on the third conductive layer. A spacer is formed on the sidewalls of the deep trench. A portion of the TTO layer is etched away to form a recess underneath the spacer, which exposing the substrate in the deep trench. Thereafter, a doping process is carried out to form a first diffusion region through the recess, followed by spacer stripping.

Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: The present invention relates to a pinned photodiode used in a CMOS image sensor. The pinned photodiode according to the present invention has an uneven surface for increasing an area of a PN junction of the photodiode. So, the increased PN junction area improves a light sensitivity of the photodiode. That is, the epitaxial layer, in which the photodiode is formed, has a trench or a protrusion. Also, in the pinned photodiode, since the P0 diffusion layer is directly in contact with the P-epi layer, the two P-type layers have the same potential and then it may operate in a low voltage.

Abstract: The invention relates to novel boron, phosphorus or boron-aluminium dopant pastes for the production of p, p+ and n, n+ regions in monocrystalline and polycrystalline Si wafers, and of corresponding pastes for use as masking pastes in semiconductor fabrication, power electronics or in photovoltaic applications.

Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a thin oxide layer and a polycrystalline semiconductor material (e.g., polysilicon) that includes a dopant of the second conductivity type.

Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.

Abstract: Steep concentration gradients are achieved in semiconductor device of small sizes formed on SOI or double SOI wafers by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects. In the case of SOI wafers greater uniformity of electrical characteristics are achieved using the high quality of semiconductor material made available therein consistent with the relatively thin active layer.

Abstract: A method for manufacturing a vertical power component on a silicon wafer, including the steps of growing a lightly-doped epitaxial layer of a second conductivity type on the upper surface of a heavily-doped substrate of a first conductivity type, the epitaxial layer having a thickness adapted to withstanding the maximum voltage likely to be applied to the power component during its operation; and delimiting in the wafer an area corresponding to at least one power component by an isolating wall formed by etching a trench through the epitaxial layer and diffusing from this trench a dopant of the first conductivity type of high doping level.

Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.

Abstract: A method for fabricating a high voltage power MOSFFT having a voltage sustaining region that includes doped columns formed by rapid diffusion. A high voltage semiconductor device having a substrate of a first or second conductivity type, an epitaxial layer of the first conductivity on the substrate, and a voltage sustaining region formed in the epitaxial layer, the voltage sustaining region including a column having a second conductivity type formed along at least outer sidewalls of a filled trench, the column including at least one first diffused region and a second diffused region, the first diffused region being connected by the second region and the second region having a junction depth measured from the trench sidewall that is less than the junction depth of the first region and a third region of a second conductivity type that extends from the surface of the epitaxial layer to intersect at least one of the first and second regions of second conductivity type.

Abstract: A method of improving planarity of a photoresist. Before coating the photoresist over a silicon oxide layer, modifying a surface of the silicon oxide layer to enhance an adhesion between the silicon oxide layer and the photoresist. The photoresist flows into trenches of the silicon oxide layer, then the photoresist has good planarity, even after performing a baking process.

Abstract: An integrated microelectromechanical system comprises at least one MOSFET interconnected to at least one MEMS device on a common substrate. A method for integrating the MOSFET with the MEMS device comprises fabricating the MOSFET and MEMS device monolithically on the common substrate. Conveniently, the gate insulator, gate electrode, and electrical contacts for the gate, source, and drain can be formed simultaneously with the MEMS device structure, thereby eliminating many process steps and materials. In particular, the gate electrode and electrical contacts of the MOSFET and the structural layers of the MEMS device can be doped polysilicon. Dopant diffusion from the electrical contacts is used to form the source and drain regions of the MOSFET. The thermal diffusion step for forming the source and drain of the MOSFET can comprise one or more of the thermal anneal steps to relieve stress in the structural layers of the MEMS device.

Abstract: A MOSFET transistor comprising a gate made of silicon-germanium alloy, formed on a single crystal silicon substrate by means of a thin insulating layer, and drain and source regions implanted in the substrate on each side of the gate, characterized in that the gate comprises side regions presenting an increasing germanium percentage towards the sides of the gate facing the drain and source regions. Advantage: compensation of the short channel effect by locally decreasing the work function of the gate material near the drain and source regions.

Abstract: A semiconductor device which can reduce contact resistance, is disclosed. A semiconductor device according to the present invention includes a lower conductor pattern and an upper conductor pattern. The lower conductor pattern is in contact with the upper conductor pattern. The lower conductor pattern includes a first doped polysilicon layer, a first tungsten silicide layer and a cap layer formed sequentially. Here, the cap layer is formed to a doped polysilicon layer containing a small amount of tungsten and has stoichiometrical equivalent ratio x of Si higher than the first tungsten silicide layer. The upper conductor pattern includes a second doped polysilicon layer and a second tungsten layer formed sequentially. The contact of lower conductor pattern and the upper conductor pattern is substantially formed between the cap layer and the second doped polysilicon layer. Preferably, stoichiometrical equivalent ratio x of Si for the first tungsten silicide layer is 2.3 to 2.

Abstract: A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of the barrier, a vertical surface and a lower horizontal surface. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface, and the barrier layer prevent the dopants from diffusing into the upper horizontal surface.

Abstract: A fabrication method of a semiconductor device that realizes a simplified contact formation process is provided. After a single-crystal silicon substrate having a main surface is provided, a dielectric film having a contact hole uncovering the main surface of the substrate is formed on the main surface of the substrate. Next, a silicon nitride film is formed on the main surface of the substrate in the contact hole of the dielectric film. Then, a metal film is formed on the dielectric film to be contacted with the silicon nitride film in the contact hole of the dielectric film. The metal film has a property that an atom of the metal film serves as diffusion species in a solid-phase silicidation reaction. The metal film, the silicon nitride film, the dielectric film, and the substrate are heat-treated to thereby form a metal silicide film due to a solid-phase silicidation reaction between the metal film and the substrate.

Abstract: For forming electrical interlayer contact in a semiconductor device, an insulating film is formed on a first electrically conductive layer and then a contact hole is formed in the insulating film to expose a part of the first electroconductive, an activated surface of the exposed part is formed in the contact hole, a gas containing an impurity component is supplied to form an impurity adsorption film on the activated surface, and the contact hole is filled with a second electrically conductive layer which electrically contacts the first layer through the contact hole.

Abstract: Known methods for forming trench storage capacitors require the chemical vapour deposition (CVD) of an undoped silicon oxide layer in order to prevent auto doping of side wall of a semiconductor trench. This layer is deposited once an arsenic doped silicon oxide layer has been disposed and etched to an appropriate depth. Such a technique results in a complex and expensive process. It is therefore proposed to deposit (step 906) the undoped silicon oxide layer 108 in-situ immediately after the arsenic doped silicon oxide layer 106 has been deposited (step 904) and before etching takes place (step 910). It is thus possible to remove the CVD of the undoped silicon oxide, thereby simplifying the overall process and yielding a device having improved performance characteristics.

Abstract: A method for fabricating a type of Trench Mask ROM cell comprises steps including: providing a substrate doped lightly with p-type dopant, sequentially forming a pad oxide layer and a nitride layer on the substrate; etching back the pad oxide layer, the nitride layer and the substrate to form plural trenches; a gate oxide layer being formed on surfaces of each trench; then, implanting n+-type ions into the substrate beneath the pad oxide layer and between each two adjacent trenches; and, forming a polysilicon layer on the gate oxide and pad oxide; finally, implanting n+-type ions into the substrate beneath the gate oxide layer on bottoms of selected trenches. And, it is appreciated that the sequence of the formation of plural trenches and implanting n+-type ions into substrate between each trench can be reversed in the embodiment without affecting subsequent steps.

Abstract: An opto-electronic device has a diffusion area of one conductive type formed in a semiconductor substrate of another conductive type, an ohmic contact layer making contact with the diffusion area, and an electrode making contact with the ohmic contact layer. The diffusion area is formed by solid-phase diffusion. The same mask is used to define the patterns of both the diffusion source layer and the ohmic contact layer, so that the ohmic contact layer is self-aligned with the diffusion area.

Abstract: A method for forming very deep pn-junctions without using epitaxy or extensively high temperature processing is provided. At least two parallel deep trenches are etched into a silicon substrate. Then the sidewalls of these trenches are predeposited by dopants. After filling the deep trenches with insulating material, a diffusion process is done. This diffusion process performs in such a way that the formerly predeposited dopant is distributed rather uniformly in between the parallel deep trenches, e.g. is counterdoping the whole region with respect to the monocrystalline silicon substrate. The said lateral trench doped region, which preferably is more deep than wide, serves either as drain or collector region of high voltage transistors or other high voltage devices. Also other devices like hall sensors, which gain advantages from the more deep than wide counterdoped regions, are possible.

Abstract: A method for uniformly doping a semiconductor surface including non-planar regions. A doped coating material, such as in-situ doped polysilicon or doped glass, is deposited or spread over an etched silicon substrate or wafer. Heat is applied at high temperatures to drive n or p type dopants from the doped coating material into nearby regions of the substrate. In this manner angled or recessed regions of a substrate, such as vertical or angled junction sidewalls in v-groove or trench structures, are uniformly doped.

Abstract: A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.

Abstract: The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

Abstract: A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.

Abstract: A method for forming a contact of a semiconductor device is described, in which a conductive layer pattern is electrically connected to a semiconductor substrate and an interlayer insulating film is formed on the semiconductor substrate including the conductive layer pattern. The interlayer insulating film is etched down to a top surface of the conductive layer pattern using a contact formation mask to form a contact hole. The conductive layer pattern is isotropically etched through the contact hole so as to extend the surface area of the exposed conductive layer pattern and the contact hole is filled with conductive material, forming a contact plug electrically connected to the conductive layer pattern. It is therefore possible to extend the contact area between the conductive layer pattern and a contact plug. As a result, the contact resistance is reduced.

Abstract: A method for counter-doping gate stack conductors on a semiconductor substrate, which substrate is provided with narrow space array regions (i.e., memory device regions) having a plurality of capped gate stack conductors spaced a first distance apart, and wide space array regions (i.e., logic device regions) having a plurality of gate stack conductors spaced a second distance apart, wherein the first distance is narrow in relation to the second distance.

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode.

Abstract: The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

Abstract: In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550.degree. C. to about 560.degree. C.

Abstract: The preferred embodiments of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity. In one embodiment, the present invention is used to form source/drain and bitline diffusion structures for use in pillar memory cells. Additionally, in another embodiment, the present invention is used to form source/drain and plate diffusion structures in pillar memory cells. Both preferred embodiments deposit conformal photoresist on a pillar structure and use an off-axis exposure process to recess a dopant source layer to the proper depth along the pillar. The recessed dopant source layer can then be used to form the source/drain/bitlines diffusions or source/drain/plate diffusions in the pillar memory device.

Abstract: A method of forming a transistor is disclosed that comprises the step forming a gate insulator layer 12 on an outer surface of the substrate 10. A first gate conductor layer 22 is formed outwardly from the gate insulator layer 12. The first gate conductor layer 22 is extremely thin. Dopants are introduced into the layer 22 to render it conductive by using a diffusion source layer 24. The diffusion source layer 24 is then removed and replaced by a second gate conductor layer 26 having low resistance. The layer 26 can be used to form a T-gate structure 28, a flush gate 30, or a conventional gate structure.

Abstract: A shallow trench isolation structure is formed by providing a pad layer and a silicon nitride polish stop layer on a surface of a P-type silicon substrate. The silicon nitride polish stop layer and the pad oxide layer are patterned to define openings corresponding to portions of the substrate that will be etched to form trenches. Trenches are defined in the P-type silicon substrate by anisotropic etching. A boron doped oxide or glass is deposited along the walls and floor of the trench. An undoped TEOS oxide is provided over the doped oxide or glass to complete filling of the trench. The device is subjected to a high temperature reflow process, causing the dielectric materials to flow, partially planarizing the device and causing the boron of the first layer to diffuse into the walls and floor of the trench. Chemical mechanical polishing removes excess portions of the dielectric layers.

Abstract: A method of fabricating high-density flat cell mask ROM is disclosed. The method comprises, formed a plurality of trenches in a silicon substrate firstly. An oxynitride layer is then grown on resultant surfaces to about 1-5 nm, After refilling a plurality of trenches with a first in-situ phosphorus doping polysilicon layer or amorphous silicon, etching back the polysilicon layer to form a flat surface by a CMP process is achieved. Subsequently, a thermal oxidation process is carried out to grow an oxide layer and to form a plurality of buried bit lines by diffusing the conductive impurities in the polysilicon layer through the oxynitride layer into the silicon substrate. A second in-situ n+ doped polysilicon layer is deposited and patterned as word lines; then a patterned photoresist coated on the second polysilicon layer except predetermining coding regions. Finally, a coding boron implant into the predetermined coding region is done to form normally off transistors.