Abstract: According to one embodiment, a nitride semiconductor device includes a semiconductor layer, a source electrode, a drain electrode, a first and a second gate electrode. The semiconductor layer includes a nitride semiconductor. The source electrode provided on a major surface of the layer forms ohmic contact with the layer. The drain electrode provided on the major surface forms ohmic contact with the layer and is separated from the source electrode. The first gate electrode is provided on the major surface between the source and drain electrodes. The second gate electrode is provided on the major surface between the source and first gate electrodes. When a potential difference between the source and first gate electrodes is 0 volts, a portion of the layer under the first gate electrode is conductive. The first gate electrode is configured to switch a constant current according to a voltage applied to the second gate electrode.

Abstract: A field effect transistor (FET) has a channel hosted in Ge. The FET has silicon-germanium (SiGe) source and drain formed by selective epitaxy. The SiGe source and drain exert a tensile stress onto the Ge channel. During forming of the SiGe source and drain, an n-type dopant species and a compensating species are being incorporated into the SiGe source and drain. The n-type dopant species and the compensating species are so selected that the size of the SiGe atomic radius is inbetween the dopant atomic radius and the compensating species atomic radius.

Abstract: Exemplary embodiments of the present invention relate to a method of fabricating a light emitting diode (LED). According to an exemplary embodiment of the present invention, the method includes growing a first GaN-based semiconductor layer on a substrate at a first temperature by supplying a chamber with a nitride source gas and a first metal source gas, stopping the supply of the first metal source gas and maintaining the first temperature for a first time period after stopping the supply of the first metal source gas, decreasing the temperature of the substrate to the a second temperature after the first time period elapses, growing an active layer of the first GaN-based semiconductor layer at the second temperature by supplying the chamber with a second metal source gas.

Abstract: According to one embodiment, an electronic device includes a side wall, an interface component, a partition wall, and a protrusion. The side wall is formed on one of the bottom wall and the top wall of a housing to spatially separate the inside of the housing from the outside. The side wall includes a through opening. The interface component faces the through opening in the housing. The partition wall is formed on the one of the bottom wall and the top wall and coupled perpendicularly to the side wall. The partition wall spatially separates the inside of the housing and a component retainer formed as a cutout or a recess of the housing. The protrusion is formed on the one of the bottom wall and the top wall to be spaced apart from the partition wall. The interface component is held between the partition wall and the protrusion.

Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.

Abstract: Group III-nitride N-type doping techniques are described.

Abstract: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.

Abstract: It is to provide a vapor phase growth method in which an epitaxial layer consisting of a compound semiconductor such as InAlAs, can be grown, with superior reproducibility, on a semiconductor substrate such as Fe-doped InP. In vapor phase growth method for growing an epitaxial layer on a semiconductor substrate, a resistivity of the semiconductor substrate at a room temperature is previously measured, a set temperature of the substrate is controlled depending on the resistivity at the room temperature such that a surface temperature of the substrate is a desired temperature regardless of the resistivity of the semiconductor substrate, and the epitaxial layer is grown.

Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

Abstract: The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) of silicon is provided, at a surface thereof, with a first semiconductor layer (1) having a lattice of a mixed crystal of silicon and germanium and a thickness such that the lattice is substantially relaxed, and on top of the first semiconductor layer (1) a second semiconductor layer (2) is provided comprising strained silicon, in which layer (2) a part of the semiconductor device (10) is formed, and wherein measures are taken to avoid reduction of the effective thickness of the strained silicon layer (2) during subsequent processing needed to form the semiconductor device (10), said measures comprising the use of a third layer (3) having a lattice of a mixed crystal of silicon and germanium.

Abstract: A method is provided for forming a silicon oxide (SiOx) thin-film with embedded nanocrystalline silicon (Si). The method deposits SiOx, where x is in the range of 1 to 2, overlying a substrate, using a high-density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, the SiOx thin-film is embedded with nanocrystalline Si. The HD PECVD process may use an inductively coupled plasma (ICP) source, a substrate temperature of less than about 400° C., and an oxygen source gas with a silicon precursor. In one aspect, a hydrogen source gas and an inert gas are used, where the ratio of oxygen source gas to inert gas is in the range of about 0.02 to 5. The SiOx thin-film with embedded nanocrystalline Si typically has a refractive index in the range of about 1.6 to 2.2, with an extinction coefficient in the range of 0 to 0.5.

Abstract: A method of growing a semiconductor layer structure comprises growing a first semiconductor layer and incorporating hydrogen into the first semiconductor layer. One or more further semiconductor layers are then grown over the first semiconductor layer to form a semiconductor layer structure. A selected portion of the first semiconductor layer is then annealed so as to change the electrical resistance of the selected portion of the first semiconductor layer. The electrical resistance of the one or more further semiconductor layers that have been grown over the first semiconductor layer is not significantly changed by the annealing step. The invention may be used, for example, to create a current aperture in a semiconductor layer within a semiconductor layer structure.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: High-Voltage Lateral MOSFET and Lateral Double-diffused MOS (LDMOS) for HV power applications with multiple paths for conduction in the drain extension and methods of fabrication are described.

Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

Abstract: A boron phosphide-based semiconductor device includes a single crystal substrate having formed thereon a boron-phosphide (BP)-based semiconductor layer containing boron and phosphorus as constituent elements, where phosphorus (P) occupying the vacant lattice point (vacancy) of boron (B) and boron occupying the vacant lattice point (vacancy) of phosphorus are present in the boron-phosphide (BP)-based semiconductor layer. The boron phosphide-based semiconductor device includes a p-type boron phosphide-based semiconductor layer in which boron occupying the vacancy of phosphorus is contained in a higher atomic concentration than phosphorus occupying the vacancy of boron and a p-type impurity of Group II element or Group I V element is added.

Abstract: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.

Abstract: Provided is a method of heating a semiconductor substrate having a surface of a III-V compound semiconductor containing phosphorus as a group V constituent element. The method comprises the steps of: (a) providing an alloy in a heating furnace, the alloy including tin, indium, and phosphorus as main constituents; and (b) raising a temperature of the article in an atmosphere containing vapor of phosphorus supplied from the alloy.

Abstract: It is an object of the present invention to make it easy to diffuse phosphorus into a silicon film and allow the phosphorus diffusion concentration to be easily controlled by varying the timing at which the dopant gas is allowed to flow. A silicon wafer 10 on whose surface an amorphous silicon film 12 has been formed is placed in a diffusion furnace. After this, phosphine (PH3) or a mixed gas containing phosphine is allowed to begin flowing over the wafer 15 and the phosphorus is diffused into the silicon film 12 before the amorphous silicon film 12 crystallizes and changes into a polysilicon film.

Abstract: Provided is a method of heating a semiconductor substrate having a surface of a III-V compound semiconductor containing phosphorus as a group V constituent element. The method comprises the steps of: (a) providing an alloy in a heating furnace, the alloy including tin, indium, and phosphorus as main constituents; and (b) raising a temperature of the article in an atmosphere containing vapor of phosphorus supplied from the alloy.

Abstract: Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.

Abstract: A method of activating a compound semiconductor layer into a p-type compound semiconductor layer is provided. In order to reduce the electrical conductivity of the compound semiconductor layer grown by a VPE method, electromagnetic waves having energy larger than the band gap of the compound semiconductor layer are irradiated and annealing is performed. If the amount of the p-type impurities contained in the layer during growth thereof increases, the resistivity of the layer increases and an annealing temperature is lowered. Also, the contact resistance between the compound semiconductor layer and an electrode is reduced.

Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.

Abstract: A method of fabricating an Emode HIGFET semiconductor device, and the device, is disclosed including epitaxially growing by metal-organic chemical vapor deposition an epitaxial buffer. The buffer includes a layer of short-lifetime gallium arsenide on a gallium arsenide substrate and a layer of aluminum gallium arsenide on the layer of short-lifetime gallium arsenide. The short-lifetime gallium arsenide is grown at a temperature below approximately 550° C. so as to have a lifetime less than approximately 500 picoseconds. A stack of compound semiconductor layers is then epitaxially grown on the layer of aluminum gallium arsenide of the buffer and an Emode field effect transistor is formed in the stack.

Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.

Abstract: An LPE (Liquid Phase Epitaxy) apparatus is diverted to a Zn-diffusion apparatus for diffusing Zn into III-V group compound semiconductor. The Zn-diffusion apparatus comprises a base plank extending in a direction, having a wafer-storing cavity for storing an object wafer and an exhaustion hole for exhaling gases, a slider having a frame and a cap plate for attaching to or detaching from the frame, the frame having serially aligning M rooms with an open bottom and a rack being separated from each other by (M−1) partition walls, a manipulating bar for sliding the slider upon the base plank forward or backward in the direction, a tube for enclosing the base plank and the slider and for being capable of being made vacuous, a heater surrounding the tube for heating the slider, each rack of the rooms being allocated with a Zn-diffusion material and a V element material (or a non-doped capping wafer) in turn for aligning the rooms into repetitions of a V element room and a diffusion room.

Abstract: An opto-electronic device has a diffusion area of one conductive type formed in a semiconductor substrate of another conductive type, an ohmic contact layer making contact with the diffusion area, and an electrode making contact with the ohmic contact layer. The diffusion area is formed by solid-phase diffusion. The same mask is used to define the patterns of both the diffusion source layer and the ohmic contact layer, so that the ohmic contact layer is self-aligned with the diffusion area.

Abstract: A method for fabricating a thin film transistor includes the steps of calculating a scan pitch of a laser beam such that an unevenly crystallized area and an evenly crystallized area of a crystallized polycrystalline silicon layer are alternately arranged at a regular interval, crystallizing an amorphous silicon layer to a polycrystalline silicon layer by scanning the laser beam according to the scan pitch, calculating a spacing pitch of active patterns from the scan pitch of the laser beam, and forming the active patterns in a selected portion of the polycrystalline silicon layer according to the spacing pitch.

Abstract: A method of activating a compound semiconductor layer into a p-type compound semiconductor layer is provided. In order to reduce the electrical conductivity of the compound semiconductor layer grown by a VPE method, electromagnetic waves having energy larger than the band gap of the compound semiconductor layer are irradiated and annealing is performed. If the amount of the p-type impurities contained in the layer during growth thereof increases, the resistivity of the layer increases and an annealing temperature is lowered. Also, the contact resistance between the compound semiconductor layer and an electrode is reduced.

Abstract: An LPE (Liquid Phase Epitaxy) apparatus is diverted to a Zn-diffusion apparatus for diffusing Zn into III-V group compound semiconductor. The Zn-diffusion apparatus comprises a base plank extending in a direction, having a wafer-storing cavity for storing an object wafer and an exhaustion hole for exhaling gases, a slider having a frame and a cap plate for attaching to or detaching from the frame, the frame having serially aligning M rooms with an open bottom and a rack being separated from each other by (M−1) partition walls, a manipulating bar for sliding the slider upon the base plank forward or backward in the direction, a tube for enclosing the base plank and the slider and for being capable of being made vacuous, a heater surrounding the tube for heating the slider, each rack of the rooms being allocated with a Zn-diffusion material and a V element material (or a non-doped capping wafer) in turn for aligning the rooms into repetitions of a V element room and a diffusion room.

Abstract: Provided is a manufacturing method of a compound semiconductor having at least one layer of carbon-doped p-type semiconductor epitaxial layer by a MOVPE process, wherein carbon trichloride bromide is used as a carbon source of carbon to be added to the p-type semiconductor epitaxial layer. In the method the etching amount during growth is relatively small, and carbon can be added to a high concentration even with a large MOVPE apparatus.

Abstract: A light-sensing/emitting diode array chip has impurity diffusion regions with a depth of at least 0.5 .mu.m but not more than 2 .mu.m in a semiconductor substrate. Each impurity diffusion region is preferably divided into a first region, used for emitting or sensing light, and a wider second region, used for electrode contact. The second regions are located on alternate sides of the array line, permitting a small array pitch to be combined with a large contact area. In a wafer process for fabrication of the chips, a diffusion mask has both windows defining the impurity diffusion regions, and dicing line marks. The dicing line marks are narrowed where they pass adjacent to the windows at the ends of the chip. In the electrode fabrication step, a photomask with an enlarged pattern is used, to allow for misalignment with the diffusion mask.

Abstract: A method for altering a dopant front profile of a dopant in a wafer is disclosed. An initial wafer is provided with an upper doped layer and a lower undoped layer. An oxide layer is grown over a portion of the wafer while a second portion of the wafer remains oxide-free. The wafer is then exposed to a substantially non-growth enhancement diffusion environment that contains the dopant at a given flow rate, but lacks additional materials which would cause growth on the exposed portions of wafer. After a predetermined amount of diffusion is allowed to occur, the wafer is removed from the diffusion environment and the oxide layer is removed.

Abstract: A manufacturing method of a junction field effect transistor, promising a low ON resistance, high maximum drain current and linearity with a high transmission gain and also enabling the gate length to be reduced, makes a channel layer by sequentially epitaxially growing an undoped GaAs layer, n.sup.+ -type GaAs layer and n-type GaAs layer on a semi-insulating GaAs substrate via a GaAs buffer layer. Through an opening formed in a diffusion mask in form of a SiN.sub.x film on the n-type GaAs layer, Zn is diffused into the n-type GaAs layer to form a p.sup.+ -type gate region. From above the diffusion mask, a gate metal layer is deposited, and patterned to make a gate electrode in the opening of the diffusion mask in self-alignment with the p.sup.+ -type gate region.

Abstract: A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated.

Abstract: The present invention relates to an epitaxial wafer including a PN junction, which is improved in terms of light output and can have a good-enough ohmic electrode formed thereon. Epitaxial layers are formed of GaAs.sub.1-x P.sub.x where 0.45 <.times..ltoreq.1). A first P-type layer is formed by a vapor-phase growth process, and a second P-type layer is formed on the first P-type layer by a thermal diffusion process, said second P-type layer having a carrier concentration higher than that of said first P-type layer.