Abstract: A solar cell including: a semiconductor substrate having a first conductivity type; a first conductivity type layer having a conductivity type equal to the first conductivity type and a second conductivity type layer having a second conductivity type opposite to the first conductivity type, which are located on a first main surface of the substrate; a first collecting electrode on the first conductivity type layer located on the first main surface; and a second collecting electrode on the second conductivity type layer located on the first main surface. In the solar cell, a second conductivity type layer having the second conductivity type is formed on a side surface of the semiconductor substrate and continuously from the second conductivity type layer located on the first main surface. Consequently, it is possible to provide a solar cell having excellent conversion efficiency and being capable of efficiently collecting carriers.

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.

Abstract: The present disclosure provides a method of manufacturing an electron source. The method includes forming one or more fixed emission sites on at least one needle tip, the fixed emission sites including a reaction product formed by metal atoms on a surface of the needle tip and gas molecules.

Abstract: What is proposed is a method of producing at least two differently heavily doped subzones (3, 5) predominantly doped with a first dopant type in a silicon substrate (1), in particular for a solar cell. The method comprises: covering at least a first subzone (3) of the silicon substrate (1) in which a heavier doping with the first dopant type is to be produced with a doping layer (7) of borosilicate glass, wherein at least a second subzone (5) of the silicon substrate (1) in which a lighter doping with the first dopant type is to be produced is not covered with the doping layer (7), and wherein boron as a dopant of a second dopant type differing from the first dopant type and oppositely polarized with respect to the same is included in the layer (7), and; heating the such prepared silicon substrate (1) to temperatures above 300° C., preferably above 900° C., in a furnace in an atmosphere containing significant quantities of the first dopant type.

Abstract: Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a self-assembled monolayer (SAM) is used to achieve selective area deposition. Methods described herein relate to alternating SAM molecule and hydroxyl moiety exposure operations which may be utilized to form SAM layers suitable for blocking deposition of subsequently deposited materials.

Abstract: Provided is a method of manufacturing a heat exchanger by diffusion bonding in which deformation of bonding members as stainless steel plates is suppressed, and releasability (detachability of a bonding member from a release member) after diffusion bonding treatment is excellent. Provided is a method of manufacturing a heat exchanger, the method including layering a plurality of bonding members 1 made of stainless steel, and applying heat and pressure to effect diffusion bonding of the bonding members 1, in which release members 3 are arranged on the both surface sides of the bonding members 1, and holding jigs 4 are arranged so as to sandwich the bonding members 1 through the release members 3, and pressing is then performed through the holding jigs 4 with a pressure device, and in which the diffusion bonding is performed using a combination of the release members 3 and the bonding members 1, the release members 3 including a steel material containing 1.

Abstract: A vapor phase growth apparatus according to an embodiment includes a reaction chamber, a ring-shaped holder provided in the reaction chamber, the ring-shaped holder configured to hold a substrate, the ring-shaped holder including an outer portion, and an inner portion on which a ring-shaped protrusion is provided and surrounded by the outer portion, the ring-shaped protrusion being separated from the outer portion, an upper surface of the outer portion being higher than an upper surface of the ring-shaped protrusion, and a heater provided below the ring-shaped holder.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. A semiconductor substrate has a surface on which an abrasion trace is formed, and a dopant diffusion region includes a portion extending in the direction at an angle within the range of ?5° to +5° with respect to the direction in which the abrasion trace extends.

Abstract: A method of etching a glass substrate using an etchant that is reversibly activated to etch only in precise locations in which such etching is desired and is deactivated when outside of these locations. The method involves exposing a first side of the glass substrate to a mixture of chemical substances that includes a neutralized etchant that is photosensitive. The neutralized etchant is formed by reacting a neutralizer with an etchant. The method also includes transmitting light from a direction of a second side of the glass into the mixture of chemical substances. In response to exposure to this light, the etchant is reversibly released from a bond to the neutralizer to form the etchant on predetermined areas of the first side of the glass, wherein the predetermined areas are defined by the dimension of the light.

Abstract: After the completion of the transport of a semiconductor wafer into a chamber, the flow rate of nitrogen gas supplied into the chamber is decreased. In this state, a preheating treatment and flash irradiation are performed. The flow rate of nitrogen gas supplied into the chamber is increased when the temperature of the front surface of the semiconductor wafer is decreased to become equal to the temperature of the back surface thereof after reaching its maximum temperature by the irradiation of the substrate with a flash of light. Thereafter, the supply flow rate of nitrogen gas is maintained at a constant value until the semiconductor wafer is transported out of the chamber. This achieves the reduction in particles deposited on the semiconductor wafer while suppressing adverse effects resulting from the nonuniform in-plane temperature distribution of the semiconductor wafer.

Abstract: A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.

Abstract: The impurity diffusion method includes: transferring an object on which the thin film is formed into a processing chamber (operation 1); raising a temperature of the object to a vapor diffusion temperature in the processing chamber (operation 3); and supplying an impurity-containing gas that contains the impurities into the processing chamber, together with an inert gas and diffusing the impurities in the thin film formed on the object of which the temperature is raised to the vapor diffusion temperature (operation 4), wherein in the operation 4, an impurity diffusion acceleration gas for accelerating the diffusion of the impurities into the thin film is supplied into the processing chamber, together with the impurity-containing gas and the inert gas.

Abstract: Methods, apparatus, and systems for depositing materials with gaseous precursors are provided. In certain implementations, the methods involve providing a wafer substrate to a chamber of an apparatus. The apparatus includes a showerhead to deliver a gas to the chamber, a volume, and an isolation valve between the volume and the showerhead. A gas is delivered the volume when the isolation valve is closed, pressurizing the volume. The isolation valve is opened to allow the gas to flow to the showerhead when the gas is being delivered to the volume. A material is formed on the wafer substrate using the gas. In some implementations, releasing the pressurized gas from the volume reduces the duration of time to develop a spatially uniform gas flow across the showerhead.

Abstract: Provided is a method of producing a wafer for a solar cell that can produce the solar cell with high conversion efficiency. A method of producing a wafer for a solar cell according to the present invention comprises a first step of contacting lower alcohol to at least one surface of the semiconductor wafer and a second step, after the first step, of contacting hydrofluoric acid containing metal ion to the at least one surface of the semiconductor wafer, and a third step that is, after the second step, a step of contacting alkali solution to the at least one surface of the semiconductor wafer, a step of contacting acid solution containing hydrofluoric acid and nitric acid to the at least one surface of the semiconductor wafer, or a step of carrying out an oxidation treatment to the at least one surface of the semiconductor wafer.

Abstract: The object of the invention is a process for P-type boron doping of silicon wafers placed on a support in the chamber of a furnace of which one end comprises a wall in which means for introducing reactive gases and a gas carrying a boron precursor in gaseous form are located, whereby said process comprises the stages that consist in: a) In the chamber, reacting the reactive gases with boron trichloride BCl3 that is diluted in the carrier gas at a pressure of between 1 kPa and 30 kPa, and a temperature of between 800° C. and 1100° C., for forming a boron oxide B2O3 glass layer, b) Carrying out the diffusion of atomic boron in silicon under an N2+O2 atmosphere at a pressure of between 1 kPa and 30 kPa. A furnace designed for the implementation of said doping process as well as its applications—the manufacturing of large boron-doped silicon slices, in particular for photovoltaic applications—is also claimed.

Abstract: A method and apparatus to manage the diffusion process by controlling the diffusion path in the semiconductor fabrication process is disclosed. In one embodiment, a method for processing a substrate comprising steps of forming one or more diffusion areas on said substrate; disposing the substrate in a diffusion chamber, wherein the diffusion chamber is under a vacuum condition and a source material therein is heated and evaporated; and diffusing the source material into the diffusion area on said substrate, wherein said source material travels through a diffusion controlling unit adapted to manage the flux thereof in the diffusion chamber, so concentration of the source material is uniform in a diffusion region above the substrate.

Abstract: A mobile terminal includes a body having a user input unit for receiving a control command; an antenna unit mounted on the body to transmit and receive a radio signal; and a circuit board connected to the antenna unit to process the radio signal, wherein the antenna unit includes: a base film made of a light-transmissive material; a first conductive oxide film formed on one surface of the base film; a metal conductive part laminated on the first conductive oxide film and forming an antenna pattern corresponding to the radio signal; and a second conductive oxide film configured to cover the metal conductive part.

Abstract: A method of vapor-diffusing impurities into a diffusion region of a target substrate to be processed using a dummy substrate is provided. The method includes loading the target substrate and the dummy substrate in a substrate loading jig, accommodating the substrate loading jig loaded with the target substrate and the dummy substrate in a processing chamber of a processing apparatus, and vapor-diffusing impurities into the diffusion region of the target substrate in the processing chamber having the accommodated substrate loading jig. The vapor-diffused impurities are boron, an outer surface of the dummy substrate includes a material having properties not allowing boron adsorption.

Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion, implantation.

Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.

Abstract: The impurity diffusion method includes: transferring an object on which the thin film is formed into a processing chamber (operation 1); raising a temperature of the object to a vapor diffusion temperature in the processing chamber (operation 3); and supplying an impurity-containing gas that contains the impurities into the processing chamber, together with an inert gas and diffusing the impurities in the thin film formed on the object of which the temperature is raised to the vapor diffusion temperature (operation 4), wherein in the operation 4, an impurity diffusion acceleration gas for accelerating the diffusion of the impurities into the thin film is supplied into the processing chamber, together with the impurity-containing gas and the inert gas.

Abstract: After the completion of the transport of a semiconductor wafer into a chamber, the flow rate of nitrogen gas supplied into the chamber is decreased. In this state, a preheating treatment and flash irradiation are performed. The flow rate of nitrogen gas supplied into the chamber is increased when the temperature of the front surface of the semiconductor wafer is decreased to become equal to the temperature of the back surface thereof after reaching its maximum temperature by the irradiation of the substrate with a flash of light. Thereafter, the supply flow rate of nitrogen gas is maintained at a constant value until the semiconductor wafer is transported out of the chamber. This achieves the reduction in particles deposited on the semiconductor wafer while suppressing adverse effects resulting from the nonuniform in-plane temperature distribution of the semiconductor wafer.

Abstract: A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns.

Abstract: A heat treatment method of the present invention includes mounting a plurality of semiconductor wafers upright on a treatment boat in parallel to each other, inserting the treatment boat in a space above an injector located in a tube to be oriented to plane surfaces of the semiconductor wafers in parallel to an extending direction of the tube, and heating the tube while continuously supplying source gas into the tube through openings of the injector.

Abstract: A dopant device includes: a dopant holder that holds Ge which is solid at normal temperature and liquefies the Ge near a surface of the semiconductor melt, the dopant holder including a communicating hole for delivering the liquefied Ge downwardly; a cover portion for covering the Ge held by the dopant holder; and a vent provided on the cover portion for communicating with the outside. A dopant injecting method is carried out using such a dopant device, the dopant injecting method including: loading Ge dopant in a solid state into the doping device; liquefying the solid Ge dopant loaded into the doping device while holding the doping device at a predetermined height from a surface of a semiconductor melt; and doping the semiconductor melt with the liquefied Ge that is flowed from the communicating hole.

Abstract: Radiation detector. The detector includes an ionic junction having an ionically bonded wide band gap material having a first region dominated by positively charged ionic defects in intimate contact with a second region dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. The detector also includes an ionic junction having a first ionically bonded wide band gap material dominated by positively charged ionic defects in intimate contact with a second ionically bonded wide band gap material dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. Circuit means are provided to establish a voltage across the junction so that radiation impinging upon the junction will cause a current to flow in the circuit.

Abstract: A process for P-type boron doping of silicon wafers placed on a support in the chamber of a furnace of whose one end includes a wall in which element for introducing reactive gases and a carrier gas carrying a boron precursor in gaseous form are located, whereby the process includes the following stages: a) reacting in the chamber, the reactive gases with boron trichloride BCl3 that is diluted in the carrier gas at a pressure of between 1 kPa and 30 kPa, and a temperature of between 800° C. and 1100° C., to form a boron oxide B2O3 glass layer; and b) carrying out the diffusion of atomic boron in silicon under an N2+O2 atmosphere at a pressure of between 1 kPa and 30 kPa. A furnace designed for implementing the doping process, and the manufacturing of large boron-doped silicon slices, in particular for photovoltaic applications are also claimed.

Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.

Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.

Abstract: A low noise transistor and a method of making a low noise transistor. A noise-reducing agent is introduced into the gate electrode and then moved into the gate dielectric of a transistor.

Abstract: A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a semiconductor body. The activated hydrogen gas breaks existing bonds in the substrate (e.g., silicon-silicon bonds), thereby forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds) and/or dangling bonds (e.g., dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, comprise reactive sites that extend into one or more surfaces of the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant) may then be introduced to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer within the semiconductor body comprising the reactant.

Abstract: According to the present invention, a method for depositing an ultra-fine crystal particle polysilicon thin film supplies a source gas in a chamber loaded with a substrate to deposit a polysilicon thin film on the substrate, wherein the source gas contains a silicon-based gas, a nitrogen-based gas and a phosphorous-based gas. The mixture ratio of the nitrogen-based gas to the silicon-based gas among the source gas may be 0.03 or lower (but, excluding zero). Nitrogen in the thin film may be 11.3 atomic percent or lower (but, excluding zero).

Abstract: An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the semiconductor substrate in the element region. A gate electrode is formed on the gate insulating film. Source/drain regions are formed to be separated from each other in a surface region of the semiconductor substrate. The source/drain regions sandwich a channel region formed below the gate insulating film. Gate sidewall films are formed on the two side surfaces of the gate electrode. Silicide films are formed on the source/drain regions so as to be separated from the element isolation region.

Abstract: A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same.

Abstract: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.

Abstract: A method of manufacturing nonvolatile memory devices comprises forming a plurality of floating gates spaced from each other over a semiconductor substrate, forming a dielectric layer on a surface of the floating gates, forming a capping layer on a surface of the dielectric layer, adding impurities to the capping layer, and forming a control gate over the capping layer containing the impurities.

Abstract: A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.

Abstract: Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber.

Abstract: A method of forming a doped Group IBIIIAVIA absorber layer for solar cells by reacting a partially reacted precursor layer with a dopant structure. The precursor layer including Group IB, Group IIIA and Group VIA materials such as Cu, Ga, In and Se are deposited on a base and partially reacted. After the dopant structure is formed on the partially reacted precursor layer, the dopant structure and partially reacted precursor layer is fully reacted. The dopant structure includes a dopant material such as Na.

Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface. The method further includes depositing an ink on the front substrate surface in a ink pattern, the ink comprising a set of silicon-containing particles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified film ink pattern.

Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front crystalline substrate surface; and forming a mask on the front crystalline substrate surface, the mask comprising exposed mask areas and non-exposed mask areas. The method also includes exposing the mask to an etchant, wherein porous silicon is formed on the front crystalline substrate surface defined by the exposed mask areas; and removing the mask. The method further includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl3 gas, at a first temperature and for a first time period, wherein a PSG layer is formed on the front substrate surface; and heating the substrate in a drive-in ambient to a second temperature and for a second time period.

Abstract: A method of manufacturing a semiconductor device including an NMOS transistor and a PMOS transistor is provided. The method includes: forming a silicon layer over a substrate through a gate insulating film; forming a first gate electrode and a second gate electrode by patterning the silicon layer, the first gate electrode being a gate electrode of the NMOS transistor, and the second gate electrode being a gate electrode of the PMOS transistor; selectively forming a silicon oxide film on the first gate electrode which is formed of silicon; after the selectively forming the silicon oxide film, forming a first metallic layer formed of a metal capable of forming a silicide over the first and second gate electrodes; and performing a first heat treatment such that a first silicide layer of a silicide of the first metallic layer is formed.

Abstract: A method is described for isotropic or nearly isotropic shallow doping of a non-planar surface exposed in a void. The results of ion implantation, a common doping method, are inherently planar. Some fabrication methods and devices may require doping a surface of a non-planar feature exposed in a void, such as a trench. The feature is doped by flowing a gas which will provide the dopant over the exposed surfaces, or by exposing the surfaces to a plasma including the dopant. The feature may be a patterned feature, including a top surface and a sidewall. In a preferred embodiment, a semiconductor feature having a top surface and a sidewall is exposed in a trench formed in a dielectric, and a gas providing a p-type or n-type dopant is flowed in the trench, providing a p-type or n-type dopant to the semiconductor.

Abstract: The invention relates to a method of doping semiconductor material. Essentially, the method comprises mixing a quantity of particulate semiconductor material with an ionic salt or a preparation of ionic salts. Preferably, the particulate semiconductor material comprises nanoparticles with a size in the range 1 nm to 100 ?m. Most preferably, the particle size is in the range from 50 nm to 500 nm. Preferred semiconductor materials are intrinsic and metallurgical grade silicon. The invention extends to a printable composition comprising the doped semiconductor material as well as a binder and a solvent. The invention also extends to a semiconductor device formed from layers of the printable composition having p and n type properties.

Abstract: The invention relates to a method for simultaneous doping and oxidizing semiconductor substrates and also to doped and oxidized semiconductors substrates produced in this manner. Furthermore, the invention relates to the use of this method for producing solar cells.

Abstract: An impurity region having a box-shaped impurity profile is formed. An impurity introducing method includes a step of introducing a desired impurity into a surface of a solid base body, and a step of radiating plasma to a surface of the solid base body after the impurity introducing step thus forming an impurity profile having an approximately box-shape.

Abstract: Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration of the materials. The nanowires may be between 10 and 30 nm in diameter, formed using a comparable size particle of catalyst material. The nanowires may then be used as part of the channel of a field effect transistor, and the field effect transistor is itself characterized.

Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.

Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.

Abstract: The invention relates to a method for doping a semiconductor material with Cesium, wherein said semiconductor material is exposed to a cesium vapor. Said Cesium vapor is provided by Cesium sublimation from a Cesium alloy. There is also provided an organic light emitting diode comprising at least one layer of a Cesium doped organic semiconductor material, wherein said at least one layer of said Cesium doped organic semiconductor material is doped with Cesium provided by Cesium evaporation of Cesium from a Cesium alloy. The Cesium vapor is preferably provided by Cesium sublimation from a standard organic material deposition evaporator.