Abstract: The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of the p-type field effect transistor; and d) performing annealing, so as to achieve the object of memorizing compressive stress in a channel of a transistor and improving the performance of the transistor. The method according to the present invention memorizes the compressive stress in the channel of the transistor by a stress memorization technique, increases mobility of holes, and improves overall performance of the semiconductor structure.

Abstract: Fabricating a vertical transistor includes providing a structural polymer layer on a substrate. A patterned inorganic thin film is formed on the structural polymer layer, leaving exposed portions of the structural polymer layer not under the inorganic thin film. Exposed portions of the structural polymer layer and portions of the structural polymer layer between the patterned inorganic thin film and the substrate are removed to form a structural polymer post having an inorganic cap that extends beyond an edge of the structural polymer post defining a reentrant profile. A conformal conductive gate layer and a conformal dielectric layer on the gate layer are formed in the reentrant profile. A conformal semiconductor layer is formed on the dielectric layer. First and second electrodes are formed in contact with a first portion (over the cap) and a second portion (not over the post) of the semiconductor layer.

Abstract: A semiconductor device includes: a nitride semiconductor layer; a first silicon nitride film that is formed on the nitride semiconductor layer, has a first opening whose inner wall is a forward tapered shape; a second silicon nitride film that is formed on the first silicon nitride film, and has a second opening whose inner wall is an inverse tapered shape; and a gate electrode formed so as to cover the whole surface of the nitride semiconductor layer exposed on the inside of the first opening; wherein a side wall of the gate electrode separates from the first silicon nitride film and the second silicon nitride film via a cavity.

Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-13) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).

Abstract: A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.

Abstract: Provided is a memory device including a first dielectric layer, a T-shaped gate, two charge storage layers and two second dielectric layers. The first dielectric layer is disposed on a substrate. The T-shaped gate is disposed on the first dielectric layer and has an upper gate and a lower gate, wherein two gaps are present respectively at both sides of the lower gate and between the upper gate and the substrate. The charge storage layers are respectively embedded into the gaps. A second dielectric layer is disposed between each charge storage layer and the upper gate, between each charge storage layer and the lower gate and between each charge storage layer and the substrate.

Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Abstract: A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer.

Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced.

Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.

Abstract: A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 ?m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.

Abstract: A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate.

Abstract: A smooth electrode is provided. The smooth electrode includes at least one metal layer having thickness greater than about 1 micron; wherein an average surface roughness of the smooth electrode is less than about 10 nm.

Abstract: A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acid.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A field-effect transistor with improved moisture resistance without an increase in gate capacitance, and a method of manufacturing the field-effect transistor are provided. The field-effect transistor includes: a T-shaped gate electrode on a semiconductor layer; and a first highly moisture-resistant protective film including one of an insulating film and an organic film having high etching resistance, the first highly moisture-resistant protective film being located above the T-shaped gate electrode, over all of a region in which the T-shaped gate electrode is located. A cavity is located between the semiconductor layer and the first highly moisture-resistant protective film, below a canopy of the T-shaped gate electrode. An end surface of the cavity is closed by a second highly moisture-resistant film.

Abstract: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.

Abstract: A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced.

Abstract: A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acid.

Abstract: Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

Abstract: The present invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a buffer layer formed of a dual-layer structure of a buffer oxide film and a buffer nitride film on a semiconductor substrate formed with a certain lower structure; forming source/drain by performing an ion injection process after forming the buffer layer; defining a gate hole by etching the buffer layer after forming the source/drain; forming a gate oxide film on the defined gate hole; forming a gate material to bury the defined gate hole; forming a T-shape gate electrode through a process of etching the gate material using the buffer nitride film as an etching stop film; and forming a contact hole after forming an inter-layer dielectric on a resulting structure formed with the T-shape gate electrode.

Abstract: A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

Abstract: Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.

Abstract: In one embodiment, a tiered gate structure is provided having a substrate including a source, a drain and a gate thereon. The gate includes an elongated gate foot having a first deposition gate material extending from the substrate, the elongated gate foot having a top portion distal from the substrate. The gate head has a second deposition gate material and includes an elongated portion extending downward from the gate head to connect to the top portion of the elongated gate foot.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A method for fabricating a tiered structure includes forming a gate on a semiconductor substrate. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped and a passivation layer is formed over the gate foot and the substrate. A gate head mask is formed over the gate foot with the gate head mask exposing a portion of the passivation layer on a top portion of the gate foot. The portion of the passivation layer on the top portion of the gate foot is removed to expose the top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film, and a second nitride film, which are formed on a sidewall of an upper portion of the gate electrode, and a gate sidewall insulating film having a two-layered structure formed of the oxide film and the second nitride film, which are formed on a sidewall of a lower portion of the gate electrode. The semiconductor apparatus further comprises a raised source/drain region formed of an impurity region formed in a surface layer of the semiconductor substrate and an impurity region grown on the impurity region.

Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film, and a second nitride film, which are formed on a sidewall of an upper portion of the gate electrode, and a gate sidewall insulating film having a two-layered structure formed of the oxide film and the second nitride film, which are formed on a sidewall of a lower portion of the gate electrode. The semiconductor apparatus further comprises a raised source/drain region formed of an impurity region formed in a surface layer of the semiconductor substrate and an impurity region grown on the impurity region.

Abstract: A Schottky diode includes a first nitride semiconductor layer formed on a substrate and a second nitride semiconductor layer selectively formed on the first nitride semiconductor layer and having a different conductivity type from that of the first nitride semiconductor layer. A Schottky electrode is selectively formed on the first nitride semiconductor layer to come into contact with the top surface of the second nitride semiconductor layer, and an ohmic electrode is formed thereon so as to be spaced apart from the Schottky electrode.

Abstract: A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.

Abstract: A method is provided for making a silicided gate in a semiconductor device. In accordance with the method, a gate (213) is provided which comprises a first portion (214) and a second portion (213). The first portion of the gate has a width w1 and the second portion of the gate has a width w2 as taken along a plane perpendicular to the length of the gate, wherein w2>w1. A layer is silicide (231) is then formed on the second portion.

Abstract: A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the ?-shaped metal gate with nano scale line-width can be formed.

Abstract: Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

Abstract: A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.

Abstract: Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal portion. The vertical portion overlies a channel region in an underlying substrate and has a first width; the horizontal portion has a second greater width. A tensile stressed film is formed overlying the second horizontal portion, and a material having a second Young's modulus less than the first Young's modulus fills the space below the second horizontal portion. The tensile stressed film imparts a stress on the horizontal portion of the gate electrode and this stress is transmitted through the vertical portion to the channel of the device. The stress imparted to the channel is amplified by the ratio of the second width to the first width.

Abstract: A semiconductor component, particularly a pHEMT, having a T-shaped gate electrode deposited in a double-recess structure, is produced with a method with self-adjusting alignment of the recesses and of the T-shaped gate electrode.

Abstract: Methods of forming T-gate structures on a substrate are provided that use only UV-sensitive photoresists. Such methods provide T-gate structures using two lithographic steps using a single wavelength of radiation.

Abstract: A field effect transistor having a T- or ?-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: Polysilicon lines are formed, featuring an upper portion extending beyond the lower portion that defines the required CD. Accordingly, metal silicide layers of increased dimensions can be formed on the upper portion of the polysilicon lines so that the resulting gate structures exhibit a very low final sheet resistance. Moreover, in situ sidewall spacers are realized during the process for forming the polysilicon lines and without additional steps and/or costs.

Abstract: A method of manufacturing a semiconductor device including a gallium nitride related semiconductor. The method include preparing a substrate having surface of a gallium nitride related semiconductor; contacting the surface with atomic nitrogen, which is obtained by decomposing a nitrogen-containing gas in a catalytic reaction, to nitride the surface; and forming, on the surface, a gate electrode and source and drain electrodes opposing each other across the gate electrode.