Multilayer Electrode Patents (Class 438/573)
  • Patent number: 9627553
    Abstract: A SiC Schottky diode which includes a Schottky barrier formed on a silicon face 4H—SiC body.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: April 18, 2017
    Assignee: SILICONIX TECHNOLOGY C.V.
    Inventor: Giovanni Richieri
  • Patent number: 9576958
    Abstract: An approach to forming a semiconductor structure with improved negative bias temperature instability includes forming an interfacial layer on a semiconductor substrate with an nFET and a pFET. The semiconductor structure includes a gate dielectric layer on the interfacial layer and a pFET work function metal layer on a portion of the gate dielectric layer over an area above the pFET. The semiconductor structure includes a nFET work function metal layer on a portion of the gate dielectric layer over an area above the nFET and on the pFET work function metal layer in the area above the pFET. The semiconductor structure includes a gate electrode metal on the nFET work function metal layer where a plurality of fluorine atoms and a plurality of reducing gas atoms are incorporated into at least a portion of the interfacial layer, the gate layer, and a portion of the nFET work function metal.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: February 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan
  • Patent number: 9318344
    Abstract: A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: April 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Daewon Yang
  • Patent number: 9202880
    Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 1, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Adam J. Williams, Dean C. Regan, Joel C. Wong
  • Patent number: 9196492
    Abstract: A method for manufacturing a semiconductor device includes: forming a metal layer on a semiconductor layer; forming a plated layer having a pattern corresponding to a pattern of a gate bus line which couples each gate finger of a plurality of FETs on the metal layer, the pattern corresponding to the pattern of the gate bus line having a deficient part; forming a mask layer which covers the metal layer exposed in the deficient part; and patterning the metal layer by using the plated layer and the mask layer as a mask.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: November 24, 2015
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kiyoshi Kajii
  • Patent number: 9035321
    Abstract: There is provided a semiconductor device including an ohmic junction layer which is excellent in surface flatness and uniformity of composition in an interface with a semiconductor substrate and thus can give a sufficiently high adhesiveness with a Schottky junction layer.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 19, 2015
    Assignee: SHOWA DENKO K.K.
    Inventors: Akihiro Matsuse, Kotaro Yano
  • Patent number: 8940567
    Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: January 27, 2015
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Zhi He, Jianjun Cao
  • Patent number: 8895423
    Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: November 25, 2014
    Assignee: Transphorm Inc.
    Inventor: Yuvaraj Dora
  • Patent number: 8847395
    Abstract: A microelectronic device, including: a substrate and a plurality of metal interconnection levels stacked on the substrate; a first metal line of a given metal interconnection level; a second metal line of another metal interconnection level located above the given metal interconnection level, the first and second lines are interconnected via at least one semiconductor connection element extending in a direction forming a nonzero angle with the first metal lines and the second metal line; and a gate electrode capable of controlling conduction of the semiconductor connection element.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: September 30, 2014
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Thomas Ernst, Paul-Henry Morel, Sylvain Maitrejean
  • Patent number: 8785309
    Abstract: A new method of electrophoretic nanotube deposition is proposed wherein individual nanotubes are placed on metal electrodes which have their length significantly exceeding their width, while the nanotube length is chosen to be close to that of the metal electrode. Due to electrostatic attraction of individual nanotube to the elongated electrode, every nanotube approaching the electrode is deposited along the electrode, since such an orientation is energetically favorable. This method offers opportunity to produce oriented arrays of individual nanotubes, which opens up a new technique for fabrication and mass production of nanotube-based devices and circuits. Several such devices are considered. These are MESFET- and MOSFET-like transistors and CMOS-like voltage inverter.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: July 22, 2014
    Assignee: Nano-Electronic And Photonic Devices And Circuits, LLC
    Inventor: Alexander Kastalsky
  • Publication number: 20140167064
    Abstract: A GaN hetereojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectric layer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 19, 2014
    Applicant: NXP B.V.
    Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Stephan Heil, Jan Sonsky
  • Publication number: 20140092636
    Abstract: A gate electrode is formed above a compound semiconductor stacked structure, and the gate electrode includes a stack of a TaN:Al layer in which Al is solid-dissolved in TaN, a TaAlN layer made of a compound of TaN and Al, and an Al layer.
    Type: Application
    Filed: August 26, 2013
    Publication date: April 3, 2014
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Masahito Kanamura, Jun YOSHIKI
  • Patent number: 8658523
    Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: February 25, 2014
    Assignee: Acorn Technologies, Inc.
    Inventors: Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp
  • Patent number: 8609522
    Abstract: A process for producing a conducting electrode on a substrate, including: depositing a layer made of a dielectric; depositing a protective layer made of the nitride of a metal on the dielectric layer; depositing a functionalization layer made of a material including a chemical species, such that the free enthalpy of formation of the nitride of the species is less, in absolute value, than the free enthalpy of formation of the nitride of the metal of the protective layer over the temperature range between 0° C. and 1200° C.; and annealing the assembly including the protective layer and the funtionalization layer so that the species diffuse from the functionalization layer into the protective layer and the nitrogen atoms migrate from the protective layer into the functionalization layer.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: December 17, 2013
    Assignee: Commissariat à l'énergie atomique et aux ènergies alternatives
    Inventors: Remy Gassilloud, François Martin
  • Patent number: 8580630
    Abstract: Methods for forming a metal gate structure on a substrate are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a dielectric layer formed on the substrate may include depositing a metal layer while providing a process gas comprising oxygen to form an oxygen doped work function layer atop the dielectric layer; and depositing a metal gate layer atop dielectric layer.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: November 12, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jianxin Lei, Xinyu Fu, Srinivas Gandikota, Jian Z. Ren
  • Patent number: 8575012
    Abstract: A semiconductor device production method includes: forming an insulating film on a semiconductor substrate, forming a concave portion in the insulating film, forming a gate insulating film at bottom of the concave portion, the bottom being on the semiconductor substrate; covering an inner wall surface of the concave portion and a top face of the insulating film with a first gate electrode film that is made of an electrically conductive material containing a first metal; covering the first gate electrode film with a covering film of a material having a second melting point higher than a first melting point of the electrically conductive material, leaving part of the side face of the concave portion uncovered; and performing heat treatment following the covering film formation to allow the first gate electrode film to reflow.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: November 5, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaki Haneda
  • Patent number: 8551876
    Abstract: A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: October 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Ren Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh
  • Patent number: 8536036
    Abstract: In a process strategy for forming high-k metal gate electrode structures in an early manufacturing phase, a predoped semiconductor material may be used in order to reduce the Schottky barrier between the semiconductor material and the conductive cap material of the gate electrode structures. Due to the substantially uniform material characteristics of the predoped semiconductor material, any patterning-related non-uniformities during the complex patterning process of the gate electrode structures may be reduced. The predoped semiconductor material may be used for gate electrode structures of complementary transistors.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Jan Hoentschel, Uwe Griebenow, Thilo Scheiper
  • Patent number: 8497553
    Abstract: A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: July 30, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroto Yamagiwa, Shingo Hashizume, Ayanori Ikoshi, Manabu Yanagihara, Yasuhiro Uemoto
  • Patent number: 8486816
    Abstract: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 16, 2013
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Patent number: 8426972
    Abstract: A semiconductor device has: a semiconductor substrate; and an upper surface electrode laminated on an upper surface of the semiconductor substrate, wherein at least one portion of the upper surface electrode includes a first layer formed on an upper surface side of the semiconductor substrate, a second layer formed on an upper surface side of the first layer, a third layer in contact with the upper surface of the second layer, and a fourth layer formed on an upper surface side of the third layer. The first layer is a barrier metal layer. The second layer is an Al (aluminum) layer. The third layer is one of an Al—Si (aluminum-silicon alloy) layer, an Al—Cu (aluminum-copper alloy) layer and an Al—Si—Cu (aluminum-silicon-copper alloy) layer. The fourth layer is a solder joint layer.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: April 23, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Keisuke Kimura
  • Patent number: 8325475
    Abstract: According to one embodiment, an electronic device includes a side wall, an interface component, a partition wall, and a protrusion. The side wall is formed on one of the bottom wall and the top wall of a housing to spatially separate the inside of the housing from the outside. The side wall includes a through opening. The interface component faces the through opening in the housing. The partition wall is formed on the one of the bottom wall and the top wall and coupled perpendicularly to the side wall. The partition wall spatially separates the inside of the housing and a component retainer formed as a cutout or a recess of the housing. The protrusion is formed on the one of the bottom wall and the top wall to be spaced apart from the partition wall. The interface component is held between the partition wall and the protrusion.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: December 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichiro Takeguchi, Shigeo Hayashi
  • Patent number: 8324704
    Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: December 4, 2012
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Hirokazu Fujiwara, Masaki Konishi, Takashi Katsuno, Yukihiko Watanabe
  • Patent number: 8319236
    Abstract: A metallization on a semiconductor substrate is disclosed in the form of a laminate comprising a plurality of layers of a “conducting” metallization for providing electrical conductivity, interspersed with a plurality of layers of another metallization. By providing many layers the thickness of each individual layer can be reduced. Reduction in thickness of each layer leads to a reduction in grain size and a consequent reduction in creep over the lifetime of a device.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: November 27, 2012
    Assignee: Oclaro Technology Limited
    Inventors: Richard Beanland, Stephen Jones, Ian Juland
  • Patent number: 8269220
    Abstract: Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: September 18, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
  • Patent number: 8163572
    Abstract: A method of manufacturing a semiconductor device forms the semiconductor device in a device region of a semiconductor substrate simultaneously with forming a monitor semiconductor device that includes a gate electrode made of silicon containing material arranged on a gate insulating film in a monitor region of the semiconductor substrate, a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. The gate electrode is removed without removing a gate insulating film by applying pyrolysis hydrogen generated by pyrolysis on the monitor semiconductor device in the monitor region, and the gate insulating film is removed by a wet process. Impurities distribution of a silicon active region appearing after the gate electrode is removed is measured and fed back to a semiconductor manufacturing process.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: April 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuo Hashimi, Hidekazu Sato
  • Patent number: 8004022
    Abstract: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: August 23, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Norimasa Yafune, John Kevin Twynam
  • Patent number: 7977761
    Abstract: The present invention provides for an array of nanostructures grown on a conducting substrate. The array of nanostructures as provided herein is suitable for manufacturing electronic devices such as an electron beam writer, and a field emission device.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: July 12, 2011
    Assignee: Smoltek AB
    Inventor: Mohammad Shafiqul Kabir
  • Publication number: 20110147767
    Abstract: There is provided a semiconductor device including an ohmic junction layer which is excellent in surface flatness and uniformity of composition in an interface with a semiconductor substrate and thus can give a sufficiently high adhesiveness with a Schottky junction layer.
    Type: Application
    Filed: August 20, 2009
    Publication date: June 23, 2011
    Applicant: SHOWA DENKO K.K.
    Inventors: Akihiro Matsuse, Kotaro Yano
  • Patent number: 7947521
    Abstract: A method for forming an electrode for Group-III nitride compound semiconductor light-emitting devices includes a step of forming a first electrode layer having an average thickness of less than 1 nm on a Group-III nitride compound semiconductor layer, the first electrode layer being made of a material having high adhesion to the Group-III nitride compound semiconductor layer or low contact resistance with the Group-III nitride compound semiconductor layer and also includes a step of forming a second electrode layer made of a highly reflective metal material on the first electrode layer.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: May 24, 2011
    Assignee: Toyota Gosei Co., Ltd.
    Inventors: Koichi Goshonoo, Miki Moriyama
  • Patent number: 7923362
    Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: April 12, 2011
    Assignee: TELEFUNKEN Semiconductors GmbH & Co. KG
    Inventors: Franz Dietz, Volker Dudek, Tobias Florian, Michael Graf
  • Patent number: 7902055
    Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: March 8, 2011
    Assignee: Texas Instruments Incoprorated
    Inventors: Richard B. Irwin, Tony T. Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer S. Dumin, Patrick J. Jones, Fredric D. Bailey
  • Publication number: 20110008953
    Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.
    Type: Application
    Filed: September 9, 2010
    Publication date: January 13, 2011
    Inventors: Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp
  • Patent number: 7825017
    Abstract: A silicon carbide semiconductor device provided as a semiconductor chip includes a substrate, a drift layer on the substrate, an insulation film on the drift layer, a semiconductor element formed in a cell region of the drift layer, a surface electrode formed on the drift layer and electrically coupled to the semiconductor element through an opening of the insulation film, and a passivation film formed above the drift layer around the periphery of the cell region to cover an outer edge of the surface electrode. The passivation film has an opening through which the surface electrode is exposed outside. A surface of the passivation film is made uneven to increase a length from an inner edge of the opening of the passivation film to a chip edge measured along the surface of the passivation film.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: November 2, 2010
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Masaki Konishi
  • Patent number: 7820540
    Abstract: Metallization contact structures and methods for forming a multiple-layer electrode structure on solar cells include depositing a conductive contact layer on a semiconductor substrate and depositing a metal bearing ink onto a portion of the conductive contact layer, wherein exposed portions of the conductive contact layer are adjacent to the metal bearing ink. The conductive contact layer is patterned by removing exposed portions of the conductive contact layer from the semiconductor substrate. The metal bearing ink is aligned with openings in a dielectric layer of the semiconductor substrate and with unexposed portions of the conductive contact layer. The unexposed portions of the conductive contact layer are interposed between the metal bearing ink and the dielectric layer such that the conductive contact layer pattern is aligned with metal bearing ink. The semiconductor substrate is thermally processed to form a current carrying metal gridline by sintering the metal bearing ink.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: October 26, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Baomin Xu, David K. Fork
  • Patent number: 7816240
    Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: October 19, 2010
    Assignee: Acorn Technologies, Inc.
    Inventors: Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp
  • Patent number: 7800091
    Abstract: A nonvolatile semiconductor memory device includes a first stacked structure in which a plurality of electrode layers are stacked on a substrate via insulating layers, a first resistance changing layer provided on a side surface of the first stacked structure and in contact with the first electrode layers, the first resistance changing layer having a resistance value changing on the basis of an applied voltage, a second electrode layer provided on a side surface of the first resistance changing layer, and a bit line provided on the first stacked structure and electrically connected to the second electrode layer.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: September 21, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kamigaichi, Hirofumi Inoue
  • Patent number: 7777292
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: August 17, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Johji Nishio, Tetsuo Hatakeyama, Takashi Shinohe
  • Patent number: 7759231
    Abstract: A method of forming contacts between at least one metallic layer and at least one semiconductor substrate through at least one layer of dielectric in a semiconductor device. The semiconductor device includes, on at least one base face of the semiconductor substrate, the dielectric layer. The metallic layer is stacked on the dielectric layer. The heated ends of plural protruding elements assembled on a support are brought into contact with the metallic layer simultaneously, thereby creating zones of melted metal under the heated ends of the protruding elements. The melted metal traverses the dielectric and amalgamates with the semiconductor of the substrate at the level of the zones of melted metal, thereby creating the contacts.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: July 20, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Pierre Jean Ribeyron, Emmanuel Rolland
  • Patent number: 7745317
    Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: June 29, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Yuji Okamura, Masashi Matsushita
  • Patent number: 7659154
    Abstract: The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: February 9, 2010
    Assignee: NXP B.V.
    Inventors: Markus Muller, Peter Stolk
  • Patent number: 7655546
    Abstract: A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: February 2, 2010
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Walter Anthony Wohlmuth
  • Patent number: 7642192
    Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: January 5, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kazuo Hashimi, Hidekazu Sato
  • Patent number: 7638415
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: December 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Martin Mollat, Tathagata Chatterjee, Henry L. Edwards, Lance S. Robertson, Richard B. Irwin, Binghua Hu
  • Patent number: 7576706
    Abstract: An image display device includes a driving unit to provide first and second image signals and first and second control signals to display images, a first display unit to display first images in response to the first image signal and the first control signal from the driving unit, a second display unit to display secondary images in response to the second image signal and the second control signal from the driving unit, first data-transfer lines to transfer the second image signal from the driving unit to the second display unit, second data-transfer lines to transfer the second control signal from the driving unit to the second display unit, and a flexible printed circuit board connected between the first and second display units to provide electrical connection between the driving unit and the second display unit.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 18, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Suk Lim, Won-Kyu Lee
  • Patent number: 7528024
    Abstract: The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: May 5, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, James J. Chambers, Mark R. Visokay
  • Publication number: 20090039456
    Abstract: This invention discloses bottom-anode Schottky (BAS) device supported on a semiconductor substrate having a bottom surface functioning as an anode electrode with an epitaxial layer has a same doped conductivity as said anode electrode overlying the anode electrode. The BAS device further includes an Schottky contact metal disposed in a plurality of trenches and covering a top surface of the semiconductor substrate between the trenches. The BAS device further includes a plurality of doped JBS regions disposed on sidewalls and below a bottom surface of the trenches doped with an opposite conductivity type from the anode electrode constituting a junction barrier Schottky (JBS) with the epitaxial layer disposed between the plurality of doped JBS regions. The BAS device further includes an ultra-shallow Shannon implant layer disposed immediate below the Schottky contact metal in the epitaxial layer between the plurality of doped JBS regions.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 12, 2009
    Inventors: Anup Bhalla, Sik K. Lui, Yi Su
  • Patent number: 7452744
    Abstract: A first gate electrode and a second gate electrode are formed on a semiconductor substrate, and then a resist pattern is formed so as to selectively leave open a portion including an overlap between the first and second gate electrodes. Next, the overlap between the gate electrodes is removed through isotropic etching. Etching is carried out at this time by an amount within a range of 140% to 200% of the film thickness of the second gate electrode. Next, a normal inter-layer insulating film and light-shielding film are formed. It is possible to eliminate the overlap between the gate electrodes adjacent to an opening of the light-shielding film, suppress the height of the light-shielding film at that portion, reduce shading for the light condensed by a lens and thereby improve the light condensing efficiency of the lens.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: November 18, 2008
    Assignee: Panasonic Corporation
    Inventors: Ken Henmi, Toshihiro Kuriyama
  • Publication number: 20080237608
    Abstract: A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum.
    Type: Application
    Filed: July 31, 2007
    Publication date: October 2, 2008
    Inventor: Giovanni Richieri
  • Patent number: 7256085
    Abstract: A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentially forming a tunnel insulating film and a charge-storable film so as to cover active regions between the element isolation regions; forming an interlayer insulating film on the charge-storable film; forming plural control gates on the interlayer insulating film in a direction orthogonal to a longitudinal direction of the trenches; among source formation regions and drain formation regions alternately provided between the plural control gates, etching the element isolation insulating film in the source formation regions, using as a mask a resist film having openings in the source formation regions, to expose surfaces of the trenches; and carrying out isotropic plasma ion implantation on the source formation regions to form source diffusion layers in
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: August 14, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhiro Hata, Shinichi Sato, Yukiharu Akiyama