Using Platinum Group Metal (i.e., Platinum (pt), Palladium (pd), Rhodium (rh), Ruthenium (ru), Iridium (ir), Osmium (os), Or Alloy Thereof) Patents (Class 438/580)
  • Patent number: 9721962
    Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 1, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 9673211
    Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 6, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 9178106
    Abstract: A method for treating a LED structure with a substance, the LED structure includes an array of nanowires on a planar support. The method includes producing the substance at a source and causing it to move to the array along a line. The angle between the line followed by the substance and the plane of the support is less than 90° when measured from the center of the support. The substance is capable of rendering a portion of the nanowires nonconductive or less conductive compared to before being treated by the substance.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: November 3, 2015
    Assignee: GLO AB
    Inventors: Scott Brad Herner, Daniel Bryce Thompson, Cynthia Lemay
  • Patent number: 8796808
    Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: August 5, 2014
    Assignee: PFC Device Corp.
    Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
  • Patent number: 8703611
    Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises following steps. A substrate is provided. A sacrificial layer is formed on the substrate. The sacrificial layer is patterned to develop a first opening and a second opening. The first opening corresponds to an exposed portion of the substrate and the second opening corresponds to an unexposed portion of the substrate. A heat procedure is performed. A target material is formed on the exposed portion of the substrate and a rest part of the sacrificial layer. The rest part of the sacrificial layer and parts of the target material on the rest part of the sacrificial layer are removed. A predetermined patterned target material is obtained.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: April 22, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Ming-Kuan Chen
  • Patent number: 8685849
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 1, 2014
    Assignee: Siliconix Technology C. V. IR
    Inventors: Andrea Irace, Giovanni Breglio, Paolo Spirito, Andrea Bricconi, Diego Raffo, Luigi Merlin
  • Patent number: 8455293
    Abstract: A method for processing solar cells comprising: providing a vertical furnace to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing; composing a process chamber loading configuration for solar cell substrates, wherein a size of the solar cell substrates that extends along a first surface to be processed is smaller than a corresponding size of the circular semiconductor wafers, such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber, loading the solar cell substrates into the process chamber; subjecting the solar cell substrates to a process in the process chamber.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: June 4, 2013
    Assignee: ASM International N.V.
    Inventors: Chris G. M. de Ridder, Klaas P. Boonstra, Adriaan Garssen, Frank Huussen
  • Publication number: 20130122695
    Abstract: A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.
    Type: Application
    Filed: January 7, 2013
    Publication date: May 16, 2013
    Applicant: PFC DEVICE CORP.
    Inventor: PFC DEVICE CORP.
  • Publication number: 20130115765
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Application
    Filed: September 25, 2012
    Publication date: May 9, 2013
    Applicant: SILICONIX TECHNOLOGY C.V.IR
    Inventor: SILICONIX TECHNOLOGY C.V.IR
  • Patent number: 8435873
    Abstract: One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: May 7, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Vladimir Frank Drobny
  • Patent number: 8350290
    Abstract: Provided is a light-receiving device which has light-receiving sensitivity superior to that of a conventional Schottky diode type light-receiving device and also has sufficiently-strengthened junction of a Schottky electrode. A first contact layer formed of AlGaN and having conductivity, a light-receiving layer formed of AlGaN, and a second contact layer formed of AlN and having a thickness of 5 nm are epitaxially formed on a predetermined substrate in the stated order, and a second electrode is brought into Schottky junction with the second contact layer, to thereby form MIS junction. Further, after the Schottky junction, heat treatment is performed under a nitrogen gas atmosphere at 600° C. for 30 seconds.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: January 8, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Mitsuhiro Tanaka
  • Patent number: 8349679
    Abstract: According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film 11, a crystalline conductive film 21, a first conductive film 23, a ferroelectric film 24 and a second conductive film 25 on a silicon substrate I in sequence, forming a conductive cover film 18 on the second conductive film 25, forming a hard mask 26a on the conductive cover film 18, forming a capacitor upon etching the conductive cover film 18, the second conductive film 25, the ferroelectric film 24 and the first conductive film 23 using the hard mask 26a as an etching mask in areas exposed from the hard mask 26a, and etching the hard mask 26a and the crystalline conductive film 21 exposed from the lower electrode 23a using an etching condition under which the hard mask 26a is etched.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8093071
    Abstract: According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film 11, a crystalline conductive film 21, a first conductive film 23, a ferroelectric film 24 and a second conductive film 25 on a silicon substrate 1 in sequence, forming a conductive cover film 18 on the second conductive film 25, forming a hard mask 26a on the conductive cover film 18, forming a capacitor upon etching the conductive cover film 18, the second conductive film 25, the ferroelectric film 24 and the first conductive film 23 using the hard mask 26a as an etching mask in areas exposed from the hard mask 26a, and etching the hard mask 26a and the crystalline conductive film 21 exposed from the lower electrode 23a using an etching condition under which the hard mask 26a is etched.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: January 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8084342
    Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: December 27, 2011
    Assignee: Avolare 2, LLC
    Inventors: John P. Snyder, John M. Larson
  • Patent number: 7955961
    Abstract: A trench-type Schottky semiconductor device and a method for fabricating the trench-type Schottky semiconductor device are disclosed. The method includes the steps of forming an epitaxial (EPI) layer atop a silicon substrate, forming a nitride layer atop the EPI layer, patterning a plurality of windows in the nitride layer into an active region and a termination region, forming a plurality of trenches in the active and termination regions such that the plurality of trenches in the termination regions are spaced apart from each other so as to form a plurality of mesas, lining the first type of trenches with a gate oxide layer, and converting the mesas to oxide mesas; and then applying a barrier layer metal to the mesas in the device active area and in the termination trenches.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: June 7, 2011
    Assignee: International Rectifier Corporation
    Inventor: Giovanni Richieri
  • Patent number: 7935620
    Abstract: Methods and apparatus are described for semiconductor devices. A method comprises providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor, and without removing the first mask, forming a Schottky contact of a first material on the exposed portion of the semiconductor, then removing the first mask, and using a further mask, forming a step-gate conductor of a second material electrically coupled to the Schottky contact and overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: May 3, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
  • Patent number: 7923362
    Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: April 12, 2011
    Assignee: TELEFUNKEN Semiconductors GmbH & Co. KG
    Inventors: Franz Dietz, Volker Dudek, Tobias Florian, Michael Graf
  • Patent number: 7901545
    Abstract: An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a process which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang within a vacuum chamber. The iPVD system is operated at low target power and high pressure >50 mT to sputter material from the target. RF energy is coupled into the chamber to form a high density plasma. A small RF bias (less than a few volts) can be applied to aid in enhancing the coverage, especially at the bottom.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: March 8, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Frank M. Cerio, Jr., Jacques Faguet, Bruce D. Gittleman, Rodney L. Robison
  • Patent number: 7902055
    Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: March 8, 2011
    Assignee: Texas Instruments Incoprorated
    Inventors: Richard B. Irwin, Tony T. Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer S. Dumin, Patrick J. Jones, Fredric D. Bailey
  • Patent number: 7749877
    Abstract: A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and an ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form and SiO2 passivation layer to improve the self aligned process.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: July 6, 2010
    Assignee: Siliconix Technology C. V.
    Inventors: Rossano Carta, Carmelo Sanfilippo
  • Patent number: 7732301
    Abstract: A method of making a bonded intermediate substrate includes forming a weak interface in a GaN source substrate by implanting ions into an N-terminated surface of the GaN source substrate, bonding the N-terminated surface of the GaN source substrate to a handle substrate, and exfoliating a thin GaN single crystal layer from the source substrate such that the thin GaN exfoliated single crystal layer remains bonded to the handle substrate and a Ga-terminated surface of the thin GaN single crystal layer is exposed. The method further includes depositing a capping layer directly onto the exposed surface of the thin GaN single crystal layer, and annealing the thin GaN single crystal layer in a nitrogen containing atmosphere after depositing the capping layer. The in-plane strain present in the thin GaN single crystal layer after the annealing is reduced relative to an in-plane strain present in said layer prior to the annealing.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: June 8, 2010
    Inventors: Thomas Henry Pinnington, James M. Zahler, Young-Bae Park, Corinne Ladous, Sean Olson
  • Patent number: 7669320
    Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: March 2, 2010
    Assignee: Amitec-Advanced Multilayer Interconnect Technologies Ltd.
    Inventors: Dror Hurwitz, Mordechay Farkash, Eva Igner, Boris Statnikov, Benny Michaeli
  • Patent number: 7588667
    Abstract: An iPVD system is programmed to deposit a barrier and/or seed layer using a Ru-containing material into high aspect ratio nano-size features on semiconductor substrates using a process which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang within an IPVD processing chamber. In the preferred embodiment, an IPVD apparatus having a frusto-conical ruthenium target equipped with a high density ICP source is provided.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: September 15, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Frank M. Cerio, Jr.
  • Publication number: 20090224355
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Application
    Filed: March 24, 2008
    Publication date: September 10, 2009
    Applicant: SILICONIX TECHNOLOGY C. V. IR
    Inventors: Andrea Irace, Giovanni Breglio, Paolo Spirito, Andrea Bricconi, Diego Raffo, Luigi Merlin
  • Patent number: 7553746
    Abstract: A method for manufacturing electrodes on a semiconducting material of type II-VI or on a compound of this material. The electrodes are preferably in gold or platinum and are formed by electrochemical deposition of gold or platinum from a solution of gold or platinum chloride in pure hydrochloric acid.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: June 30, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Gérard Petroz
  • Publication number: 20080230804
    Abstract: A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.
    Type: Application
    Filed: February 25, 2008
    Publication date: September 25, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi Nishi, Takashi Yamauchi, Yoshinori Tsuchiya, Junji Koga
  • Patent number: 7276796
    Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: October 2, 2007
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Nancy R. Klymko, Christopher C. Parks, Keith Kwong Hon Wong
  • Publication number: 20070212862
    Abstract: A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and a ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form an SiO2 passivation layer to improve the self aligned process.
    Type: Application
    Filed: March 6, 2007
    Publication date: September 13, 2007
    Inventors: Rossano Carta, Carmelo Sanfilippo
  • Patent number: 7157383
    Abstract: After cleaning a surface of a silicon substrate (1), impurities and natural oxide film existing on the silicon substrate (1) are removed by soaking the silicon substrate (1) in a 0.5%-by-volume HF aqueous solution for 5 minutes. The silicon substrate (1) is rinsed (cleaned) with ultrapure water for five minutes. Then, the silicon substrate (1) is soaked for 30 minutes in azeotropic nitric acid heated to an azeotropic temperature of 120.7° C. In this way, an extremely thin chemical oxide film (5) is formed on the surface of the silicon substrate (1). Subsequently, a metal film (6) (aluminum-silicon alloy film) is deposited, followed by heating in a hydrogen-containing gas at 200° C. for 20 minutes. Through the heat processing in the hydrogen-containing gas, hydrogen reacts with interface states and defect states in the chemical oxide film (5), causing disappearance of the interface states and defect states. As a result, the quality of the film can be improved.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: January 2, 2007
    Assignee: Japan Science and Technology Agency
    Inventor: Hikaru Kobayashi
  • Patent number: 6872644
    Abstract: A semiconductor device includes source and drain contact regions which include a non-compounded combination of a semiconductor material and at least one metal. The metal may include an elemental metal, such as gold or aluminum, or may include an intermetallic. The contact regions may be formed by depositing a limited amount of the at least one metal on a source and a drain of the device, and annealing the device to induce diffusion of the at least one metal into the source and drain. The annealing time and temperature may be selected to limit diffusion of the at least one metal.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: March 29, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew S. Buynoski, Witold P. Maszara
  • Patent number: 6852612
    Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: February 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
  • Patent number: 6846731
    Abstract: In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: January 25, 2005
    Assignee: Rutgers, The State University of New Jersey
    Inventors: Yicheng Lu, Haifeng Sheng, Sriram Muthukumar, Nuri William Emanetoglu, Jian Zhong
  • Patent number: 6825073
    Abstract: A Schottky diode structure and a method of making the same are disclosed. The method comprises following steps: firstly, a semiconductor substrate having a first conductive layer and an epi-layer doped with the same type impurities is provided. Then a first oxide layer is form on the epi layer. A patterning step to pattern first oxide layer and recess the epi layer (optional) is then followed to define guard rings. After stripping the photoresist pattern, a polycrystalline silicon layer formation is then followed. A boron and/or BF2+ ion implant is then performed. Subsequently, a high temperature drive in process and oxidation process to oxidize the polycrystalline silicon layer and drive ions is then carried out. A second mask and etch steps are then performed to open the active regions. A metallization process is then done. A third mask and etch steps are then implemented to define anode. Finally, a backside metal layer is then formed and serves as a cathode.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: November 30, 2004
    Assignee: Chip Integration Tech Co., Ltd.
    Inventor: Shye-Lin Wu
  • Patent number: 6809212
    Abstract: This invention relates to liquid cyclopentadienyltrimethylplatinum compounds selected from (isopropylcyclopentadienyl)trimethylplatinum and (tert-butylcyclopentadienyl)trimethylplatinum. This invention also relates to a process for producing a film, coating or powder by decomposing a cyclopentadienyltrimethylplatinum compound precursor selected from (isopropylcyclopentadienyl)trimethylplatinum and (tert-butylcyclopentadienyl)-trimethylplatinum, thereby producing the film, coating or powder. This invention further relates to a one pot method for producing an organometallic compound comprising reacting a metal source compound, an alkylating agent and a cyclopentadienyl compound under reaction conditions sufficient to produce said organometallic compound.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: October 26, 2004
    Assignee: Praxair Technology, Inc.
    Inventors: Scott Houston Meiere, Cynthia A. Hoover
  • Publication number: 20040161892
    Abstract: The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to release metal from the precursor, and subsequently the released metal is deposited over the semiconductor substrate. The invention also includes capacitor constructions, and methods of forming capacitor constructions.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 19, 2004
    Inventor: Haining Yang
  • Patent number: 6734086
    Abstract: A WN film serving as an adhesive layer is deposited over the sidewalls and bottom surface of a hole in a silicon oxide film where an information storage capacitor is to be formed. A Ru film to serve as a lower electrode for the information storage capacitor is formed above the WN film by CVD using Ru(HFAC)3, H2O and H2 as ingredients, so that a ratio of partial pressure of H2O to H2 is controlled to be in the area below a curve (a). When the Ru film is formed by CVD utilizing hydrolysis, the film quality of the Ru film can be enhanced. The ratio of partial pressure of H2O to H2 is controlled, whereby oxidation of the Ru film can be suppressed. When it is controlled to be in the area below a curve (b) to form the Ru film, oxidation of the WN film can be suppressed.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: May 11, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Masayuki Suzuki
  • Patent number: 6727194
    Abstract: A system and method for isothermally distributing a temperature across a semiconductor device. A furnace assembly is provided, which includes a processing tube configured to removably receive a wafer carrier having a full compliment of semiconductor wafers. A heating assembly is provided which can include a resistive heating element positioned to heat air or other gases allowed to enter the process tube. The wafer carrier and heating assembly are vertically raised into a position within the process tube. Once the heating assembly forms a seal with the process tube, the process tube is exhausted and purged of air. Gas is then allowed to flow into the process tube and exchange heat with the heating element. The heated gas circulates through the process tube to convectively raise the temperature of the wafers.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: April 27, 2004
    Assignee: WaferMasters, Inc.
    Inventor: Woo Sik Yoo
  • Patent number: 6699775
    Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or Palladium contact layer.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: March 2, 2004
    Assignee: International Rectifier Corporation
    Inventors: Igor Bol, Iftikhar Ahmed
  • Patent number: 6683001
    Abstract: A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: January 27, 2004
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Eun-ae Chung, Doo-sup Hwang, Cha-young Yoo
  • Publication number: 20030235936
    Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.
    Type: Application
    Filed: May 16, 2003
    Publication date: December 25, 2003
    Inventors: John P. Snyder, John M. Larson
  • Patent number: 6656823
    Abstract: Method for forming a Schottky contact in a semiconductor device includes a step of preparing an n type GaN group compound semiconductor layer, such as AlxGa1-xN and InxGa1-xN. At least one metal layer including a ruthenium component layer is formed on the n type GaN group compound semiconductor layer as a rectifying junction metal. The rectifying junction metal may be used as a gate of a field effect transistor, or an electrode of a Schottky diode. The ruthenium oxide has a low cost, is stable to heat and chemical, and has excellent electric characteristics. The application of the ruthenium oxide to the rectifying junction metal enhances performances, such as UV ray detection, of electronic devices and optical devices operable at an elevated temperature.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: December 2, 2003
    Assignee: LG Electronics Inc.
    Inventors: Suk Hun Lee, Yong Hyun Lee, Jung Hee Lee, Sung Ho Hahm
  • Patent number: 6551932
    Abstract: A method for forming a metal line of a semiconductor device is disclosed, in which a Cu thin film is deposited on a diffusion barrier film after a chemical enhancer and plasma are applied thereon, thereby improving fill characteristics of a contact hole having an ultra-fine structure. The method for forming a metal line in a semiconductor device includes the steps of forming an interlevel insulating film on a semiconductor substrate having a predetermined lower structure, forming a damascene pattern in the interlevel insulating film, forming a diffusion barrier film on a whole structure having the damascene pattern, applying a chemical enhancer on the diffusion barrier film to form a chemical enhancer film on the diffusion barrier film, performing plasma treatment, forming a Cu thin film on the whole structure to fill the damascene pattern, and performing a polishing process to expose an upper surface of the interlevel insulating film so that the Cu thin film only remains within the damascene pattern.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: April 22, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Gyu Pyo
  • Patent number: 6509234
    Abstract: A method of forming a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET). The method includes forming a T-shaped gate electrode formed at least in part in a recess formed in a layer of semiconductor material and over a body region that is disposed between a source and a drain. The method includes spacing the gate electrode from the body by a gate dielectric made from a high-K material.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: January 21, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Publication number: 20030013284
    Abstract: Power combining amplifiers using two different monocrystalline materials in a monolithic device are provided. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
    Type: Application
    Filed: July 16, 2001
    Publication date: January 16, 2003
    Applicant: MOTOROLA, INC.
    Inventors: Rudy M. Emrick, Nestor J. Escalera
  • Patent number: 6506676
    Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: January 14, 2003
    Assignee: Hynix Semiconductor Inc
    Inventors: Dae Gyu Park, Tae Ho Cha, Se Aug Jang, Heung Jae Cho, Tae Kyun Kim, Kwan Yong Lim, In Seok Yeo, Jin Won Park
  • Patent number: 6495423
    Abstract: An electronic power device is integrated monolithically in a semiconductor substrate. The device includes a power region, itself having at least one P/N junction provided therein which comprises a first semiconductor region with a first type of conductivity extending into the substrate from the top surface of the device and being diffused into a second semiconductor region with the opposite conductivity from the first; and an edge protection structure of substantial thickness and limited planar size incorporating at least one trench filled with dielectric material.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: December 17, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventor: Salvatore Leonardi
  • Patent number: 6486524
    Abstract: A FRED device having an ultralow Irr employs a contact layer which contacts spaced P diffusions in an N type silicon substrate and also contacts the silicon surface spanning between the P diffusions. The contact layer is formed of a contact having a lower barrier height than the conventional aluminum, and is palladium silicide with a top contact layer of aluminum.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: November 26, 2002
    Assignee: International Rectifier Corporation
    Inventor: Iftikhar Ahmed
  • Patent number: 6448162
    Abstract: A method for producing a Schottky diode formed of a doped guard ring in an edge area of the Schottky contact is described. The guard ring is produced by depositing a high barrier material, especially made of platinum, on the surface of the semiconductor layer. The surface is provided with a structured masking layer beforehand, and which is subsequently etch-backing.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: September 10, 2002
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Losehand, Hubert Werthmann
  • Publication number: 20020102826
    Abstract: A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.
    Type: Application
    Filed: December 18, 2001
    Publication date: August 1, 2002
    Inventors: Yasuhiro Shimamoto, Masahiko Hiratani, Yuichi Matsui, Satoshi Yamamoto, Toshihide Nabatame, Toshio Ando, Hiroshi Sakuma, Shinpei Iljima
  • Publication number: 20020086504
    Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a NMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 4, 2002
    Inventors: Dae Gyu Park, Tae Ho Cha, Se Aug Jang, Heung Jae Cho, Tae Kyun Kim, Kwan Yong Lim, In Seok Yeo, Jin Won Park