Method for processing solar cell substrates
A method for processing solar cells comprising: providing a vertical furnace to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing; composing a process chamber loading configuration for solar cell substrates, wherein a size of the solar cell substrates that extends along a first surface to be processed is smaller than a corresponding size of the circular semiconductor wafers, such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber, loading the solar cell substrates into the process chamber; subjecting the solar cell substrates to a process in the process chamber.
Latest ASM International N.V. Patents:
This application is a divisional application under §1.53(b) of prior application Ser. No. 12/814,899, filed Jun. 14, 2010, entitled: Method for Processing Solar Cell Substrates, the entire disclosure of which is incorporated by reference herein.FIELD OF THE INVENTION
The present invention relates to the field of processing of planar thin semiconductor substrates such as solar cells, and more in particular to the processing of solar cell substrates in a vertical furnace.BACKGROUND
It is commonly known that different kinds of furnaces may be used to process substrates such as substantially circular wafers for integrated circuit processing. A first kind of furnace comprises a horizontal furnace having a process chamber that substantially extends in a horizontal direction. To process said circular wafers, the wafers are loaded into the process chamber such that the respective wafers are oriented substantially vertically and arranged substantially parallel. Another kind of furnace comprises a vertical furnace with a process chamber arranged in said furnace such that a central axis of the process chamber substantially coincides, or at least extends in a substantially similar direction, with a central axis of the vertical furnace. Before processing wafers in a vertical furnace, the wafers are provided in a loading configuration wherein the wafers are substantially horizontally oriented and are mutually spaced in a vertical direction wherein the centre points of the wafers are approximately positioned on the central axis of the process chamber. Vertical furnaces usually have a load size of 100-150 wafers that are spaced apart such that during processing of the respective wafers the entire surface of each substrate can be subjected to the process. In order to enable the substrate to be exposed to one or more volatile precursors, which may react and/or decompose on the substrate surface to produce a desired thin film, a certain minimal space needs to be available between adjacent substrates. Consequently, the load size of vertical furnaces is limited and determined by the size of the respective furnace and kind of process used to apply a thin film on the wafers provided in said furnace. At the same time, a vertical furnace can be automated more easily than a horizontal furnace.
Due to increasing demand of thin semiconductor substrates such as solar cells, it is desired to enhance the throughput of substrates to be processed in such a vertical furnace. Therefore, it is an object of the present invention to provide for an improved method to process planar thin semiconductor substrates such as solar cells in a known furnace. More in particular an object of the invention is to provide a method to process solar cells in a vertical furnace with an increased throughput.SUMMARY OF THE INVENTION
According to one aspect of the invention a method for processing solar cells is provided. The method may comprise providing a vertical furnace configured for batch processing. Said vertical furnace may be provided with a substantially cylindrical, vertically extending process chamber that is adapted to receive an array of circular semiconductor wafers for integrated circuit processing. The method may further comprise composing a suitable process chamber loading configuration for solar cell substrates having a first surface to be processed. A size of the solar cell substrates that extends along the first surface is smaller than a corresponding size of said circular semiconductor wafers such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber. The loading configuration may comprise multiple arrays of solar cell substrates, wherein each array comprises a plurality of solar cell substrates that are substantially vertically oriented and substantially horizontally spaced apart, wherein the respective arrays are provided at a plurality of levels located along a central axis of the process chamber in the vertical furnace. A number of solar cell substrates that can be accommodated in the process chamber may be substantially larger than a number of circular semiconductor wafers. The method may also comprise loading the solar cell substrates into the process chamber of the vertical furnace. Subsequently, the solar cell substrates may be subjected to a process in the process chamber.
By using the proposed method to process solar cell substrates, the prejudice that large industrial vertical furnaces are only suitable to process a single array of horizontally oriented and vertically spaced semiconductor wafers for integrated circuit processing is overcome. The vertically extending process chamber that is arranged in a known vertical furnace may be loaded such that, surprisingly, multiple arrays of solar cell substrates may be processed in a single batch, thereby maintaining the advantages of a vertical furnace and increasing the amount of substrate surfaces that can be processed at the same time. Consequently, by using the provided method, solar cells may be produced in a cost efficient way in a furnace that can be automated in a simple manner.
With regard to the state of the art, the following is noted.
U.S. Pat. No. 6,335,295 discloses a method for performing wet oxidation for forming an oxygen containing layer on a semiconductor surface. The furnace comprises a process chamber adapted to receive wafers that are supported on a quartz boat. Said boat is a ladder arrangement of horizontal quartz wafer support structures cut or held in place by three or more vertical rails. The quartz boat may hold between 100 and 200 wafers, in one or more vertically spaced arrays of wafers, arranged around a central vertical gas inlet column.
U.S. Pat. No. 4,545,327 shows a chemical vapour deposition device having a dome shaped deposition reaction chamber with spaced heating elements that are selected to provide controlled temperature condition within the reaction chamber. The chamber is adapted to receive vertically oriented substrates such as semiconductor wafers that are supported on boats resting on rods on the chamber base.
Furthermore, U.S. Pat. No. 4,738,618 discloses a vertically oriented thermal processor for the processing of silicon or gallium arsenide wafers or substrates. The processor comprises a load chamber adapted to receive a wafer boat and silicon or gallium, arsenide wafers or substrates provided in a single array.
The mentioned state of the art documents fail to disclose a loading configuration especially suitable for processing a large load size of relatively small solar cell substrates in a vertical furnace.
The aforementioned and other features and advantages of the invention will be more fully understood from the following detailed description of certain embodiments of the invention, taken together with the accompanying drawings, which are meant to illustrate and not to limit the invention.
It is noted that identical or corresponding elements in the different drawings are indicated with identical or corresponding reference numerals.DETAILED DESCRIPTION
The entire disclosure of U.S. application Ser. No. 12/814,899, filed Jun. 14, 2010, is incorporated by reference herein.
It is noted that throughout this application, the term “imaginary line” refers to different kinds of lines for instance a substantially straight line or a substantially curved line, such as a substantially arc shaped or circular line. Thus, the term “imaginary line” has to be interpreted in a broad manner and is not limited to solely straight lines. Furthermore, if two lines are arranged parallel it is to be understood that said respective lines extend in a substantially similar direction but at mutual distance.
The loading configuration 14 may be provided by using a substrate rack 20 as shown in
The proposed method may comprise subjecting the solar cell substrates 6 to an atomic layer deposition (ALD) process. However, it may be possible to subject the solar cell substrates 6 provided in the vertical furnace 1 to other processes as well, such as a POCl3 pre deposition step or an annealing process step. When the solar cell substrate 6 is to be provided with a film layer by means of ALD, it is possible to limit the spacing p between adjacent substrates 6. Deposition with ALD allows for the deposition of a thin film layer in a precisely controlled way. Due to the fact that ALD is a deposition process which deposits one atomic layer at a time through chemisorption until saturation of the surface to be processed, the spacing p may for instance be smaller than 5 mm, for instance smaller than 3 mm and be approximately 2 mm. Consequently, a maximum amount of solar cell substrates 6 may be provided in the loading configuration 14 according to the proposed method. When using a spacing p of approximately 2 mm, relatively thin solar cell substrates 6 that may bend somewhat may still be handled in a desired manner.
By providing a dual batch system, the method as proposed can provide an increased throughput of processed solar cell substrates 6. The first batch of solar cell substrates 6 can be processed. After processing, the first batch of substrates 6 is removed from the process chamber 10 for cool down. When sufficiently cooled down, the substrates 6 can be unloaded and new substrates 6 to be processed can be loaded. Meanwhile the second batch of substrates 6 is inserted in the process chamber 10 to be processed while the first batch is cooling down, unloaded and a new batch is loaded.
A third example of a loading configuration 214 according to the method for processing solar cell substrates 6 is shown in
The loading configuration 214 as shown in
Furthermore, the adjacent arrays 216 of the same level 225 partially overlap each other, as is clearly visible in
Although in the example shown in
In the abovementioned examples, the solar cell substrates 6 are substantially vertically oriented at all times. Since the solar cell substrates 6 are relatively thin and thus may be bend easily, the vertical orientation may prevent undesired breakage of the solar cell substrates 6 during processing.
The last example of a loading configuration 314 of the provided method for processing solar cell substrates is shown in
The substrates can be regular semiconductor wafers wherein a p/n junction is formed between the front and rear surface of the wafer. Alternatively, the substrates can be semiconductor wafers in accordance with the sliver technology as described in US Patent Application Publication No. 2004/0097012. In this technology a plurality of parallel elongated slots are formed at least partly through a semiconductor wafer to form a series of semiconductor strips or slivers. The width of the slots and the thickness of the strips are selected such that the thickness of the wafer is larger than the sum of the slot width and the strip thickness. Cells produced by this method are bifacial—that is, these respond equally well to sunlight impinging on either surface. The slivers are preferably processed when still supported in the wafer. ALD is a suitable technology to form a uniform passivation layer on both the sliver sidewall surfaces down the narrow slots because of the self limiting nature of the process. After completion of the process, the slivers are cut from the wafer and laid flat side by side, resulting in a solar cell surface area that is larger than the original semiconductor wafer.
Although illustrative embodiments of the present invention have been described above, in part with reference to the accompanying drawings, it is to be understood that the invention is not limited to these embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. It will be clear, for example, that the multiple arrays can be provided in a different configuration, for instance due to a certain design of the boat or rack, or depending on the kind, shape and dimensions of the solar cell substrates to be processed. Furthermore, the rack or boat may have a different construction, for instance a different rod assembly comprising a different amount of rods and different receiving openings adapted to receive the respective solar cell substrates. The solar cell substrates of different adjacent arrays may not overlap or may at least partially overlap. The pitch or spacing between adjacent solar cell substrates may be determined dependent on the kind of process to be used to apply the thin film on the surface of the solar cell substrate. Loading and unloading of the boat or rack may be conducted in different manners, depending on the production process of which the vertical furnace provides a process step.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment in the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, it is noted that particular features, structures or characteristics of one or more embodiments may be combined in any suitable manner to form new, not explicitly described embodiments.
1. A method for processing solar cells comprising:
- providing a vertical furnace configured for batch processing, the furnace having a substantially cylindrical process chamber adapted to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing;
- composing a process chamber loading configuration for the solar cell substrates having a first surface to be processed, wherein a size of the solar cell substrates that extends along the first surface is smaller than a corresponding size of the circular semiconductor wafers, wherein the loading configuration comprises multiple arrays of solar cell substrates, wherein each array comprises a plurality of solar cell substrates that are substantially horizontally oriented and substantially vertically spaced apart, wherein the respective arrays extend in a direction substantially parallel to a central axis of the process chamber in the vertical furnace and wherein a number of solar cell substrates that can be accommodated in the process chamber is substantially larger than a number of circular semiconductor wafers;
- loading the solar cell substrates into the process chamber;
- subjecting the solar cell substrates to a process in the process chamber.
2. Method according to claim 1, wherein adjacent arrays in the loading configuration partially overlap each other, such that solar cell substrates of a first array at least partially extend between two adjacent solar cell substrates of a second adjacent array.
3. Method according to claim 1, wherein solar cell substrates of a first array do not overlap adjacent solar cell substrates of an adjacent array.
4. Method according to claim 1, wherein the solar cell substrates in the process chamber are subjected to an atomic layer deposition (ALD) process to provide a thin film on the solar cell substrate surface.
5. Method according to claim 1, wherein the array is a stack of mutually spaced and substantially parallel arranged solar cell substrates.
6. Method according to claim 1, wherein a centre point of each solar cell substrate of an array is located on an imaginary line that extends substantially perpendicular to the solar cell surface, wherein the imaginary lines of the respective arrays extend, preferably substantially parallel at mutual distance.
7. Method according to claim 1, wherein the multiple arrays provided along the central axis of the process chamber together form a first set of arrays, wherein the loading configuration further comprises at least a second set of arrays, which second set also comprises a plurality of arrays located at a plurality of levels located along the central axis, wherein the first set and the second set are horizontally displaced relative to each other.
8. Method according to claim 1, wherein a space between adjacent solar cell substrates of an array is smaller then 5 mm.
9. Method according to claim 1, wherein a space between adjacent solar cell substrates of an array is smaller than 3 mm.
10. Method according to claim 1, wherein a space between adjacent solar cell substrates of an array is approximately 2 mm.
11. Method according to claim 1, wherein an array of solar cell substrates is loaded into a boat at a location horizontally displaced from the process chamber position, wherein the boat loaded with substrates is subsequently loaded into the process chamber.
12. Method according to claim 1, wherein the solar cell substrates have a circular or square shape.
|4545327||October 8, 1985||Campbell et al.|
|4721427||January 26, 1988||Sanders et al.|
|4738618||April 19, 1988||Massey et al.|
|5125359||June 30, 1992||Barale et al.|
|5169478||December 8, 1992||Miyamoto et al.|
|6335295||January 1, 2002||Patel|
|20090035946||February 5, 2009||Pierreux et al.|
|20090294777||December 3, 2009||Cheng et al.|
|20110306217||December 15, 2011||Sato|
|20120258414||October 11, 2012||Matsuura et al.|
|WO 89/01054||February 1989||WO|
Filed: Nov 6, 2012
Date of Patent: Jun 4, 2013
Patent Publication Number: 20130065352
Assignee: ASM International N.V. (Almere)
Inventors: Chris G. M. de Ridder (Almere), Klaas P. Boonstra (Almere), Adriaan Garssen (Almere), Frank Huussen (Almere)
Primary Examiner: Julio J Maldonado
Assistant Examiner: Shantanu C Pathak
Application Number: 13/669,550
International Classification: H01L 21/00 (20060101);