Silicide Patents (Class 438/581)
  • Patent number: 10249542
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a first channel region of the second semiconductor fin. A first doped region is formed on the first semiconductor fin, adjacent to the first gate. A second doped region is formed in a top portion of the first doped region and a third doped region is formed in a top portion of the second semiconductor fin. The third doped region is removed to form a recess and the recess is filled with a fourth doped region.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Zuoguang Liu, Gen Tsutsui, Heng Wu
  • Patent number: 10083822
    Abstract: The invention relates to a physical vapor deposition coating device (1), comprising a process chamber (2) with an anode (3) and a consumable cathode (4) to be consumed by an electrical discharge for coating a substrate located within the process chamber (2). The coating device (1) further includes a first electrical energy source (5) being connected with its negative pole to said consumable cathode (4), and a second electrical energy source (6) being connected with its positive pole to said anode (3). According to the invention, a third electrical energy source (7) is provided being connected with its negative pole to a source cathode (8) which is different from the consumable cathode (4). In addition, the invention relates to a physical vapor deposition method for coating a substrate.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: September 25, 2018
    Assignee: OERLIKON SURFACE SOLUTIONS AG, PFAEFFIKON
    Inventors: Jones Alami, Georg Erkens, Tariq Rasa, Jörg Vetter
  • Patent number: 9865535
    Abstract: A semiconductor device includes a planar interconnection layer formed on a substrate and made of a semiconductor, a first pillar-shaped semiconductor layer formed on the interconnection layer, a semiconductor-metal compound layer formed so as to cover the entire upper surface of the interconnection layer except for a bottom portion of the first pillar-shaped semiconductor layer, a first gate insulating film surrounding the first pillar-shaped semiconductor layer, a first gate electrode surrounding the first gate insulating film, and a first gate line connected to the first gate electrode.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: January 9, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura, Nozomu Harada
  • Patent number: 9337185
    Abstract: A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: May 10, 2016
    Assignee: Infineon Technologies AG
    Inventors: Frank Pfirsch, Dorothea Werber, Carsten Schaeffer
  • Patent number: 9093552
    Abstract: A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: July 28, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Fabrice Nemouchi, Patrice Gergaud, Thierry Poiroux, Bernard Previtali
  • Patent number: 8937343
    Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: January 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hyuk Kim, Dongsuk Shin, Hoi Sung Chung, Naein Lee
  • Patent number: 8895424
    Abstract: A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and an ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form an SiO2 passivation layer to improve the self aligned process.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: November 25, 2014
    Assignee: Siliconix Technology C. V.
    Inventors: Rossano Carta, Carmelo Sanfilippo
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8859408
    Abstract: Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Clemens Fitz, Tom Herrmann
  • Patent number: 8785310
    Abstract: A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 22, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Toshio Hasegawa, Kunihiro Tada, Hideaki Yamasaki, David L. O'Meara, Gerrit J. Leusink
  • Patent number: 8748246
    Abstract: A transistor includes a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. An independent work function adjustment process implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants lanthanide series dopants into a gate polysilicon layer of a NMOS transistor.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Manfred Ramin, Michael Pas
  • Patent number: 8664057
    Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Pal, Sven Beyer, Andy Wei, Richard Carter
  • Patent number: 8647971
    Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: February 11, 2014
    Assignee: Intersil Americas Inc.
    Inventors: Dev Alok Girdhar, Michael David Church, Alexander Kalnitsky
  • Patent number: 8610233
    Abstract: A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
  • Patent number: 8569827
    Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided, which extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: October 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Byoungkeun Son, Hyejin Cho
  • Patent number: 8569837
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Ta-Ming Kuan, Wen-Chin Lee
  • Patent number: 8551874
    Abstract: A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.
    Type: Grant
    Filed: May 8, 2010
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Bruce B. Doris, Chih-Chao Yang
  • Patent number: 8513765
    Abstract: A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8466051
    Abstract: A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 18, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Patent number: 8450156
    Abstract: In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 28, 2013
    Assignee: Infineon Technologies AG
    Inventors: Harald Gossner, Thomas Schulz, Christian Russ, Gerhard Knoblinger
  • Publication number: 20130130485
    Abstract: A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer.
    Type: Application
    Filed: December 28, 2011
    Publication date: May 23, 2013
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Patent number: 8444728
    Abstract: A chemical mechanical polishing composition, comprising, as initial components: water; 0.1 to 20 wt % abrasive having an average particle size of 5 to 50 nm; and, 0.001 to 1 wt % of an adamantyl substance according to formula (II): wherein A is selected from N and P; wherein each R8 is independently selected from hydrogen, a saturated or unsaturated C1-15 alkyl group, C6-15 aryl group, C6-15 aralkyl group, C6-15 alkaryl group; and, wherein the anion in formula (II) can be any anion that balances the positive charge on the cation in formula (II).
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: May 21, 2013
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Yi Guo, Zhendong Liu, Kancharla-Arun Kumar Reddy, Guangyun Zhang
  • Patent number: 8367508
    Abstract: A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Wilfried E. Haensch, Xinhui Wang, Keith Kwong Hon Wong
  • Patent number: 8349718
    Abstract: According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Uozumi
  • Publication number: 20120292733
    Abstract: The present invention relates to the field of microelectronic technology. It discloses a mixed Schottky/P-N junction diode and a method of making the same. The mixed Schottky/P-N junction diode comprises a semiconductor substrate having a bulk region and a doped region, and a conductive layer on the semiconductor substrate. The doped region has opposite doping from that of the bulk region. A P-N junction is formed between the bulk region and the doped region, a Schottky junction is formed between the conductive layer and the semiconductor substrate, and an ohmic contact is formed between the conductive layer and the doped region. The mixed Schottky/P-N junction diode of the present invention has high operating current, fast switching speed, small leakage current, high breakdown voltage, ease of fabrication and other advantages.
    Type: Application
    Filed: January 4, 2011
    Publication date: November 22, 2012
    Applicant: FUDAN UNIVERSITY
    Inventors: Dongping Wu, Shi-Li Zhang, Yinghua Pu
  • Patent number: 8283244
    Abstract: A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: October 9, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James D. Burnett, Brian A. Winstead
  • Patent number: 8278198
    Abstract: A method of producing a Schottky diode includes the steps of: forming a resist layer on the semiconductor substrate; performing a first exposure process on the resist layer; performing a first developing process for developing the resist layer to form a first Schottky diode having an excess region; performing a first cleaning process; performing a second exposure process on the first Schottky diode; performing a second developing process on the first Schottky diode to remove the excess region from the first Schottky diode so that a second Schottky diode corresponding to the specific Schottky diode is formed; and performing a second cleaning process.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: October 2, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Yuuki Doi, Hirokazu Fujimaki
  • Patent number: 8263466
    Abstract: A process for forming a FET (e.g., an n-FET or a p-FET), in which during formation a metal which makes up a source or drain of the transistor is stressed so that stress is induced in a semiconductor channel of the transistor.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: September 11, 2012
    Assignee: Acorn Technologies, Inc.
    Inventors: Paul Clifton, Daniel J. Connelly
  • Patent number: 8247319
    Abstract: Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Benjamin Luke Fletcher, Christian Lavoie, Siegfried Lutz Maurer, Zhen Zhang
  • Patent number: 8232197
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Patent number: 8202799
    Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: June 19, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chaing-Ming Chuang, Shau-Lin Shue
  • Patent number: 8158483
    Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 17, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 8148262
    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode, a source region and a drain region, forming a first metal layer, forming silicide layers by first annealing, removing a remainder of the first metal layer after the first annealing, performing a second annealing, forming a second metal layer, performing a third annealing, and removing a remainder of the second metal layer.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: April 3, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuya Okubo, Yusuke Morisaki, Youichi Momiyama
  • Patent number: 8143152
    Abstract: A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls 112 formed on the sidewalls of the gate electrode 108; a silicide layer 132 formed lateral to the sidewalls 112 of the first gate 114a on a surface of the silicon substrate 102; and a contact 164 which overlaps at least partially in plan view with the first gate 114a and reaches to the silicide layer 132 of the surface of the silicon substrate 102; wherein an insulator film is located between the contact 164 and the gate electrode 108 of the first gate 114a.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: March 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Masashige Moritoki
  • Patent number: 8105946
    Abstract: A method of forming the conductive lines of a semiconductor memory device comprises forming a first polysilicon layer over an underlying layer, forming first polysilicon patterns by patterning the first polysilicon layer, filling the space between the first polysilicon patterns with an insulating layer, etching a top portion of the first polysilicon patterns to form recess regions, forming spacers on the sidewalls of the recess regions, filling the recess regions with a second polysilicon layer to form second polysilicon patterns, and performing a metal silicidation process to convert the second polysilicon patterns to metal silicide patterns.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: January 31, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Sic Woo
  • Patent number: 8101511
    Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: January 24, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Dev Alok Girdhar, Michael David Church, Alexander Kalnitsky
  • Publication number: 20120009771
    Abstract: A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cyril Cabral, JR., John M. Cotte, Dinesh R. Koli, Laura L. Kosbar, Mahadevaiyer Krishnan, Christian Lavoie, Stephen M. Rossnagel, Zhen Zhang
  • Patent number: 8084342
    Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: December 27, 2011
    Assignee: Avolare 2, LLC
    Inventors: John P. Snyder, John M. Larson
  • Patent number: 8043912
    Abstract: A semiconductor device is provided with a semiconductor substrate comprising element isolation regions and an element region surrounded by the element isolation regions, a first polysilicon layer formed in the element region of the semiconductor substrate, an element-isolating insulation film formed in the element isolation region of the semiconductor substrate, a second polysilicon layer formed on the element-isolating insulation film, a first silicide layer formed on the first polysilicon layer. And the device further comprising a second silicide layer formed on the second polysilicon layer and being thicker than the first silicide layer.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Matsuda
  • Patent number: 8030154
    Abstract: In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper surface of the gate structure and on an exposed surface of the semiconductor substrate that is adjacent to the gate structure. An upper surface of the metal semiconductor alloy is converted to an oxygen-containing protective layer. The sidewall spacers are removed using an etch that is selective to the oxygen-containing protective layer. A strain-inducing layer is formed over the gate structure and the semiconductor surface, in which at least a portion of the strain-inducing layer is in direct contact with the sidewall surface of the gate structure. In another embodiment, the oxygen-containing protective layer of the metal semiconductor alloy is provided by a two stage annealing process.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 4, 2011
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc.
    Inventors: Ahmet S. Ozcan, Christian Lavoie, Zhen Zhang, Bin Yang
  • Patent number: 8021971
    Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Domenicucci, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 8008177
    Abstract: A method for fabricating a semiconductor device is provided using a nickel salicide process. The method includes forming a gate pattern and a source/drain region on a silicon substrate, forming a Ni-based metal layer for silicide on the silicon substrate where the gate pattern and the source/drain region are formed, and forming an N-rich titanium nitride layer on the Ni-based metal layer for silicide. Next, a thermal treatment is applied to the silicon substrate where the Ni-based metal layer for silicide and the N-rich titanium nitride layer are formed, thereby forming a nickel silicide on each of the gate pattern and the source/drain region. Then, the Ni-based metal layer for silicide and the N-rich titanium nitride layer are selectively removed to expose a top portion of a nickel silicide layer formed on the gate pattern and the source/drain region.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-chul San, Ja-hum Ku, Chul-sung Kim, Kwan-jong Roh, Min-joo Kim
  • Patent number: 7981784
    Abstract: Isolation regions are formed on a substrate to define an active region. A gate electrode is formed on the active region. A spacer structure is formed on a sidewall of the gate electrode. A gate silicide layer is formed on the gate electrode and a source/drain silicide layer is formed on the active region adjacent to the gate electrode. An upper portion of the gate silicide layer and a portion of the spacer structure are simultaneously removed to form a spacer structure pattern and a gate silicide layer pattern. A stress layer is formed to cover the gate electrode and spacer structure pattern.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: July 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Ki-Chul Kim, Jung-Deog Lee
  • Patent number: 7981735
    Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: July 19, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yark Yeon Kim, Seong Jae Lee, Moon Gyu Jang, Chel Jong Choi, Myung Sim Jun, Byoung Chul Park
  • Publication number: 20110159675
    Abstract: A process for forming a Schottky barrier to silicon to a bather height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and a ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form an SiO2 passivation layer to improve the self aligned process.
    Type: Application
    Filed: July 6, 2010
    Publication date: June 30, 2011
    Applicant: VISHAY-SILICONIX
    Inventors: Rossano Carta, Carmelo Sanfilippo
  • Patent number: 7947560
    Abstract: A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrate); and after the introduction of the nitrogen, applying heat treatment to the nickel film and the silicon layer (or the silicon substrate) under predetermined conditions to form a nickel disilicide layer.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: May 24, 2011
    Assignees: Seiko Epson Corporation, Renesas Technology Corporation
    Inventors: Yukimune Watanabe, Nobuyuki Mise, Shinji Migita
  • Patent number: 7943499
    Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: May 17, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang, Joe G. Tran
  • Patent number: 7923362
    Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: April 12, 2011
    Assignee: TELEFUNKEN Semiconductors GmbH & Co. KG
    Inventors: Franz Dietz, Volker Dudek, Tobias Florian, Michael Graf
  • Patent number: 7902055
    Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: March 8, 2011
    Assignee: Texas Instruments Incoprorated
    Inventors: Richard B. Irwin, Tony T. Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer S. Dumin, Patrick J. Jones, Fredric D. Bailey
  • Publication number: 20100258899
    Abstract: A Schottky diode device includes a silicon substrate, an epitaxial silicon layer on the silicon substrate, an annular trench in a scribe line region that encompasses the epitaxial silicon layer, an insulation layer on interior sidewall of the annular trench, a silicide layer on the epitaxial silicon layer, a conductive layer on the silicide layer, and a guard ring in the epitaxial silicon layer, wherein the guard ring butts the insulation layer.
    Type: Application
    Filed: April 8, 2009
    Publication date: October 14, 2010
    Inventors: Chih-Tsung Huang, Jhih-Siang Huang