Plural Gate Levels Patents (Class 438/588)
  • Patent number: 10355008
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 10002767
    Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Gordon A. Haller, Fatma A. Simsek-Ege
  • Patent number: 9941163
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 10, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Patent number: 9793124
    Abstract: Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: October 17, 2017
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 9761604
    Abstract: Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: September 12, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani
  • Patent number: 9698231
    Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Namkoong, Dong-Kyum Kim, Jung-Hwan Kim, Jung Geun Jee, Han-Vit Yang, Ji-Man Yoo
  • Patent number: 9379125
    Abstract: A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: June 28, 2016
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9356021
    Abstract: Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ru-Gun Liu, Ken-Hsien Hsieh, Ming-Feng Shieh, Chih-Ming Lai, Tsai-Sheng Gau
  • Patent number: 9299714
    Abstract: A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: March 29, 2016
    Assignees: SK HYNIX INC., TOHOKU UNIVERSITY
    Inventors: Moon-Sik Seo, Tetsuo Endoh
  • Patent number: 9263596
    Abstract: A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: February 16, 2016
    Assignee: SK Hynix Inc.
    Inventor: Deung Kak Yoo
  • Patent number: 9224747
    Abstract: A memory device includes a memory cell array having a first side and a second side and a stepped word line contact region located between the first side and the second side of the memory array. A first word line stair pattern is located in the stepped word line contact region adjacent to the first side of the memory array and a second word line stair pattern located in the stepped word line contact region adjacent to the second side of the memory array. A peripheral device region located in the stepped word line contact region between the first and the second word line stair patterns.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: December 29, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Yuki Mizutani, Fumiaki Toyama
  • Patent number: 9184175
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 9041090
    Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Akira Goda, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20150115347
    Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. The memory layer includes a tunnel insulating layer adjacent to the channel, a charge blocking layer adjacent to the gate, and a charge storing layer interposed between the tunnel insulating layer and the charge blocking layer. The tunnel insulating layer includes a first insulating layer adjacent to the channel and an air layer interposed between the first insulating layer and the charge storing layer.
    Type: Application
    Filed: January 20, 2014
    Publication date: April 30, 2015
    Applicant: SK hynix Inc.
    Inventor: Kyung-Sik MUN
  • Publication number: 20150115344
    Abstract: A 3D stacked semiconductor structure is provided, comprising a plurality of stacks formed on a substrate; at least a contact hole formed vertically in one of the stacks; a conductor formed in the contact hole; and a charging trapping layer at least formed at sidewalls of the stacks. One of the stacks comprises a multi-layered pillar, including a plurality of insulating layers and a plurality of conductive layers arranged alternately, and a dielectric layer formed on the multi-layered pillar. The contact hole is formed vertically in one of the stacks, and the contact hole penetrates the dielectric layer, the insulating layers and the conductive layers of the corresponding stack. Also, a top surface of the conductor is higher than a top surface of the multi-layered pillar for the corresponding stack.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Erh-Kun Lai
  • Patent number: 9012318
    Abstract: Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 21, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Prashant Raghu
  • Patent number: 9006089
    Abstract: The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sung-Wook Jung
  • Publication number: 20150099353
    Abstract: A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Jung-Geun JEE, Seok-Hoon KIM, Su-Jin SHIN, Woo-Sung LEE, Tae-Ouk KWON
  • Publication number: 20150079776
    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 19, 2015
    Inventors: Srijit MUKHERJEE, Christopher J. WIEGAND, Tyler J WEEKS, Mark Y. LIU, Michael L. HATTENDORF
  • Publication number: 20150072512
    Abstract: Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.
    Type: Application
    Filed: November 17, 2014
    Publication date: March 12, 2015
    Inventor: Hongmei Wang
  • Publication number: 20150064885
    Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.
    Type: Application
    Filed: June 19, 2014
    Publication date: March 5, 2015
    Inventors: Bo-Young Lee, Jong-Wan Choi, Dae-Hun Choi, Myoung-Bum Lee
  • Publication number: 20150054044
    Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells (105-109, 113-115) on a first flash cell substrate area (111) which are encapsulated in one or more planar dielectric layers (116) prior to forming an elevated substrate (117) on a second CMOS transistor area (112) on which high-k metal gate electrodes (119-120, 122-126, 132, 134) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Freescale Semiconductor, Inc
    Inventors: Asanga H. Perera, Sung-Taeg Kang, Jane A. Yater, Cheong Min Hong
  • Patent number: 8962464
    Abstract: Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ru-Gun Liu, Ken-Hsien Hsieh, Ming-Feng Shieh, Chih-Ming Lai, Tsai-Sheng Gau
  • Publication number: 20150050803
    Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device may include forming a structure including insulating layers and gate layers that are alternately and repeatedly stacked on a substrate. The method may include forming through-holes in the structure. The method may include forming first patterns on sidewalls of the gate layers, by performing an oxidation process. The method may include forming second patterns on portions of the substrate, by performing the oxidation process. The method may include removing the second patterns. Moreover, the method may include forming semiconductor patterns in the through-holes.
    Type: Application
    Filed: May 28, 2014
    Publication date: February 19, 2015
    Inventors: Sunghae Lee, Dongkyum Kim, Joonsuk Lee
  • Publication number: 20150044860
    Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.
    Type: Application
    Filed: October 27, 2014
    Publication date: February 12, 2015
    Inventors: Anurag Jindal, Gowri Damarla, Roger W. Lindsay, Eric Blomiley
  • Patent number: 8940596
    Abstract: A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer directly on the gate dielectric layer, and the gate layer directly on the gate conductive layer. A drain contact region is formed on the drain region, and a source contact region is formed on the source region. A conductive region is formed directly on the gate conductive layer and adjacent to a second portion of the gate layer. A gate contact terminal is formed in contact with the conductive region.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Ming-Hsiang Song, Kuo-Ji Chen, Ming Zhu, Po-Nien Chen, Bao-Ru Young
  • Patent number: 8936983
    Abstract: A method of fabricating a semiconductor device according to present invention includes forming a stack layers on a semiconductor substrate having a first area and a second area; forming first gates on the semiconductor substrate of the first area by patterning the stack layers, wherein the first gates are formed a first distance apart from each other; forming a first impurity injection area in the semiconductor substrate of the first area exposed at both sides of each of the first gates; filling a space between the first gates with an insulating layer; forming second gates on the semiconductor substrate of the second area by patterning the stack layers, wherein the second gates are formed a second distance apart from each other, and wherein the second distance is larger than the first distance; and forming a second impurity injection area in the semiconductor device of the second area exposed between the second gates.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: January 20, 2015
    Assignee: SK Hynix Inc.
    Inventors: Kang Jae Lee, Eun Joo Jung
  • Publication number: 20150014787
    Abstract: A method for manufacturing a semiconductor device includes: forming a first insulation film on a portion of a first region of a semiconductor substrate and forming a second insulation film between a second region and a third region of the semiconductor substrate; etching an upper portion of the first insulation film such that the thickness of the first insulation film is less than the thickness of the second insulation film; forming a third insulation film in the second region and forming a fourth insulation film in the third region; and forming a first gate electrode on the first insulation film whose upper portion was etched, forming a second gate electrode on the third insulation film, and forming a third gate electrode on the fourth insulation film.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 15, 2015
    Inventor: Takahisa AKIBA
  • Publication number: 20150008501
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate, and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 8, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiwamu SAKUMA, Masahiro KIYOTOSHI
  • Patent number: 8916431
    Abstract: The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: December 23, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazushi Fujita, Taiji Ema, Hiroyuki Ogawa
  • Patent number: 8912069
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: December 16, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Patent number: 8895389
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Manufacturing International Corp
    Inventor: Zhongshan Hong
  • Publication number: 20140339621
    Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.
    Type: Application
    Filed: May 15, 2013
    Publication date: November 20, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Fatma Arzum Simsek-Ege, Akira Goda, Durai Vishak Nirmal Ramaswamy
  • Patent number: 8883624
    Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 11, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 8877568
    Abstract: Methods of making a logic transistor in a logic region and an NVM cell in an NVM region of a substrate include forming a conductive layer on a gate dielectric, patterning the conductive layer over the NVM region, removing the conductive layer over the logic region, forming a dielectric layer over the NVM region, forming a protective layer over the dielectric layer, removing the dielectric layer and the protective layer from the logic region, forming a high-k dielectric layer over the logic region and a remaining portion of the protective layer, and forming a first metal layer over the high-k dielectric layer. The first metal layer, the high-k dielectric, and the remaining portion of the protective layer are removed over the NVM region. A conductive layer is deposited over the remaining portions of the dielectric layer and over the first metal layer, and the conductive layer is patterned.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Publication number: 20140319623
    Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
    Type: Application
    Filed: December 28, 2011
    Publication date: October 30, 2014
    Inventors: Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez
  • Patent number: 8872252
    Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Anurag Jindal, Gowri Damarla, Roger W. Lindsay, Eric Blomiley
  • Publication number: 20140315360
    Abstract: A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 23, 2014
    Inventors: Kuan-Ting Liu, Liang-Gi Yao, Yasutoshi Okuno, Clement Hsingjen Wann
  • Patent number: 8853068
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
  • Patent number: 8846537
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Publication number: 20140264539
    Abstract: A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.
    Type: Application
    Filed: February 27, 2014
    Publication date: September 18, 2014
    Applicant: Silicon Storage Technology, Inc.
    Inventors: Nhan Do, Hieu Van Tran, Chien-Sheng Su, Prateep Tuntasood
  • Patent number: 8822321
    Abstract: According to one embodiment, an opening pattern is formed in the core film above a processing target, and a mask film is conformally formed above the processing target. Next, etch-back of the mask film is performed so that the mask film remains on a side surface of the core film. After that, line-and-space shaped core patterns, made of the core film, is formed in an area other than an area forming the opening pattern. Next, sidewall patterns are formed around the core patterns, and the core patterns are removed. Next, the processing target is patterned by using the mask film and the sidewall patterns.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiji Kajiwara
  • Publication number: 20140220770
    Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.
    Type: Application
    Filed: April 11, 2014
    Publication date: August 7, 2014
    Applicant: Infineon Technologies AG
    Inventors: Knut Stahrenberg, Jin-Ping Han
  • Publication number: 20140175534
    Abstract: In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.
    Type: Application
    Filed: August 5, 2013
    Publication date: June 26, 2014
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Naoyuki KOFUJI, Nobuyuki NEGISHI, Hiroaki ISHIMURA
  • Patent number: 8741754
    Abstract: A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: June 3, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Ya-Jui Lee, Ying-Chia Lin
  • Patent number: 8741719
    Abstract: A thermally-grown oxygen-containing gate dielectric and select gate are formed in an NVM region. A high-k gate dielectric, barrier layer, and dummy gate are formed in a logic region. The barrier layer may include a work-function-setting material. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, resulting in an opening. A gate layer is formed over the charge storage layer in the NVM region and within the opening in the logic region, wherein the gate layer within the opening together with the barrier layer form a logic gate in the logic region, and the gate layer is patterned to form a control gate in the NVM region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
  • Patent number: 8722493
    Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8723247
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of gate electrode films arranged parallel to each other along a direction, a semiconductor member extending in the direction, and passing through the plurality of gate electrode films, and a charge storage film provided between the gate electrode films and the semiconductor member. Protrusions are provided projecting along the direction at the ends of the gate electrode films in opposition to the semiconductor member. A gaseous layer is formed in a part of a gap between the gate electrode films.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Komori, Daigo Ichinose
  • Patent number: 8716120
    Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing an upper portion of the final work function metal, for instance a titanium nitride material in P-channel transistors. In some illustrative embodiments, the selective removal of the metal-containing electrode material in an upper portion of the gate opening may be accomplished without unduly increasing overall process complexity.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Klaus Hempel, Andy Wei, Martin Mazur
  • Patent number: 8716089
    Abstract: A thermal oxide is formed in an NVM region and a logic region. A polysilicon layer is formed over the thermal oxide and patterned to form a dummy gate and a select gate in the logic and NVM regions, respectively. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, forming an opening. A second dielectric layer is formed over the select gate and within the opening, and a gate layer is formed over the second dielectric layer and within the opening, wherein the gate layer within the opening forms a logic gate and the gate layer is patterned to form a control gate in the NVM region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff