Forming Array Of Gate Electrodes Patents (Class 438/587)
  • Patent number: 10431466
    Abstract: Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process is performed on a metal nitride layer in a film stack, thereby removing oxygen atoms disposed within layers of the film stack and, in some embodiments eliminating an oxygen-containing interfacial layer disposed within the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift. Further, the metal gate structure operates with an increased leakage current that is as little as one quarter the increase in leakage current associated with a similar metal gate structure formed via conventional techniques.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: October 1, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Johanes S. Swenberg, Wei Liu, Houda Graoui, Steven C. H. Hung
  • Patent number: 10411026
    Abstract: The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 10276391
    Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate structure includes a work function metal layer, a first conductor layer, and a second conductor layer arranged over the work function metal layer. The second conductor layer has a sidewall and a top surface, and the first conductor layer has a first section arranged between the second conductor layer and the work function metal layer and a second section arranged adjacent to a first portion of the sidewall of the second conductor layer. A dielectric cap is arranged on the gate structure. The dielectric cap has a first section arranged over the top surface of the second conductor layer and a second section arranged adjacent to a second portion of the sidewall of the second conductor layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: April 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Patent number: 10276658
    Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10157797
    Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10157796
    Abstract: The disclosure relates to methods including: forming a soft mask; forming a first marking trench within a portion of the soft mask by selectively removing a portion of the soft mask at a first location, over one of a pair of gate trenches; forming an insulative liner on the soft mask and within the first marking trench; forming an anti-reflective film on the insulative liner and within the first marking trench; selectively removing the anti-reflective film and the insulative liner at a second location to expose a portion of the soft mask positioned over the other one of the pair of gate trenches; forming a second marking trench by removing another portion of the soft mask at the second location; and removing a portion of the soft mask at the first and second marking trenches to expose a lower surface of each of the pair of gate trenches.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Chanro Park, Ruilong Xie, Pei Liu
  • Patent number: 10090164
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: October 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekmini A. De Silva, Isabel C. Estrada-Raygoza, Yann A. M. Mignot, Indira P. V. Seshadri, Yongan Xu
  • Patent number: 10014221
    Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 9837427
    Abstract: Deterioration in reliability is prevented regarding a semiconductor device. The deterioration is caused when an insulating film for formation of a sidewall is embedded between gate electrodes at the time of forming sidewalls having two kinds of different widths on a substrate. A sidewall-shaped silicon oxide film is formed over each sidewall of a gate electrode of a low breakdown voltage MISFET and a pattern including a control gate electrode and a memory gate electrode. Then, a silicon oxide film beside the gate electrode is removed, and a silicon oxide film is formed on a semiconductor substrate, and then etchback is performed. Accordingly, a sidewall, formed of a silicon nitride film and the silicon oxide film, is formed beside the gate electrode, and a sidewall, formed of the silicon nitride film and the silicon oxide films, is formed beside the pattern.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Masaaki Shinohara
  • Patent number: 9728646
    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile by the thermal hydrogen treatment.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Shiu-Ko Jangjian, Cheng-Wei Chen, Ting-Chun Wang
  • Patent number: 9595475
    Abstract: A method for fabricating a semiconductor device having a multi-stage fin profile includes providing a substrate and forming a first spacer having a first spacer width over the substrate. The first spacer masks a first portion of the substrate during a first etch process. By way of example, the first etch process is performed on the substrate to form a first-stage fin region, where a width of the first-stage fin region is substantially equal to about the first spacer width. A second spacer having a second spacer width is formed over the substrate, where the second spacer and the first-stage fin region mask a second portion of the substrate during a second etch process. In some examples, the second etch process is performed on the substrate to form a second-stage fin region, where a width of the second-stage fin region is greater than the width of the first-stage fin region.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9515070
    Abstract: A semiconductor structure which includes: a fin on a semiconductor substrate; and a gate structure wrapped around the fin. The gate structure includes: spaced apart spacers to form an opening, the spacers being perpendicular to the fin, the spacers having a height with respect to the fin; a high-k dielectric material in the opening and over the fin, the high-k dielectric material in contact with the spacers and a bottom of the opening; a work function metal in contact with the high-k dielectric material that is over the fin, the spacers and the bottom of the opening, the work function metal that is in contact with the high-k dielectric material having a height in the opening that is less than the height of the spacers, the high-k dielectric material and the work function metal only partially filling the opening; and a metal completely filling the opening.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Effendi Leobandung, Stefan Schmitz, Junli Wang
  • Patent number: 9484458
    Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: November 1, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Wook Lee, Myeong-Cheol Kim, Sang-Min Lee, Young-Ju Park, Hyung-Yong Kim, Myung-Hoon Jung
  • Patent number: 9466501
    Abstract: Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: October 11, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Hsien Lu, Chang-Sheng Lin
  • Patent number: 9437637
    Abstract: A method for manufacturing a semiconductor device comprising, forming a first photoresist pattern by exposing and then developing a first photoresist film formed on a substrate, irradiating the first photoresist pattern with UV light to cure its surface, forming a second photoresist film so as to cover the substrate and the first photoresist pattern, forming a second photoresist pattern and performing ion implantation in the substrate using the second photoresist pattern. The second photoresist pattern is not subjected to UV irradiation after the second photoresist film has been developed and before the ion implantation is performed, or is irradiated with the UV light, after the second photoresist film has been developed and before the ion implantation is performed, under a reduced condition relative to that for the first photoresist pattern.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: September 6, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Atsushi Kanome, Nobutaka Ukigaya, Koji Hara, Satoshi Yoshizaki, Masahiko Kondo
  • Patent number: 9343412
    Abstract: A method of forming a MOSFET structure is provided. In the method, an epitaxial layer is formed. A cap layer is formed above the epitaxial layer. A first trench is formed above the epitaxial layer. A protection layer is deposited within the first trench. The protection layer is a material selected from the group consisting of germanium and silicon-germanium.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Patent number: 9293568
    Abstract: Embodiments of the present invention may include a semiconductor patterning method involving forming a fin on a substrate, where the fin may have a sloped sidewall. The fin may be characterized by an initial height and a first width measured proximate a midpoint of the initial height. The method may include forming a masking layer above the fin, and the method may involve removing a first portion of the masking layer. The method may include decreasing the first width of the fin while maintaining the initial height.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: March 22, 2016
    Assignee: Applied Materials, Inc.
    Inventor: Jungmin Ko
  • Patent number: 9263442
    Abstract: Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further includes segmenting the continuous replacement gate structure into separate replacement gate structures. The method further includes forming insulator material between the separate replacement gate structures.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 9209308
    Abstract: There is provided a thin film transistor, comprising a substrate (1) and a gate layer (3), a gate insulating layer (4), an active layer (5), an electrode metal layer (8) and a passivation layer (9) which are formed on the substrate (1) in sequence; the electrode metal layer (8) comprises a source electrode (8a) and a drain electrode (8b), which are separated from each other with a channel region being defined therebetween; between the gate layer (3) and the substrate (1), there is formed a first transparent conductive layer (2); between the active layer (5) and the electrode metal layer (8), there is formed a second transparent conductive layer (7). The transparent conductive layers (2, 7) are added so that adhesive force between the gate metal layer (3) and the substrate (1) is enhanced, diffusion of the electrode metal to the active layer (5) is prevented.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: December 8, 2015
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xuehui Zhang, Xiang Liu, Jainshe Xue
  • Patent number: 9093470
    Abstract: Producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal dielectric material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the dielectric material layer, over the conductive gate structure. An electrode is formed located over the conductive gate structure and in contact with a first portion of the semiconductor layer and another electrode is formed vertically separated from the electrode and located in contact with a second portion of the semiconductor layer by printing an inhibitor that wicks along the reentrant profile of the conductive gate structure and depositing a conductive inorganic thin film using an atomic layer deposition process where the inhibitor is absent to form a channel in the semiconductor layer along the reentrant profile between the electrodes by inhibiting deposition of conductive material between the electrodes with the wicked inhibitor.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: July 28, 2015
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Shelby Forrester Nelson, Carolyn Rae Ellinger
  • Patent number: 9087870
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: July 21, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Wei Hua Tong, Huang Liu, HongLiang Shen, Jin Ping Liu, Seung Kim
  • Publication number: 20150145023
    Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 28, 2015
    Inventors: Tsuyoshi Arigane, Daisuke Okada, Digh Hisamoto
  • Publication number: 20150140742
    Abstract: Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.
    Type: Application
    Filed: January 21, 2015
    Publication date: May 21, 2015
    Inventors: Carlo Pozzi, Marcello Mariani, Gianpietro Carnevale
  • Publication number: 20150137250
    Abstract: The present invention further provides a string select line (SSL) of a three-dimensional memory array, including: a dielectric substrate; an SSL structure disposed on the dielectric substrate, wherein the SSL structure includes a plurality of dielectric layers and a plurality of first conductive layers, the dielectric layers and the first conductive layers stacked alternatively; a second conductive layer covering sidewalls and a top portion of the SSL structure; and an oxide layer disposed between the first conductive layers and the second conductive layer, and contacting with the first conductive layers and the second conductive layer.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: MACRONIX International Co., Ltd.
    Inventor: Erh-Kun Lai
  • Patent number: 9034698
    Abstract: A semiconductor device manufacturing method includes exciting a processing gas containing a HBr gas and a Cl2 gas within a processing chamber that accommodates a target object including a substrate, regions made of silicon, which are protruded from the substrate and arranged to form a gap, a metal layer formed to cover the regions, a polycrystalline silicon layer formed on the metal layer, and an organic mask formed on the polycrystalline silicon layer. The Cl2 gas is supplied at a flow rate of about 5% or more to about 10% or less with respect to a flow rate of the HBr gas in the processing gas.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 19, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Ozu, Shota Yoshimura, Hiroto Ohtake, Kosuke Kariu, Takashi Tsukamoto
  • Patent number: 9034710
    Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Gurtej S. Sandhu
  • Publication number: 20150132936
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventors: Il-Cheol RHO, Jong-Min LEE
  • Publication number: 20150129961
    Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicants: STMicroelectronics, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wai-Kin Li, Chieh-Yu Lin, Yannick Daurelle
  • Patent number: 9023724
    Abstract: A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventors: Duk Eui Lee, Seung Cheol Lee
  • Patent number: 9024288
    Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 5, 2015
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Tuo Sun
  • Patent number: 9018710
    Abstract: A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region. A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seung-Mi Lee, Yun-Hyuck Ji
  • Publication number: 20150108561
    Abstract: Provided is a semiconductor device and a method of fabricating the same. The method may include forming trenches in a substrate and lower gate patterns on the substrate between the trenches, forming sacrificial patterns filling the trenches, forming a porous insulating layer on the lower gate patterns to cover top surfaces of the sacrificial patterns, removing the sacrificial patterns through pores of the porous insulating layer to form air gaps surrounded by the trenches and the porous insulating layer, and forming a liner insulating layer on inner surfaces of the trenches through the pores of the porous insulating layer.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 23, 2015
    Inventors: HyoJoong Kim, Songha Oh, Changgoo Jung
  • Patent number: 9012270
    Abstract: Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ji Xu, Vito Dai
  • Patent number: 9012286
    Abstract: Disclosed herein are various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate to define at least one fin (or fins) for the device, prior to forming a gate structure above the fin (or fins), performing a first epitaxial growth process to grow a first semiconductor material on exposed portions of the fin (or fins) and forming the gate structure above the first semiconductor material on the fin (or fins).
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Min-Hwa Chi
  • Patent number: 9012318
    Abstract: Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 21, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Prashant Raghu
  • Publication number: 20150104934
    Abstract: A semiconductor device includes a substrate including an active region, an insulation layer formed over the substrate, a plurality of openings formed in the insulation layer, a plurality of contact plugs filling the plurality of openings, a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug. The semiconductor device may decrease contact resistance by forming a silicide layer before the formation of openings regardless of the linewidth and aspect ratio of the openings. Also, because it does not have to consider step coverage based on the aspect ratio of openings, there is no limitation in the method of depositing a metal layer. Therefore, productivity may be improved.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 16, 2015
    Inventor: Hyung-Kyun KIM
  • Publication number: 20150104935
    Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 16, 2015
    Applicant: INTEL CORPORATION
    Inventor: MARK T. BOHR
  • Patent number: 9006089
    Abstract: The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sung-Wook Jung
  • Patent number: 9006815
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a silicon-containing substrate, a plurality of memory cells, and an insulating film. The substrate includes silicon. The plurality of memory cells is provided on the substrate with a spacing therebetween. The insulating film is provided on a sidewall of the memory cell. The insulating film includes a protrusion protruding toward an adjacent one of the memory cells above a void portion is provided between the memory cells.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuhiro Oda
  • Publication number: 20150097251
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
  • Publication number: 20150097249
    Abstract: Methodologies for forming a cross coupling gate and a resulting device are disclosed. Embodiments include: providing a plurality of gates extending vertically on a plurality of equally spaced horizontal positions of an IC; providing a cross-couple region of a gate of the plurality of gates, the cross-couple region including a portion of the gate extending from a first horizontal position of the horizontal positions to a second horizontal position of the horizontal positions; and providing at least one of the plurality of gates with an overlap of first and second segments of the at least one gate, the first and second segments being designated to be decomposed using different colors.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Ryan KIM, Jason CANTONE
  • Patent number: 8999791
    Abstract: A plurality of doped sacrificial semiconductor material portions of a first width and a plurality of doped sacrificial semiconductor material portions of a second width, which is different from the first width, are provided on a sacrificial gate dielectric material. Exposed portions of the sacrificial dielectric material are removed. A dielectric material is formed adjacent each doped sacrificial semiconductor material portion such that an upper surface of each doped sacrificial semiconductor material portion is exposed. Each doped sacrificial semiconductor material portion is removed providing a first set of gate cavities having the first width and a second set of gate cavities having the second width. Each gate cavity is filled with a gate structure. The gate structures formed in the first set of gate cavities have the first width, while the gate structure formed in the second set of gate cavities have the second width.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8999830
    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
  • Patent number: 8999827
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first and second interconnect trenches adjacent to each other in an interlayer insulating film; providing a first interconnect and a space thereon within the first interconnect trench, and a second interconnect and a space thereon within the second interconnect trench; forming a first trench larger in width from the first interconnect trench and a second trench larger in width from the second interconnect trench, by conducting isotropic-etching; and forming a first insulating film within the first trench and a second insulating film within the second trench by filling an insulating material in the first trench and the second trench.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: April 7, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshiyuki Hirota
  • Publication number: 20150093869
    Abstract: A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Inventors: Werner Juengling, Howard C. Kirsch
  • Publication number: 20150093888
    Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
  • Patent number: 8987080
    Abstract: Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xinliang Lu, Seshadri Ganguli, Atif Noori, Maitreyee Mahajani, Shih Chung Chen, Yu Lei, Xinyu Fu, Wei Tang, Srinivas Gandikota
  • Patent number: 8987787
    Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Kuang-Yeu Hsieh, Cheng-Yuan Wang
  • Publication number: 20150079775
    Abstract: Systems and methods are provided for fabricating semiconductor devices. For example, a substrate is provided. A polymer layer is formed on the substrate. An oxygen-based plasma is applied to remove the polymer layer. An oxidizing solution is applied to generate a dielectric layer. A conductive layer is formed on the dielectric layer for fabricating semiconductor devices.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: SHAO-JYUN WU
  • Patent number: 8981422
    Abstract: To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over sidewalls SW facing each other in the abutting portion between gate electrodes G2 and G5, a liner insulating film 6 and an interlayer insulating film 7 are formed. Between the sidewalls SW, the liner insulating film 6 formed on each of the side walls of the sidewalls SW are brought in contact with each other to close a space between the sidewalls SW to prevent a void from being generated inside the interlayer insulating film 7 and the liner insulating film 6.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Masahiko Takeuchi