Recessed Into Semiconductor Substrate Patents (Class 438/589)
  • Patent number: 10797057
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Winbond Electronic Corp.
    Inventors: Wei-Che Chang, Tzu-Ming Ou Yang
  • Patent number: 10770476
    Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped regions, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 8, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yao-An Chung, Yuan-Chieh Chiu
  • Patent number: 10755982
    Abstract: One illustrative method disclosed herein includes forming 1st and 2nd sacrificial gate structures for, respectively, 1st and 2nd devices, removing 1st and 2nd sacrificial gate electrodes from the 1st and 2nd sacrificial gate structures so as to at least partially define, respectively, 1st and 2nd replacement gate (RMG) cavities, and removing the 2nd sacrificial gate insulation layer from the 2nd RMG cavity while leaving the 1st sacrificial gate insulation layer in position in the 1st RMG cavity. The method also includes forming a conformal gate insulation layer in both the 1st and 2nd RMG cavities, removing the conformal gate insulation layer and the 1st sacrificial gate insulation layer from the 1st RMG cavity while leaving the conformal gate insulation layer in the 2nd RMG cavity, and performing an oxidation process to form an interfacial gate insulation layer only in the 1st RMG cavity.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: August 25, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Abu Naser M. Zainuddin, Wei Ma, Daniel Jaeger, Joseph Versaggi, Jae Gon Lee, Thomas Kauerauf
  • Patent number: 10727068
    Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Hsiao-Chiu Hsu
  • Patent number: 10586765
    Abstract: Aspects of the disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a power rail formed in an isolation trench. The power rail is covered by a dielectric cap that isolates the power rail from conductive pattern structures on the dielectric cap. Further, an opening is selectively formed in the dielectric cap and is filled with conductive material to selectively connect a conductive pattern structure with the power rail.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 10, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. Devilliers, Kandabara Tapily
  • Patent number: 10515807
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Fen Chien, Chih-Hsiang Fan, Hsiao-Kuan Wei, Pohan Kung, Hsien-Ming Lee
  • Patent number: 10418456
    Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Patent number: 10388763
    Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Chang, Chiung Wen Hsu, Yu-Ting Weng
  • Patent number: 10373834
    Abstract: The present disclosure provides a semiconductor structure of a metal gate and a manufacturing method therefor. The manufacturing method includes providing a semiconductor substrate; uniformly depositing a first hard mask layer on the semiconductor substrate, corresponding to a region where the metal gate is located, patterning and etching the first hard mask layer to form a recess, forming a sloping sidewall on a sidewall of the recess, the sloping sidewall and an upper surface of the substrate forming a groove structure, with the size of an upper part of the groove structure being larger than that of a lower part thereof, and forming a metal gate in the groove structure; and removing the first hard mask layer.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: August 6, 2019
    Assignee: Shaghai Huali Microelectronics Corporation
    Inventor: Qiuming Huang
  • Patent number: 10269912
    Abstract: A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 10243084
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: March 26, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Jung Chen, Tzu-Ping Chen
  • Patent number: 10157919
    Abstract: A semiconductor device includes a semiconductor substrate, multiple fins formed on a front surface of the semiconductor substrate, a stress layer formed on a top surface of the fins, multiple strip-shaped gate structures formed above the stress layers, each of which extending in a direction substantially perpendicular to a direction of the fins, a contact hole etch stop layer covering the front surface of the semiconductor substrate, sidewalls of the fins, and top surfaces and sidewalls of the stress layers, a first interlayer dielectric layer over the contact hole etch stop layer, the first interlayer dielectric layer including filling voids formed therein, and a top surface of the first interlayer dielectric layer being below the top surfaces of the stress layers, a barrier liner layer over the first interlayer dielectric layer, and a second interlayer dielectric layer over the barrier liner layer and the contact hole etch stop layer.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 18, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Yizhi Zeng
  • Patent number: 10068796
    Abstract: A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A hole portion is formed in the first sacrificial film. A second sacrificial film is formed in the hole portion. A second processed layer is formed above the first sacrificial film and the second sacrificial film, and a second hole is formed in the second processed layer to expose the second sacrificial film. A third sacrificial film is formed on an inner side surface of the second hole, and a fourth sacrificial film is formed on the third sacrificial film. The second sacrificial film is etched using the fourth sacrificial film as a mask. The third sacrificial film exposed by etching the second sacrificial film is etched. The second processed layer is etched using the third sacrificial film as a mask.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki Sasaki
  • Patent number: 10062613
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate; forming a first work function metal layer in the first trench and the second trench; forming a patterned mask to cover the second trench; removing the first work function metal layer from the first trench; forming a second work function metal layer in the first trench and the second trench; and forming a conductive layer in the first trench and the second trench to form a first gate structure and a second gate structure.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: August 28, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Yu-Cheng Tung, Ming-Feng Kuo, Li-Chiang Chen
  • Patent number: 9853126
    Abstract: A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench. First and second source regions are formed in a self-alignment manner by introduction of impurities through the first insulating film.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 26, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shuji Mizokuchi, Ryousuke Ookawa, Naoki Sato
  • Patent number: 9780036
    Abstract: A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 3, 2017
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Jin Ho Bin
  • Patent number: 9653684
    Abstract: A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2<2×N×k is satisfied.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenichi Murooka
  • Patent number: 9627272
    Abstract: A patterning scheme to minimize dry/wet strip induced device degradation and resultant devices are provided. The method includes removing a workfunction material over a first device area of a structure, while protecting the workfunction material over a second device area of the structure with a first masking material. The method further includes applying a second masking material over the first device area and the first masking material. The method further includes removing the first masking material and the second masking material until the workfunction material is exposed over the second device area.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: April 18, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Huihang Dong, Wai-Kin Li
  • Patent number: 9627403
    Abstract: A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 18, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jin Liu, Tong Zhang, Jayavel Pachamuthu, Yao-Sheng Lee, Johann Alsmeier
  • Patent number: 9614088
    Abstract: A semiconductor structure includes a substrate including a first active region, a second active region and an isolation disposed between the first active region and the second active region; a plurality of gates disposed over the substrate and including a first gate extended over the first active region, the isolation and the second active region, and a second gate over the first active region and the second active region; and an inter-level dielectric (ILD) disposed over the substrate and surrounding the plurality of gates, wherein the second gate is configured not to conduct current flow and includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: April 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Shuo Ho, Tsung-Yu Chiang, Kuang-Hsin Chen
  • Patent number: 9613959
    Abstract: The present disclosure relates to methods of forming a field effect transistor (FET) over a substrate, and associated integrated circuit device that improve etching back profile and prevent metal gate defect. In some embodiments, a recess is formed through an inter-layer dielectric (ILD) layer along a sidewall spacer and filled with a high-? dielectric layer and a metal gate. An etch back is performed to lower the high-? dielectric layer and the metal gate, where an “antenna” shaped residue of the high-? dielectric material and the metal gate material is left at the boundary region of the high-? layer and the metal gate, along the sidewall spacer. Then a second etch is performed to the sidewall spacer, removing a top edge portion of the sidewall spacer. Then one more step of etch can be performed to the high-? layer and the metal gate to planarize and remove the residue.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shiang-Bau Wang
  • Patent number: 9548380
    Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 17, 2017
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Nhan Do
  • Patent number: 9466676
    Abstract: Provided are approaches of forming a semiconductor device (e.g., transistor such as a FinFET or planar device) having a gate metal recess. In one approach, a liner layer and a metal layer (e.g., W) are applied in a trench (e.g., via CVD and/or ALD). Then, a single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Ruilong Xie
  • Patent number: 9330938
    Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: May 3, 2016
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Hemanth Jagannathan, Balaji Kannan, Siddarth A. Krishnan, Unoh Kwon, Rekha Rajaram
  • Patent number: 9324837
    Abstract: A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench. First and second source regions are formed in a self-alignment manner by introduction of impurities through the first insulating film.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: April 26, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shuji Mizokuchi, Ryousuke Ookawa, Naoki Sato
  • Patent number: 9318555
    Abstract: A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an embodiment, the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-on-insulator layer on the buried oxide. A graphene layer is transferred onto the silicon-on-insulator layer. Source and drain regions are formed in the silicon-on-insulator layer, and a gate is formed above the graphene. In one embodiment, the processing includes growing a respective oxide layer on each of first and second silicon sections, and joining these silicon sections together via the oxide layers to form the silicon material. The processing, in an embodiment, further includes removing a portion of the first silicon section, leaving a residual silicon layer on the bonded oxide, and the graphene layer is positioned on this residual silicon layer.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Patent number: 9281374
    Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: March 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
  • Patent number: 9281309
    Abstract: Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a conductor to form a recessed region and subsequently etching the conductor to form gates on the fins. The wet etching may include formation of recesses which are may be backfilled with a fill material to form spacers on the conductor. Portions of a plug may be removed during the wet etch to form overhanging spacers to provide further protection of the conductor during the dry etch.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 8, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 9245962
    Abstract: A method of manufacturing a semiconductor device includes forming a sacrificial pattern, forming a first stacked structure including first material layers and second material layers alternately stacked on the sacrificial pattern, forming first semiconductor patterns passing through the first stacked structure and dielectric multi-layers surrounding the first semiconductor patterns, forming a slit passing through the first stacked structure and exposing the sacrificial pattern, forming a spacer on an inner wall of the slit, forming a first opening by removing the sacrificial pattern through the slit, forming a second opening by partially removing the dielectric multi-layers through the first opening to expose lower portions of the first semiconductor patterns, and forming a connection pattern in contact with the first semiconductor patterns in the first and second openings.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: January 26, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Yang, Dong Sun Sheen
  • Patent number: 9196691
    Abstract: A method of fabricating a metal gate electrode of a field effect transistor includes forming a dielectric layer over an active region, and forming an opening in the dielectric layer. The method further includes partially filling the opening with a high-dielectric-constant material, partially filling the opening with a conformal first metal material over the high-dielectric-constant material, and filling the opening with a capping layer over the first metal material. The method further includes partially removing the first metal material and capping layer in the opening using a wet etching process. The method further includes fully removing the remaining capping layer in the opening using a wet etching process. The method further includes depositing a second metal material in the opening over the remaining first metal material, and planarizing the second metal material.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: November 24, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hao Hou, Peng-Soon Lim, Da-Yuan Lee, Xiong-Fei Yu, Chun-Yuan Chou, Fan-Yi Hsu, Jian-Hao Chen, Kuang-Yuan Hsu
  • Patent number: 9196625
    Abstract: Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: November 24, 2015
    Assignee: Intel Corporation
    Inventor: Randy J. Koval
  • Patent number: 9142460
    Abstract: Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: September 22, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Carlo Pozzi, Marcello Mariani, Gianpietro Carnevale
  • Patent number: 9117923
    Abstract: A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 25, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunil Shim, Jaehoon Jang, Hansoo Kim, Sungmin Hwang, Wonseok Cho, Jinsoo Lim
  • Publication number: 20150145027
    Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Jia-Rong Wu, Ching-Wen Hung
  • Publication number: 20150145057
    Abstract: A multi-channel semiconductor device includes a first and second gate channels formed in a semiconductor substrate. The first gate channel has a first length and the second gate channel has a second length greater than the first length. A gate dielectric layer is formed in the first and second gate channels. A first plurality of work function metal layers is formed on the gate dielectric layer of the first gate channel. A second plurality of work function metal layers is formed on the gate dielectric layer of the second gate channel. A barrier layer is formed on each of the first and second plurality of work function metal layers, and the gate dielectric layer. The multi-channel semiconductor device further includes metal gate stacks formed on of the barrier layer such that the barrier layer is interposed between the metal gate stacks and the gate dielectric layer.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 28, 2015
    Applicant: International Business Machines Corporation
    Inventors: Su Chen Fan, Balasubramanian Pranatharthiharan, Rajasekhar Venigalla
  • Publication number: 20150140797
    Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.
    Type: Application
    Filed: January 30, 2015
    Publication date: May 21, 2015
    Inventors: John Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti
  • Patent number: 9035397
    Abstract: A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first TiN layer, a TaN layer, a second TiN layer, a high-k first dielectric layer, and an interfacial layer; etching the stack to result in a remaining stack that includes at least a remaining dummy layer, a first remaining TiN layer, and a remaining TaN layer; providing an etching stop layer on the substrate; providing a second dielectric layer on the etching stop layer; performing planarization according to the remaining dummy layer; removing the remaining dummy layer and a first portion of the first remaining TiN layer using a dry etching process; removing a second portion of the first remaining TiN layer using a wet etching process; and providing a metal gate layer on the remaining TaN layer.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Aileen Li, Jinghua Ni, David Han
  • Patent number: 9034712
    Abstract: A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Richard A. Phelps, Jed H. Rankin, Yun Shi
  • Patent number: 9024377
    Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: May 5, 2015
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Patent number: 9018049
    Abstract: A method for manufacturing an IGBT includes: forming oxide layers on the surfaces of the front and the back of an N-type substrate; forming a buffer layer in the surface of the back of the N-type substrate; forming protection layers on the surfaces of the oxide layers; removing the protection layer and the oxide layer overlying the front of the N-type substrate while reserving the oxide layer and the protection layer on the back of the N-type substrate for protection of the back of the N-type substrate; forming a front IGBT structure and applying a protection film on the surface of the front IGBT structure for protection of the front IGBT structure; removing the protection layer and the oxide layer overlying the back of the N-type substrate; forming a back IGBT structure and a back metal layer; and removing the protection film overlying the surface of the front IGBT structure.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: April 28, 2015
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Guangran Pan
  • Patent number: 9018700
    Abstract: In a general aspect, an apparatus can include a semiconductor layer of a first conductivity type, the semiconductor layer having a top-side surface. The apparatus can also include a well region of a second conductivity type opposite the first conductivity type, the well region being disposed in an upper portion of the semiconductor layer. The apparatus can further include a gate trench disposed in the semiconductor layer, the gate trench extending through the well region, and a drain contact disposed, at least in part, on the top-side surface of the semiconductor layer, the drain contact being adjacent to the well region. The apparatus can still further include an isolation trench disposed between the drain contact and the gate trench in the semiconductor layer, the isolation trench extending through the well region.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: April 28, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Ashok Challa
  • Patent number: 9018711
    Abstract: Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Hoon Kim, Xunyuan Zhang
  • Patent number: 9006090
    Abstract: A method for forming a shielded gate of a MOSFET includes steps as following: providing a semiconductor substrate having at least one trench, forming a bottom gate oxide region and a shielded gate poly region in the trench of the semiconductor substrate, forming an inter-poly oxide region on the shielded gate poly region through high temperature plasma deposition, poly etching back and oxide etching back; and forming a gate oxide region and a gate poly region on the inter-poly oxide region. By utilizing the etching back processes in replace of traditional chemical mechanical polishing processes, the manufacturing cost of manufacturing a shielded gate structure is reduced, and the total cost of manufacturing a FET is also reduced. Meanwhile, the gate charge is effectively reduced due to the shielded gate structure, so that the performance of a MOSFET is enhanced.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Mosel Vitelic Inc.
    Inventor: Richard Lai
  • Patent number: 9006091
    Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Chien-Ting Lin, Wen-Tai Chiang
  • Patent number: 9006085
    Abstract: A wafer processing method including a fixing step of providing a wafer on a protective member so that a device area of the wafer faces an unevenness absorbing member provided in a recess of the protective member and providing an adhesive outside the device area to thereby fix the protective member and the wafer, a grinding step of holding the protective member on a holding table in the condition where the back side of the wafer is exposed and next grinding the back side of the wafer by using a grinding unit to thereby reduce the thickness of the wafer to a predetermined thickness, and a removing step of removing the protective member from the wafer. The adhesive is locally provided outside of the device area, so that the protective member can be easily removed from the wafer without leaving the adhesive on the front side of each device.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Disco Corporation
    Inventor: Karl Heinz Priewasser
  • Patent number: 8999828
    Abstract: A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: April 7, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Shyue Seng (Jason) Tan
  • Patent number: 8999829
    Abstract: The control of gate widths is improved for system-on-a-chip (SoC) devices which require multiple gate dielectric “gate” thicknesses, e.g., for analog and digital processing on the same chip. A hard mask is formed to protect a thick gate while the thin gate region is etched to remove oxide (sometimes referred to as a preclean step). The patterned substrate is then processed to selectively deposit a second thickness of gate material. The thin gate may be silicon oxide and the physical thickness of the thin gate may be less than that of the thick gate. In a preferred embodiment, the substrate is not exposed to air or atmosphere after the hardmask is removed.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Adam Brand, Bingxi Wood
  • Patent number: 8987090
    Abstract: A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 24, 2015
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Marko Lemke, Rolf Weis, Stefan Tegen
  • Patent number: 8987101
    Abstract: A method of forming strained source and drain regions in a P-type FinFET structure is disclose. The method comprises depositing an isolation layer on the FinFET structure; applying a lithography and etching process to expose the isolation layer in two areas on opposite sides of the gate over the source/drain region of the FinFET, and etching through the exposed isolation layer to expose the semiconductive material of the source/drain region in the two areas; forming a recess in each of the source/drain region from the exposed semiconductive material; selectively epitaxially growing another semiconductive material in the recesses to increase the source/drain strain; and removing the rest of the isolation layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: March 24, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Yi Ding, Minghua Zhang, Jingxun Fang, Junhua Yan
  • Publication number: 20150079779
    Abstract: Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film.
    Type: Application
    Filed: November 24, 2014
    Publication date: March 19, 2015
    Inventors: Hiroo NISHI, Hiromitsu OSHIMA