Abstract: A method of manufacturing a semiconductor device includes forming an insulating isolation portion in a groove of a substrate, forming a projection portion in which an upper portion of the insulating isolation portion projects from a principal surface of the substrate, forming a sidewall spacer covering a side surface of the projection portion and part of the principal surface of the substrate along the side surface of the projection portion, and forming a first trench in the substrate by etching the substrate using the sidewall spacer as a mask.

Abstract: The invention discloses a method of fabricating a GOI silicon wafer, a GOI silicon wafer, and a method of GOI detection on the fabricated GOI silicon wafer, where the method of fabricating a GOI silicon wafer includes: in a process of fabricating a trench-type VDMOS, after a trench is formed and a gate oxide layer is grown, a poly-silicon layer is grown; and after the poly-silicon layer is grown, a mask of a metal layer is aligned with a silicon substrate with the poly-silicon layer grown, where the mask of the metal layer is a mask used in formation of the metal layer in the process of fabricating the VDMOS; and at least one pattern for GOI detection is formed on the silicon substrate with the poly-silicon layer grown, through the aligned mask of the metal layer in a photo-lithography to form a GOI silicon wafer.

Abstract: A fabrication method for a semiconductor device includes the step of forming a gate insulating film on the side of a trench, the bottom thereof, and the periphery thereof. The step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom and periphery of the trench using a high-density plasma chemical vapor deposition method. The thickness of the portions of the gate insulating film formed on the bottom and periphery of the trench is made larger than that of the portion of the gate insulating film formed on the side of the trench.

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract: In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.

Abstract: A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure.

Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

Abstract: A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode.

Abstract: A trench gate semiconductor device is disclosed which has a trench gate structure including an insulator in the upper portion of a first trench, the insulator being on a gate electrode; a source region having a lower end surface positioned lower than the upper surface of the gate electrode; a second trench in the surface portion of a semiconductor substrate between the first trenches, the second trench having a slanted inner surface providing the second trench with the widest trench width at its opening and a bottom plane positioned lower than the lower end surface of the source region, the slanted inner surface being in contact with the source region; and a p-type body-contact region in contact with the slanted inner surface of the second trench. The trench gate semiconductor device and its manufacturing method facilitate increasing the channel density and lowering the body resistance of the parasitic BJT.

Abstract: In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.

Abstract: A method is provided for fabricating a metal gate transistor. The method includes providing a semiconductor substrate; and forming a dielectric layer on the semiconductor substrate. The method also includes forming at least one dummy gate on the dielectric layer; and forming a first sidewall spacer around the dummy gate. Further, the method includes forming a gate dielectric layer with sidewalls protruding from sidewalls of the dummy gate and vertical to the semiconductor substrate by etching the dielectric layer using the first sidewall spacer and the dummy gate as an etching mask; and removing the dummy gate to form a trench. Further, the method also includes forming a metal gate in the trench; and forming a source region and a drain region in the semiconductor substrate.

Abstract: A trench Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device is disclosed. The trench MOSFET device includes a substrate, a body region, a source region, a dielectric layer, a metal layer, a contact hole, and a trench structure. The substrate includes a substrate layer and an epitaxial layer formed on the substrate layer; the body region is formed in the epitaxial layer; and the source region is formed in the body region of the epitaxial layer. Further, the dielectric layer is formed on the epitaxial layer; the metal layer is formed on the dielectric layer; and the contact hole is formed in the dielectric layer to connect the source region with the metal layer. In addition, the trench structure is formed in the epitaxial layer, and the trench structure includes a first trench that is a pectinate trench including a plurality of tooth trenches and a bar trench interconnecting the plurality of tooth trenches.

Abstract: A silicon carbide substrate is prepared which has a main surface covered with a silicon dioxide layer. In the silicon dioxide layer, an opening is formed by etching. In the opening, a residue resulting from the etching is on the silicon carbide substrate. The residue is removed by plasma etching in which only an inert gas is introduced. After removing the residue, under heating, a reactive gas is supplied to the silicon carbide substrate covered with the silicon dioxide layer having the opening formed therein. In this way, a trench is formed in the main surface of the silicon carbide substrate.

Abstract: A semiconductor device comprises a buried gate formed by being buried under a surface of a semiconductor substrate, a dummy gate formed on the buried gate, and a landing plug formed on a junction region of the semiconductor substrate being adjacent to the dummy gate.

Abstract: A device may include a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain. Methods, systems, and other devices are contemplated.

Abstract: A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the semiconductor substrate through the conductive layer, forming a recessed gate electrode in the trench, doping the conductive layer and the recessed first gate electrode, and forming a second gate electrode by etching the doped conductive layer.

Abstract: A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.

Abstract: Gate structures and methods of fabricating gate structures of semiconductor devices are provided. One method includes, for instance: providing a sacrificial layer over a substrate; patterning the sacrificial layer to form a gate opening within the sacrificial layer; providing a gate structure within the gate opening in the sacrificial layer; and removing the sacrificial layer, leaving the gate structure over the substrate. In enhanced aspects, the method includes: forming a reverse sidewall-spacer within the gate opening within the sacrificial layer, and after providing the gate structure, recessing the gate structure within the gate opening, and providing a gate cap within the gate recess in the gate structure.

Abstract: According to one embodiment, in a semiconductor device, a first semiconductor layer of a first conductivity type has a first impurity concentration. A second semiconductor layer of the first conductivity type is formed on the first semiconductor layer and has a second impurity concentration lower than the first impurity concentration. A field plate electrode is formed in a lower portion of a trench formed in the second semiconductor layer through a first insulating film so as to bury the lower portion of the trench. A second insulating film is formed in the upper portion of the trench so as to be in contact with the top surface of the field plate electrode. A gate electrode is formed in the upper portion of the trench through a gate insulating film so as to bury the upper portion of the trench to sandwich the second insulating film.

Abstract: There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion.

Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.

Abstract: A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.

Abstract: A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.

Abstract: A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a semiconductor layer 2 of a wide band gap semiconductor arranged on a principal surface of a substrate 1; a trench 5 arranged in the semiconductor layer and including a bottom surface, a plurality of main side surfaces, and a plurality of corner side surfaces each connecting together two adjacent main side surfaces; a gate insulating film 6 arranged on the bottom surface, the main side surfaces and the corner side surfaces of the trench 5; and a gate electrode 8 arranged in the trench, wherein the semiconductor layer includes a drift region 2d of a first conductivity type, and a body region 3 of a second conductivity type arranged on the drift region; the trench runs through the body region 3 and has the bottom surface inside the drift region; the corner side surfaces of the trench do not have a depressed portion; the gate insulating film 6 is thicker on the corner side surfaces of the trench than on the main side surfaces o

Abstract: In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

Abstract: The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree.

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract: Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit.

Abstract: Disclosed herein is a semiconductor device that includes a trench formed across active regions and the element isolation regions. A conductive film is formed at a lower portion of the trench, and a cap insulating film is formed at an upper portion of the trench. The cap insulating film has substantially the same planer shape as that of the conductive film.

Abstract: Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a conductor to form a recessed region and subsequently etching the conductor to form gates on the fins. The wet etching may include formation of recesses which are may be backfilled with a fill material to form spacers on the conductor. Portions of a plug may be removed during the wet etch to form overhanging spacers to provide further protection of the conductor during the dry etch.

Abstract: A semiconductor device includes a semiconductor substrate having a groove and an active region adjacent to the groove; a buried gate electrode in the groove; and a capacitor contact including a first portion and a second portion over the first portion. The first portion is greater in horizontal dimension than the second portion. The first portion has a bottom surface that is in contact with an upper surface of the active region.

Abstract: A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed.

Abstract: Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.

Abstract: Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.

Abstract: An embodiment for realizing a power device with trench-gate structure integrated on a semiconductor substrate, and including etching the semiconductor substrate to make a first trench having first side walls and a first bottom; and further etching said semiconductor substrate to make a second trench inside the first trench, realized in a self-aligned way and below this first trench, the first trench and the second trench defining the trench-gate structure with a bird beak-like transition profile suitable for containing a gate region.

Abstract: Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.

Abstract: Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. The panel divides the stack into a first section on a first side of the panel and a second section on a second side of the panel. Memory cell stacks are between the channel material panel and the control gate material. The memory cell stacks include cell dielectric material shaped as containers having open ends pointing toward the channel material panel, and include charge-storage material within the containers. Some embodiments include methods of forming semiconductor constructions.

Abstract: Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a gate stack disposed on the semiconductor substrate. The gate stack includes a high-k dielectric material layer, a titanium-rich TiN layer over the high-k dielectric layer, and a metal layer disposed over the titanium-rich TiN layer. The metal layer includes aluminum.

Abstract: Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include a trench in a substrate. The semiconductor devices may also include a bulk electrode within opposing sidewalls of the trench. The semiconductor devices may further include a liner electrode between the bulk electrode and the opposing sidewalls of the trench. The liner electrode may include a sidewall portion between a sidewall of the bulk electrode and one of the opposing sidewalls of the trench.

Abstract: A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.

Abstract: A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.

Abstract: The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole.

Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.

Abstract: Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.