Having Diverse Electrical Device Patents (Class 438/59)
  • Patent number: 10790262
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 29, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Liang Wang, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
  • Patent number: 10712456
    Abstract: Disclosed herein is a method comprising: obtaining a substrate comprising an electronic system in or on the substrate, and a plurality of electric contacts on a first surface of the substrate, the electronic system being electrically connected to the electric contacts; obtaining a chip comprising an X-ray absorption layer, the X-ray absorption layer comprising an electrode; electrically connecting the electrode to at least one of the electric contacts by bonding the chip to the substrate; and thinning the substrate at a surface opposite the first surface.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 14, 2020
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 10686030
    Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
  • Patent number: 10665703
    Abstract: The lateral bipolar junction transistor has a silicon carbide layer, the silicon carbide layer comprises a base region with a first conductivity type, a collector region with a second conductivity type and an emitter region with a second conductivity type. The collector region and the emitter region are within the base region, and the base region, collector region and emitter region are all arranged along an upper surface of the silicon carbide layer.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 26, 2020
    Assignee: Raytheon Systems Limited
    Inventors: David Trann Clark, Ewan Philip Ramsay
  • Patent number: 10615214
    Abstract: A semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: April 7, 2020
    Assignee: SONY CORPORATION
    Inventor: Takashi Yokoyama
  • Patent number: 10228473
    Abstract: Disclosed herein is a method of making an apparatus suitable for detecting x-ray, the method comprising: obtaining a substrate having a first surface and a second surface, wherein the substrate comprises an electronic system in or on the substrate, wherein the substrate comprises a plurality of electric contacts are on the first surface; obtaining a first chip comprising a first X-ray absorption layer, wherein the first X-ray absorption layer comprises an electrode; bonding the first chip to the substrate such that the electrode of the first X-ray absorption layer is electrically connected to at least one of the electric contacts.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 12, 2019
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 10150140
    Abstract: A superhydrophobic and self-cleaning surface including a substrate and a superhydrophobic layer. The superhydrophobic layer having a reacted form of octadecyltrichlorosilane. The octadecyltrichlorosilane is disposed on and crosslinked to a surface of the substrate via surface hydroxyl groups. The surface exhibits a rms roughness of 40 nm to 60 nm, a water contact angle of 155° to 180°, and a contact angle hysteresis of less than 15°. A method of preparing the substrate with a superhydrophobic and self-cleaning surface including treating a substrate with a plasma treatment, contacting the substrate with water or an alcohol to form an hydroxylated substrate, contacting the hydroxylated substrate with a solution of octadecyltrichlorosilane in an alkane solvent at a concentration in the range of 0.05 M to 0.3 M, and drying the solution on to the substrate under ambient air to form the superhydrophobic and self-cleaning surface on the substrate.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 11, 2018
    Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: Asif Matin, Necar Merah
  • Patent number: 10061040
    Abstract: Disclosed herein is a method of making an apparatus suitable for detecting x-ray, the method comprising: obtaining a substrate having a first surface and a second surface, wherein the substrate comprises an electronics system in or on the substrate, wherein the substrate comprises a plurality of electric contacts are on the first surface; obtaining a first chip comprising a first X-ray absorption layer, wherein the first X-ray absorption layer comprises an electrode; bonding the first chip to the substrate such that the electrode of the first X-ray absorption layer is electrically connected to at least one of the electrical contacts.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 28, 2018
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 10043845
    Abstract: A structure includes a silicon substrate; silicon readout circuitry disposed on a first portion of a top surface of the substrate and a radiation detecting pixel disposed on a second portion of the top surface of the substrate. The pixel has a plurality of radiation detectors connected with the readout circuitry. The plurality of radiation detectors are composed of at least one visible wavelength radiation detector containing germanium and at least one infrared wavelength radiation detector containing a Group III-V semiconductor material. A method includes providing a silicon substrate; forming silicon readout circuitry on a first portion of a top surface of the substrate and forming a radiation detecting pixel, on a second portion of the top surface of the substrate, that has a plurality of radiation detectors formed to contain a visible wavelength detector composed of germanium and an infrared wavelength detector composed of a Group III-V semiconductor material.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra K. Sadana, Robert L. Wisnieff
  • Patent number: 10020333
    Abstract: In this solid-state imaging device, the sameness of the potential distributions in pixels, in a region from a photodiode of a transfer transistor to a floating diffusion in a charge transfer path, is improved. The solid-state imaging device includes a first transfer transistor including a first photodiode, a first gate electrode, and a first floating diffusion, a second transfer transistor including a second photodiode, a second gate electrode, and a second floating diffusion, a third transfer transistor including a third photodiode, a third gate electrode, and a third floating diffusion, and a reset transistor including a diffusion layer, which is a source or drain region, and a reset gate. The first to third floating diffusions and the diffusion layer of the reset transistor are separated from each other, and are electrically connected to each other via an interconnect. The first to third photodiodes are arrayed one-dimensionally.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 10, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Noriyuki Nakamura, Mitsuo Sekisawa
  • Patent number: 10021357
    Abstract: An image capturing apparatus includes: photoelectric converting elements having a light reception sensitivity to light in a wavelength band from 600 to 2500 nm, and receiving an object light flux to output pixel signals; n types of wavelength filters (n>4) allowing passage therethrough of light included in the flux and is in wavelength bands being respectively different, each including the wavelength band; and an image data generator generating image data using the output from an element among those having received the flux passed through one of m types of the wavelength filters (3?m<n) a combination determined based on a predetermined condition being determined such that among the respective wavelength bands of the m types of filters, a shortest-wavelength side wavelength band and a longest-wavelength side wavelength band overlap, and each filter among the m types allowing passage therethrough of light in the wavelength band including a predetermined effective wavelength band.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: July 10, 2018
    Assignee: NIKON CORPORATION
    Inventors: Junya Hagiwara, Yusuke Takanashi, Kiyoshige Shibazaki
  • Patent number: 10002711
    Abstract: The present disclosure generally relates to capacitors having a multilayer dielectric material between two electrodes. The multilayer dielectric material can have a small thickness with little to no breakdown strength reduction. By utilizing a multilayer dielectric structure in a capacitor, not only can the breakdown strength remain at an acceptable level, but the collective thickness of the capacitor may be reduced to accommodate the higher density pixels for display devices or any device that utilizes a capacitor.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 19, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Dapeng Wang, Yixuan Wu, Gaku Furuta, Tae Kyung Won, Beom Soo Park
  • Patent number: 9973700
    Abstract: A solid-state imaging device, a method for driving the solid-state imaging device, and an electronic apparatus capable of suppressing occurrence of motion distortion while realizing widening of dynamic range and in turn realizing a higher image quality are provided.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: May 15, 2018
    Assignee: Brillnics Japan Inc.
    Inventors: Shunsuke Okura, Isao Takayanagi
  • Patent number: 9941419
    Abstract: A thin-film monolithically integrated solar module with a solar cell, an integrated energy storage device, and a controller may be provided. It may comprise a thin-film solar cell, having at least one solar diode, on a transparent substrate, a thin-film energy storage device, and an electronic controller comprising at least one thin-film transistor above the thin-film energy storage device. The electronic controller may be electrically connected to the thin-film solar cell and the thin-film energy storage device by vias. The named functional units may build a monolithically integrated device on one substrate.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Johann H. Bredel, Hans-Juergen Eickelmann, Ruediger Kellmann, Hartmut Kuehl, Markus Schmidt
  • Patent number: 9911784
    Abstract: A structure includes a silicon substrate; silicon readout circuitry disposed on a first portion of a top surface of the substrate and a radiation detecting pixel disposed on a second portion of the top surface of the substrate. The pixel has a plurality of radiation detectors connected with the readout circuitry. The plurality of radiation detectors are composed of at least one visible wavelength radiation detector containing germanium and at least one infrared wavelength radiation detector containing a Group III-V semiconductor material. A method includes providing a silicon substrate; forming silicon readout circuitry on a first portion of a top surface of the substrate and forming a radiation detecting pixel, on a second portion of the top surface of the substrate, that has a plurality of radiation detectors formed to contain a visible wavelength detector composed of germanium and an infrared wavelength detector composed of a Group III-V semiconductor material.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra K. Sadana, Robert L. Wisnieff
  • Patent number: 9762821
    Abstract: A unit pixel of an image sensor includes a charge generation unit, a signal generation unit, and a ground control transistor. The charge generation unit generates photo-charges in response to incident light and provides the photo-charges to a floating diffusion area in response to a transmission control signal. The signal generation unit generates an analog signal having a magnitude corresponding to an electrical potential of the floating diffusion area based on a reset control signal and a row selection signal. The ground control transistor is coupled between the floating diffusion area and a ground voltage, and is turned on in response to a ground control signal.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ho Lee, Hee-Sang Kwon
  • Patent number: 9659987
    Abstract: An active pixel sensor (APS) with a vertical transfer gate and a pixel transistor (e.g., a transfer transistor, a source follower transistor, a reset transistor, or a row select transistor) electrically isolated by an implant isolation region is provided. A semiconductor substrate has a photodetector buried therein. The vertical transfer gate extends into the semiconductor substrate with a channel region in electrical communication with the photodetector. The pixel transistor is arranged over the photodetector and configured to facilitate the pixel operation (e.g., reset, signal readout, etc.). The implant isolation region is arranged in the semiconductor substrate and surrounds and electrically isolates the pixel transistor. A method for manufacturing the APS is also provided.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Jui Wang, Yuichiro Yamashita, Seiji Takahashi, Jen-Cheng Liu
  • Patent number: 9622350
    Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.
    Type: Grant
    Filed: September 28, 2013
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Mihir K. Roy, Mathew J. Manusharow
  • Patent number: 9559130
    Abstract: A method of making a composite pixel image sensor includes forming an image sensing array; and forming a depth sensing pixel. The depth sensing pixel includes a depth sensing photodiode; a first photo storage diode; and a first transistor configured to selectively couple the depth sensing photodiode to the first photo storage diode. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the depth sensing photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node. The method includes bonding the image sensing array to the depth sensing pixel.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: January 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Calvin Yi-Ping Chao, Kuo-Yu Chou, Chih-Min Liu
  • Patent number: 9461582
    Abstract: Methods and structures for extracting at least one electric parametric value from a back contact solar cell. According to one embodiment, a first layer of electrically conductive metal having an interdigitated pattern of base electrodes and emitter electrodes is formed on the backside surface of a semiconductor solar cell substrate. An electrically insulating layer is formed on the first layer of electrically conductive metal providing electrical isolation between the first layer of electrically conductive metal and a second layer of electrically conductive metal. Vias are formed in the electrically insulating layer providing access to the first layer of electrically conductive metal. A second electrically conductive metallization layer is formed on the electrically insulating layer and contacts the first electrically conductive metal layer through the vias.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: October 4, 2016
    Assignee: Solexel, Inc.
    Inventors: Swaroop Kommera, Pawan Kapur, Mehrdad M. Moslehi
  • Patent number: 9368716
    Abstract: A magnetic tunnel junction storage element for a spin transfer torque magnetoresistive random access memory (STT-MRAM) bit cell includes a bottom electrode layer, a pinned layer adjacent to the bottom electrode layer, a dielectric layer encapsulating a portion of the bottom electrode layer and the pinned layer, the dielectric layer including sidewalls that define a hole adjacent to a portion of the pinned layer, a tunneling barrier adjacent to the pinned layer, a free layer adjacent to the tunneling barrier, and a top electrode adjacent to the free layer, wherein a width of the bottom electrode layer and/or the pinned barrier in a first direction is greater than a width of a contact area between the pinned layer and the tunneling barrier in the first direction. Also a method of forming an STT-MRAM bit cell.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: June 14, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Seung H. Kang, Xiaochun Zhu
  • Patent number: 9368668
    Abstract: A method comprises preparing a semiconductor substrate having a first portion, and a second portion including a first region and a second region; forming an active region in the first portion, and an isolating portion of an insulator defining the active region in the second portion; forming a first semiconductor region of a first conductivity type configuring a first photoelectric conversion element, a second semiconductor region of first conductivity type configuring a second photoelectric conversion element, a third semiconductor region of first conductivity type, a fourth semiconductor region of the conductivity type, a first gate electrode configuring a first transfer transistor, and a second gate electrode configuring a second transfer; exposing the first region of the semiconductor substrate, and performing ion implantation masked by a first photoresist pattern covering the second region of the semiconductor substrate, thus forming a fifth semiconductor region of a second conductivity type.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: June 14, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichi Tazoe, Yu Arishima, Akira Okita, Kazuki Ohshitanai, Yasuharu Ota
  • Patent number: 9331121
    Abstract: A method of manufacturing a photoelectric conversion apparatus which includes a pixel circuit section having a well where a photoelectric conversion element and an amplification element configured to generate a signal based on an amount of charge generated in the photoelectric conversion element are arranged, and a peripheral circuit section having a MOS transistor. The method includes forming a dielectric film for covering the photoelectric conversion element, the amplification element, and a gate electrode of the MOS transistor and forming, by etching the dielectric film, a side spacer by remaining a portion of the dielectric film on a side surface of the gate electrode while protecting by a resist, wherein an opening is formed in the dielectric film of the pixel circuit section with the etching, and a contact for defining a potential of the well is formed through the opening.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 3, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yusuke Onuki, Hiroaki Naruse, Masashi Kusukawa, Katsunori Hirota
  • Patent number: 9214502
    Abstract: Embodiments of the invention are directed to IR photodetectors with gain resulting from the positioning of a charge multiplication layer (CML) between the cathode and the IR sensitizing layer of the photodetector, where accumulating charge at the CML reduces the energy difference between the cathode and the CML to promote injection of electrons that result in gain for an electron only device. Other embodiments of the invention are directed to inclusion of the IR photodetectors with gain into an IR-to-visible up-conversion device that can be used in night vision and other applications.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: December 15, 2015
    Assignees: University of Florida Research Foundation, Inc., Nanoholdings, LLC
    Inventors: Franky So, Do Young Kim, Bhabendra K. Pradhan
  • Patent number: 9171879
    Abstract: A method for fabricating a sensor, comprising: forming a pattern of a bias line on a base substrate by using a first patterning process; forming a pattern of a transparent electrode, a pattern of a photodiode, a pattern of a receive electrode, a pattern of a source electrode, a pattern of a drain electrode, a pattern of a data line and a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer, a pattern of a first passivation layer, a pattern of a gate electrode and a pattern of a gate line by using a third patterning process. The above method reduces the number of used mask in the fabrication processes as well as the production cost and simplifies the production process, thereby significantly improves the production capacity and the yield rate.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 27, 2015
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tiansheng Li, Xiaohui Jiang, Shaoying Xu, Zhenyu Xie
  • Patent number: 9164525
    Abstract: A photovoltaic device includes at least one photovoltaic cell and a DC/DC converter electrically coupled to the at least one photovoltaic cell. The at least one photovoltaic cell and the DC/DC converter are integrated into a photovoltaic package.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: October 20, 2015
    Assignee: APOLLO PRECISION FUJIAN LIMITED
    Inventors: Robert W. Erickson, Jr., Steven Croft, Shawn Everson, Aaron Schultz
  • Patent number: 9147709
    Abstract: A solid-state image sensor includes a structure having a semiconductor layer in which a plurality of photoelectric converters are arranged, a light blocking member arranged above a face of the structure and including a plurality of circular openings each corresponding to at least one of the photoelectric converters, a first layer configured to cover the light blocking member, and exposed portions of the face of the structure, that are formed by the plurality of circular openings, and a second layer arranged to cover the first layer and having a refractive index higher than that of the first layer, wherein an interface between the first layer and the second layer includes lens faces protruding toward the exposed portions.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: September 29, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mineo Shimotsusa
  • Patent number: 9136296
    Abstract: A photodiode includes a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type that is opposite to the first conductivity type of the first semiconductor layer, and a third semiconductor layer interposed between the first semiconductor layer and the second semiconductor layer. An edge of the first semiconductor layer is inset from an edge of the second semiconductor layer.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: September 15, 2015
    Assignee: SONY CORPORATION
    Inventor: Tsutomu Tanaka
  • Patent number: 9059167
    Abstract: The present invention relates to bonded semiconductor integrated circuits, more specifically to a structure to protect against crack propagation into any layer of such integrated circuits. Embodiments of the present invention may include a first semiconductor substrate having a first layer bonded to second layer of a substantially thinner second semiconductor substrate by a bonding layer. The first layer may contain a crack stop. The crack stop may be in contact with a circumferential wall, made up of posts, that extends through the bonding layer, the second layer, and the second substrate.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Griesemer, William F. Landers, Ian D. Melville, Thomas M. Shaw, Huilong Zhu
  • Publication number: 20150144872
    Abstract: A semiconductor device includes a substrate supporting a plurality of layers that include at least one modulation doped quantum well (QW) structure offset from a quantum dot in quantum well (QD-in-QW) structure. The modulation doped QW structure includes a charge sheet spaced from at least one QW by a spacer layer. The QD-in-QW structure has QDs embedded in one or more QWs. The QD-in-QW structure can include at least one template/emission substructure pair separated by a barrier layer, the template substructure having smaller size QDs than the emission substructure. A plurality of QD-in-QW structures can be provided to support the processing (emission, absorption, amplification) of electromagnetic radiation of different characteristic wavelengths (such as optical wavelengths in range from 1300 nm to 1550 nm).
    Type: Application
    Filed: November 20, 2014
    Publication date: May 28, 2015
    Applicants: Opel Solar, Inc., The University of Connecticut
    Inventor: Geoff W. Taylor
  • Publication number: 20150145094
    Abstract: A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 28, 2015
    Inventors: Chien-Hung LIU, Ying-Nan WEN
  • Publication number: 20150145092
    Abstract: A semiconductor device includes a semiconductor substrate, a photoelectric conversion element, a first isolation insulating film, and a current blocking region. The first isolation insulating film is formed around the photoelectric conversion element. The current blocking region is formed in a region between the photoelectric conversion element and the first isolation insulating film. The current blocking region includes an impurity diffusion layer, and a defect extension preventing layer disposed in contact with the impurity diffusion layer to form a twin with the impurity diffusion layer. The defect extension preventing layer has a different crystal structure from that of the impurity diffusion layer. At least a part of the current blocking region is disposed in contact with the first isolation insulating film.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 28, 2015
    Inventor: Keiichi ITAGAKI
  • Publication number: 20150144889
    Abstract: An organic x-ray detector and a method of making the organic x-ray detector are disclosed. The x-ray detector includes a TFT array disposed on a substrate, an organic photodiode layer disposed on the TFT array, a barrier layer disposed on the photodiode layer, and a scintillator layer disposed on the barrier layer, such that the barrier layer includes at least one inorganic material.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: General Electric Company
    Inventors: Kwang Hyup An, Aaron Judy Couture, Gautam Parthasarathy, Ri-An Zhao, Jie Jerry Liu
  • Publication number: 20150147843
    Abstract: A method of manufacturing a photoelectric conversion apparatus which includes a pixel circuit section having a well where a photoelectric conversion element and an amplification element configured to generate a signal based on an amount of charge generated in the photoelectric conversion element are arranged, and a peripheral circuit section having a MOS transistor. The method includes forming a dielectric film for covering the photoelectric conversion element, the amplification element, and a gate electrode of the MOS transistor and forming, by etching the dielectric film, a side spacer by remaining a portion of the dielectric film on a side surface of the gate electrode while protecting by a resist, wherein an opening is formed in the dielectric film of the pixel circuit section with the etching, and a contact for defining a potential of the well is formed through the opening.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 28, 2015
    Inventors: Yusuke Onuki, Hiroaki Naruse, Masashi Kusukawa, Katsunori Hirota
  • Publication number: 20150137088
    Abstract: The present invention relates to a radiation detector with organic photodiodes and to a method of producing such a radiation detector. The TFT backplane (103, 104) is placed between the scintillator (101) and the organic photodiode layer stack (105, 106, 107, 108). This implies the use of transparent TFT-electronics, e.g., a-Si with back-thinned glass or an organic TFT on foil. The geometrical order enables a multitude of possible stack built- ups for OPDs and has advantages for encapsulation and manufacturing.
    Type: Application
    Filed: June 13, 2013
    Publication date: May 21, 2015
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Matthias Simon, Jorrit Jorritsma
  • Publication number: 20150129943
    Abstract: Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode.
    Type: Application
    Filed: November 3, 2014
    Publication date: May 14, 2015
    Inventors: Nanako Kato, Toshifumi Wakano
  • Publication number: 20150129836
    Abstract: Photonic devices monolithically integrated with CMOS are disclosed, including sub-100 nm CMOS, with active layers comprising acceleration regions, light emission and absorption layers, and optional energy filtering regions. Light emission or absorption is controlled by an applied voltage to deposited films on a pre-defined CMOS active area of a substrate, such as bulk Si, bulk Ge, Thick-Film SOI, Thin-Film SOI, Thin-Film GOI.
    Type: Application
    Filed: December 17, 2014
    Publication date: May 14, 2015
    Inventor: Carlos J.R.P. Augusto
  • Patent number: 9029170
    Abstract: A magnetic tunnel junction (MTJ) device is formed by a process that includes forming a trench in a substrate and depositing an MTJ structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The process includes applying reverse photo etching to remove material that is not directly over the trench. The process also includes plagiarizing the MTJ structure without performing a photo-etch process on the MTJ structure.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 12, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Patent number: 9029241
    Abstract: A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 12, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mineo Shimotsusa, Takeshi Ichikawa, Yasuhiro Sekine
  • Patent number: 9029182
    Abstract: A method of manufacturing a solid-state image sensor having a pixel region and a peripheral circuit region, includes forming an oxide film on a semiconductor substrate, forming an insulating film on the oxide film, forming a first opening in the insulating film and the oxide film in the peripheral circuit region, forming a trench in the semiconductor substrate in the peripheral circuit region by etching the semiconductor substrate through the first opening using the insulating film as a mask, forming a second opening in the insulating film to penetrate through the insulating film in the pixel region and to reach a predetermined depth of the oxide film, and forming insulators in the trench and the second opening.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: May 12, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Aoki
  • Patent number: 9029181
    Abstract: Methods and apparatus relating to providing a collection grid suitable for use in PV modules. The disclosed collection grid may be at least partially applied to a protective laminate sheet in a manner that removes the high temperature requirements of conventional screen printed collection grids, to avoid unwanted heat-related deformation of the laminate sheet.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: May 12, 2015
    Assignee: Hanergy Hi-Tech Power (HK) Limited
    Inventors: Zulima Rhodes, Darren Verebelyi
  • Publication number: 20150123134
    Abstract: An infrared detector includes a substrate, a light blocking layer on the substrate, a lower electrode on the light blocking layer, the lower electrode electrically connected to the light blocking layer, a lower insulating layer on the light blocking layer, a first semiconductor layer on the lower insulating layer, a first source electrode and a first drain electrode on the first semiconductor layer, an upper insulating layer on the first semiconductor layer, and a first gate electrode on the upper insulating layer, the first gate electrode electrically connected to the lower electrode, where the first semiconductor layer includes a zinc and a nitrogen, and the first semiconductor layer is configured to generate electric charges by reacting with an infrared ray.
    Type: Application
    Filed: March 20, 2014
    Publication date: May 7, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Seong-Min Wang, Byeong-Hoon Cho
  • Publication number: 20150123179
    Abstract: A solid-state imaging device includes two-dimensionally arranged pixels, and each pixel includes a photoelectric conversion element configured to generate charges according to a light amount of incident light and accumulate the charges therein; and at least one of an amplification transistor configured to amplify a voltage corresponding to the charges accumulated in the photoelectric conversion element, a readout transistor configured to read a signal of the voltage amplified by the amplification transistor, and a reset transistor configured to reset the charges accumulated in the photoelectric conversion element, a channel region of each transistor being formed in a direction perpendicular to a substrate.
    Type: Application
    Filed: October 27, 2014
    Publication date: May 7, 2015
    Inventor: Yoshiaki Kikuchi
  • Publication number: 20150123157
    Abstract: A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.
    Type: Application
    Filed: September 10, 2014
    Publication date: May 7, 2015
    Applicant: Skorpios Technologies, Inc.
    Inventors: John Dallesasse, Stephen B. Krasulick, Timothy Creazzo, Elton Marchena
  • Publication number: 20150123119
    Abstract: Provided are an image sensor and a method of manufacturing method of manufacturing the image sensor. The image sensor includes a substrate, photoelectric transducers and switching elements formed in layers on the substrate in this order. Each of the photoelectric transducers includes a hydrogenated amorphous silicon layer. Each of the switching elements includes an amorphous oxide semiconductor layer. The image sensor further includes a blocking layer arranged between the hydrogenated amorphous silicon layers of the photoelectric transducers and the amorphous oxide semiconductor layers of the switching elements, where the blocking layer suppresses penetration of hydrogen separated from the hydrogenated amorphous silicon layers.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 7, 2015
    Applicant: NLT TECHNOLOGIES, LTD.
    Inventors: Hiroyuki SEKINE, Takayuki ISHINO, Toru UKITA, Fuminori TAMURA, Kazushige TAKECHI
  • Patent number: 9024320
    Abstract: Embodiments of the present invention disclose a sensor and a method for manufacturing the same, the sensor comprising a plurality of sensing units arranged in array, each of which comprises a thin film transistor device and a photodiode sensor device and the photodiode sensor device comprising: a receiving electrode connected with a drain of the thin film transistor device, a photodiode located on the receiving electrode and covering the thin film transistor device, a transparent electrode on the photodiode and a biasing line connected with the transparent electrode.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: May 5, 2015
    Assignee: Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Tiansheng Li, Changjiang Yan, Shaoying Xu, Zhenyu Xie
  • Patent number: 9024416
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 5, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Hung Chen, Ming-Tse Lin, Chien-Li Kuo, Kuei-Sheng Wu
  • Publication number: 20150115338
    Abstract: A solid-state imaging device according to an embodiment includes photoelectric conversion devices, a dopant layer, a low concentration region, and a transistor. The photoelectric conversion devices are disposed on a semiconductor layer. The dopant layer is disposed on a layer same as the semiconductor layer where photoelectric conversion devices are arrayed, and includes dopant having a conductivity type reverse to a charge accumulating region of the photoelectric conversion device. The low concentration region is disposed inside the dopant layer and has dopant concentration lower than the dopant layer. A transistor includes an active region disposed on the dopant layer.
    Type: Application
    Filed: September 11, 2014
    Publication date: April 30, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisayuki TARUKI, Nagataka TANAKA
  • Publication number: 20150118781
    Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.
    Type: Application
    Filed: January 2, 2015
    Publication date: April 30, 2015
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung, Pao-Tung Chen, Jen-Cheng Liu
  • Publication number: 20150115387
    Abstract: According to one embodiment, the present invention relates to a method for manufacturing a photovoltaic device comprising a photovoltaic cell or a plurality of photovoltaic cells (PV cells) connected to an electronic integrated circuit having at least one electrical contact area. A stack comprising the PV cell(s) is produced separately from the electronic integrated circuit, the electronic integrated circuit is then transferred to said stack comprising the PV cell(s). During this transfer, connection areas carried by the PV cell(s) are brought into contact with matching connection areas carried by the electronic integrated circuit.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Julien BUCKLEY, Haykel BEN JAMAA