Abstract: A method of fabricating a semiconductor device having a transistor with a metal gate electrode and a gate dielectric layer includes forming a protective layer on the gate dielectric layer and forming a metal gate electrode over the protective layer. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

Abstract: A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode.

Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

Abstract: A method for fabricating a semiconductor device includes: forming a GaN-based semiconductor layer on a substrate; forming a gate insulating film of aluminum oxide on the GaN-based semiconductor layer at a temperature equal to or lower than 450° C.; forming a protection film on an upper surface of the gate insulating film; performing a process with an alkaline solution in a state in which the upper surface of the gate insulating film is covered with the protection film; and forming a gate electrode on the gate insulating film.

Abstract: A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.

Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.

Abstract: The invention provides a stacked gate structure and metal-oxide-semiconductor including the same, and method for manufacturing the stacked gate structure. The stacked gate structure comprises a substrate, a semiconductor layer positioned on the substrate, a gate dielectric positioned on the semiconductor layer, and a gate electrode layer positioned on the gate dielectric, which the gate dielectric comprises a composite oxide layer composed of lanthanum oxide (La2O3) and hafnium oxide (HfO2).

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract: A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter.

Abstract: Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.

Abstract: The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type made of SiC, a body region of a second conductivity type formed on a surface layer portion of the semiconductor layer, a gate trench dug down from a surface of the semiconductor layer with a bottom surface formed on a portion of the semiconductor layer under the body region, source regions of the first conductivity type formed on a surface layer portion of the body region adjacently to side surfaces of the gate trench, a gate insulating film formed on the bottom surface and the side surfaces of the gate trench so that the thickness of a portion on the bottom surface is greater than the thickness of portions on the side surfaces, a gate electrode embedded in the gate trench through the gate insulating film, and an implantation layer formed on a portion of the semiconductor layer extending from the bottom surface of the gate trench to an intermediate portion of the semiconductor layer in the t

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.

Abstract: Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.

Abstract: According to one embodiment, a semiconductor device includes an active area that is formed on a semiconductor substrate, a trench that isolates the active area, a nitride film that is buried in the trench, an air gap that is formed above the nitride film along the trench, and a gate electrode that is formed on the active area to span the trench through the air gap.

Abstract: The present invention discloses a method for manufacturing a semiconductor device. According to the method provided by the present disclosure, a dummy gate is formed on a substrate, removing the dummy gate to form an opening having side walls and a bottom gate, a dielectric material is formed on at least a portion of the sidewalls of the opening and the bottom surface of the opening, and a pre-treatment is performed to a portion of the dielectric material layer on the sidewalls of the opening, and thus the properties of the dielectric material is changed, and then the pre-treated dielectric material on the sidewalls of the opening is removed by a selective process. The semiconductor device manufactured by using the method of the present disclosure is capable of effectively reducing parasitic capacitance.

Abstract: Structures and methods for reducing backside polysilicon peeling are disclosed. A structure includes a substrate having a first side and a second opposite side, a first dielectric layer on the second side of the substrate extending in a direction from an edge of the substrate towards a center of the substrate, a high-k layer on the first dielectric layer, and a polysilicon layer on the high-k layer. The first dielectric layer has a first innermost sidewall relative to the center of the substrate, and the high-k layer has a second innermost sidewall relative to the center of the substrate. The second innermost sidewall is within 2 millimeters from the first innermost sidewall in a direction parallel to the second side. The polysilicon layer extends towards the center of the substrate further than the first innermost sidewall.

Abstract: Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

Abstract: Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate having formed thereon a sacrificial silicon oxide layer, an interlayer dielectric layer formed over the sacrificial silicon oxide layer, and a dummy gate structure formed over the sacrificial silicon oxide layer and within the interlayer dielectric layer, removing the dummy gate structure to form an opening within the interlayer dielectric layer, and removing the sacrificial silicon oxide layer within the opening to expose the semiconductor substrate within the opening. The method further includes the steps of thermally forming an oxide layer on the exposed semiconductor substrate within the opening, subjecting the thermally formed oxide layer to a decoupled plasma oxidation treatment, and etching the thermally formed oxide layer using a self-saturated wet etch chemistry. Still further, the method includes depositing a high-k dielectric over the thermally formed oxide layer within the opening.

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract: Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel oxide may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner tunnel oxide in SLC blocks may allow a lower program voltage to be used, which may improve endurance. A thicker tunnel oxide in MLC blocks may improve data retention. A thinner IPD may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner IPD may provide a higher coupling ratio, which may allow a lower program voltage. A lower program voltage in SLC blocks can improve endurance. A thicker IPD in MLC blocks can prevent or reduce read disturb. SLC blocks may have a different number of data word lines than MLC blocks.

Abstract: The invention provides a B4-flash device and the manufacture method thereof, wherein the device comprises a substrate, a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, and all those layers are disposed on the substrate in sequence. The first silicon oxide layer comprises a first section, a second section and a third section, and all those sections are along the channel direction in sequence. The thickness ratio among the first section, the second section and the third section is (1.5-2.5):(0.8-1.2):(1.5-2.5). The embodiments of the present invention use the non-uniform silicon oxide to slow down the degeneration of the silicon oxide and to relieve the effect of the programming of the electron injection and the erasing of the holes injection as well. As a result, the reliability of the device is improved.

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract: A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a PFET base covered with a high-k dielectric, a layer of annealed TiN, a layer of unannealed TiN, a thin barrier over the unannealed TiN, and n-type metal over the thin barrier.

Abstract: The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing an upper portion of the final work function metal, for instance a titanium nitride material in P-channel transistors. In some illustrative embodiments, the selective removal of the metal-containing electrode material in an upper portion of the gate opening may be accomplished without unduly increasing overall process complexity.

Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

Abstract: A transistor includes a semiconductor layer and a gate structure located on the semiconductor layer. The gate structure includes a first dielectric layer. The first dielectric layer includes a doped region and an undoped region below the doped region. A second dielectric layer is located on the first dielectric layer, and a first metal nitride layer is located on the second dielectric layer. The doped region of the first dielectric layer comprises dopants from the second dielectric layer. Source and drain regions in the semiconductor layer are located on opposite sides of the gate structure.

Abstract: A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first TiN layer, a TaN layer, a second TiN layer, a high-k first dielectric layer, and an interfacial layer; etching the stack to result in a remaining stack that includes at least a remaining dummy layer, a first remaining TiN layer, and a remaining TaN layer; providing an etching stop layer on the substrate; providing a second dielectric layer on the etching stop layer; performing planarization according to the remaining dummy layer; removing the remaining dummy layer and a first portion of the first remaining TiN layer using a dry etching process; removing a second portion of the first remaining TiN layer using a wet etching process; and providing a metal gate layer on the remaining TaN layer.

Abstract: A semiconductor device includes a PFET transistor (a PMOS FET) having a poly(silicon) layer with a p-type doped portion and an n-type doped portion. The p-type doped portion is located above a channel region of the transistor and the n-type doped portion is located in an end portion of the poly layer outside the channel region. The poly layer may be formed by doping portions of an amorphous silicon layer with either the p-type dopant or the n-type dopant and then annealing the amorphous silicon layer to diffuse the dopants and crystallize the amorphous silicon to form polysilicon. The n-type doped portion of the poly layer may provide an electrical shunt in the end portion of the poly layer to reduce any effects of insufficient diffusion of the p-type dopant in the poly layer.

Abstract: A method for manufacturing a dual workfunction semiconductor device using a hybrid gate last integration scheme is described. According to one embodiment, the method includes heat-treating a first high-k film at a first heat-treating temperature to diffuse a first chemical element from a first cap layer into the first high-k film in a device region to form a first modified high-k film. The method further includes a gate-last processing scheme to form recessed features defined by sidewall spacers in the device regions and depositing a second high-k film in the recessed features. Some embodiments include forming an oxygen scavenging layer on the first high-k film, where the heat-treating the first high-k film scavenges oxygen from an interface layer to eliminate or reduce the thickness of an interface layer.

Abstract: A semiconductor device includes conductive layers and interlayer insulating layers stacked alternately with each other, at least one first channel layer passing through the conductive layers and the interlayer insulating layers, at least one second channel layer coupled to the first channel layers and passing through the conductive layers and the interlayer insulating layers, a first insulating layer interposed between the at least one first channel layer and the conductive layers, and a second insulating layer interposed between the at least one second channel layer and the conductive layers and having a higher nitrogen concentration than the first insulating layer.

Abstract: A fabricating method of a semiconductor device includes stacking a high-k dielectric film not containing silicon (Si) and an insulating film containing silicon (Si) on a substrate, and diffusing Si contained in the insulating film into the high-k dielectric film by annealing the substrate having the high-k dielectric film and the insulating film stacked thereon.

Abstract: A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

Abstract: A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure.

Abstract: A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al2O3, HfO2, ZrO2, TiO2, and MgO, the material is stoichiometric composition, and the charge trapping film includes material different from the material of the metal oxide.

Abstract: A method includes forming an interlayer on a substrate, depositing a dielectric on the interlayer to form a dielectric stack, forming a sacrificial cap layer over the dielectric stack, processing the substrate to alter properties of the dielectric stack, and removing the sacrificial cap layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.

Abstract: The description relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a fin having a first height above a first surface of a substrate, where a portion of the fin has first tapered sidewalls, and the fin has a top surface. The FinFET further includes an insulation region over a portion of the first surface of the substrate, where a top of the insulation region defines a second surface. The FinFET further includes a gate dielectric over the first tapered sidewalls and the top surface. The FinFET further includes a conductive gate strip over the gate dielectric, where the conductive gate strip has second tapered sidewalls along a longitudinal direction perpendicular to the first height, and a first width between the second tapered sidewalls in the longitudinal direction is greater at a location nearest to the substrate than a second width at a location farthest from the substrate.

Abstract: Methods of forming semiconductor devices are provided. The methods may include forming a gate pattern on an active region of a substrate. The methods may further include performing a deoxidization treatment on the substrate.

Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Abstract: Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.

Abstract: The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.

Abstract: A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric.

Abstract: According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.

Abstract: A method for fabricating a metal gate includes the following steps. First, a substrate having an interfacial dielectric layer above the substrate is provided. Then, a gate trench having a barrier layer is formed in the interfacial dielectric layer. A source layer is disposed above the barrier layer. Next, a process is performed to have at least one element in the source layer move into the barrier layer. Finally, the source layer is removed and a metal layer fills up the gate trench.

Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.

Abstract: A method of manufacturing a non-volatile memory is provided. A substrate includes a memory cell region and a first periphery circuit region. The memory cell region includes a select transistor region. A first gate dielectric layer having a first thickness is formed on the substrate in the first periphery circuit region and the select transistor region. A portion of the first gate dielectric layer on the select transistor region is removed to form a second gate dielectric layer. The second dielectric layer has a second thickness, wherein the second thickness is less than the first thickness.

Abstract: According to an embodiment, a non-volatile memory device includes a memory cell including a semiconductor layer, a charge storage layer provided on the semiconductor layer, and a first insulating film provided between the semiconductor layer and the charge storage layer. The device also includes a first conductive layer provided on the charge storage layer, a second conductive layer provided between the charge storage layer and the first conductive layer, a second insulating film provided between the charge storage layer and the second conductive layer, and a third insulating film provided between the first conductive layer and the second conductive layer.

Abstract: An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer later of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.