Having Sidewall Structure Patents (Class 438/595)
  • Patent number: 11145510
    Abstract: A semiconductor device includes a substrate, a FinFET, and an insulating structure. The FinFET includes a fin, a gate electrode, and a gate dielectric layer. The fin is over the substrate. The gate electrode is over the fin. The gate dielectric layer is between the gate electrode and the fin. The insulating structure is over the substrate, adjacent the fin, and has a top surface lower than a top surface of the fin. The top surface of the insulating structure has opposite first and second edge portions and an intermediate portion between the first and second edge portions. The first edge portion of the top surface of the insulating structure is lower than the intermediate portion of the top surface of the insulating structure.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 11121238
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Shiung Wu, Guan-Jie Shen
  • Patent number: 11088266
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Shiung Wu, Guan-Jie Shen
  • Patent number: 11075125
    Abstract: A device includes a semiconductor fin, a first transistor, a second transistor and a dielectric structure. The first semiconductor fin extends from a substrate. The first transistor is formed on a first region of the semiconductor fin. The second transistor is formed on a second region of the semiconductor fin laterally spaced apart from the first region of the semiconductor fin. The dielectric structure has a lower portion extending in the semiconductor fin and between the first transistor and the second transistor. The lower portion of the dielectric structure has a width increasing from a bottommost position of the dielectric structure to a first position higher than the bottommost position of the dielectric structure and decreasing from the first position to a second position higher than the first position.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-Iuan Lin
  • Patent number: 11075082
    Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Hung Hsieh
  • Patent number: 11062946
    Abstract: A method for forming one or more self-aligned contacts on a semiconductor device includes applying a protective layer on an oxide surface above a source and drain of the semiconductor device. The protective layer covers a top surface of the oxide surface selective to nitride above a gate contact pillar. A sacrificial layer is applied to the nitride surface. The sacrificial layer is deposited only on the nitride surface that is selective to the oxide layer coated with the protective layer. The protective layer is removed from the oxide surface and source/drain contact holes are etched in the oxide surface to form self-aligned contacts on the semiconductor device.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashim Dutta, Jennifer Church, Ekmini A. de Silva, Luciana M. Thompson
  • Patent number: 11018152
    Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: May 25, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tatsuya Hinoue, Kengo Kajiwara, Ryousuke Itou, Naohiro Hosoda
  • Patent number: 10957775
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
  • Patent number: 10937659
    Abstract: Embodiments provide anisotropic etch processes for silicon carbon nitride (SiCN) or other materials within multi-color structures with improved selectivity to materials in adjacent lines. Cyclic surface modification and activation processes are used to achieve an anisotropic etch with desired selectivity with respect to other materials in a multi-color structure. For example embodiments, selectivity of a first material, such as SiCN or silicon nitride, with respect to other materials in adjacent lines for the multi-color structure is achieved using the cyclic modification/activation processes. The materials within the multi-color structure can include, for example, silicon, silicon nitride, silicon carbon oxide, silicon oxide, titanium nitride, and/or other materials. For one embodiment, hydrogen is introduced to process chemistry to facilitate the surface modification. For one embodiment, a non-corrosive gas, such as nitrogen trifluoride, is included in the process chemistry with the hydrogen.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shihsheng Chang, Andrew Metz
  • Patent number: 10892193
    Abstract: Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Veeraraghavan S. Baskar, Jay W. Strane, Ekmini Anuja De Silva
  • Patent number: 10867807
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Patent number: 10840145
    Abstract: Device structures and methods are provided for fabricating vertical field-effect transistor devices with non-uniform thickness bottom spacers to achieve increased device performance. For example, a semiconductor substrate surface is etched to form semiconductor fins having bottom portions with concave sidewall surfaces that undercut upper portions of the fins. A doped epitaxial source/drain layer is formed on the concave sidewall surfaces, wherein portions of the doped epitaxial source/drain layer disposed between the fins have a raised curved surface. A bottom spacer layer is formed on the doped epitaxial source/drain layer, wherein portions of the bottom spacer layer disposed between the fins have a curved-shaped profile with a non-uniform thickness.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, ChoongHyun Lee, Shogo Mochizuki
  • Patent number: 10832965
    Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yiheng Xu, Haiting Wang, Qun Gao, Scott Beasor, Kyung Bum Koo, Ankur Arya
  • Patent number: 10819060
    Abstract: A stacked connector includes a first housing (10A) and a second housing (10B) to be stacked one on the other. The first and second housings (10A, 10B) respectively include first detecting portions (17A) and second detecting portions (17B) configured to interfere with incompletely inserted second terminal fittings (60B) and first terminal fittings (60A) on a first facing surface (11A) and a second facing surface (11B). The first housing (10A) is recessed with groove portions (35) formed in an outer side surface opposite to the first facing surface (11A) by cutting a region along a width direction, extending in a depth direction, and open on both ends in the depth direction.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 27, 2020
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Keiichi Tsukiyoshi, Yuto Harada
  • Patent number: 10811321
    Abstract: A semiconductor device includes a substrate having a semiconductor fin, an isolation feature over the substrate and not overlapping the semiconductor fin, a first gate structure over the substrate, and a second gate structure over the substrate. The isolation feature is closer to the first gate structure than the second gate structure. The first gate structure has a maximum width greater than a maximum width of the second gate structure.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon-Jhy Liaw
  • Patent number: 10679894
    Abstract: Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 9, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Chanro Park, Kangguo Cheng
  • Patent number: 10665513
    Abstract: A method includes removing a first portion of a dummy gate structure over a first fin while keeping a second portion of the dummy gate structure over a second fin, where removing the first portion forms a first recess exposing the first fin, forming a first gate dielectric material in the first recess and over the first fin, and removing the second portion of the dummy gate structure over the second fin, where removing the second portion forms a second recess exposing the second fin. The method further includes forming a second gate dielectric material in the second recess and over the second fin, the second gate dielectric material contacting the first gate dielectric material, and filling the first recess and the second recess with a conductive material.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Ching Chang, Bao-Ru Young, Yu Chao Lin
  • Patent number: 10483399
    Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-yup Chung, Myung-yoon Um, Dong-ho Cha, Jung-gun You, Gi-gwan Park
  • Patent number: 10411708
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for arranging configurable logic circuits such that the configurable logic circuit may be configured to form one or more of several logic circuits by coupling a combination of nodes included in the logic circuit. Configuring the configurable logic circuit may include modification of a single wiring layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Ken Ota
  • Patent number: 10312148
    Abstract: A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu, Chen Zhang
  • Patent number: 10236220
    Abstract: A method includes removing a first portion of a dummy gate structure over a first fin while keeping a second portion of the dummy gate structure over a second fin, where removing the first portion forms a first recess exposing the first fin, forming a first gate dielectric material in the first recess and over the first fin, and removing the second portion of the dummy gate structure over the second fin, where removing the second portion forms a second recess exposing the second fin. The method further includes forming a second gate dielectric material in the second recess and over the second fin, the second gate dielectric material contacting the first gate dielectric material, and filling the first recess and the second recess with a conductive material.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Ching Chang, Bao-Ru Young, Yu Chao Lin
  • Patent number: 10229926
    Abstract: A method for manufacturing a flash memory device includes providing a substrate structure including a substrate, an insulating layer on the substrate, and a stack structure including a charge storage layer, a tunneling dielectric layer, a charge trapping layer, a blocking dielectric layer and a gate layer disposed sequentially from bottom to top on the insulating layer. The method also includes performing a selective nitriding process on the substrate structure to form a nitride layer exposed surfaces of the charge storage layer and the gate layer, and forming an isolation region on side surfaces of the stack structure. The method can mitigate the problem of an undesirable increase in the threshold voltage with an increase in the integration density of the flash memory device.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 12, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Guobin Yu, Xiaoping Xu
  • Patent number: 10177144
    Abstract: A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction. The at least one second gate structure has a convex upper surface extending in the first direction and a second width in the second direction, the second width being greater than the first width.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-youn Kim, Sang-jung Kang, Ji-hwan An
  • Patent number: 10153277
    Abstract: An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-suk Tak, Tae-jong Lee, Gi-gwan Park, Ji-myoung Lee
  • Patent number: 10141263
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Patent number: 10079143
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 18, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsu Ting, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 9922880
    Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Choh Fei Yeap
  • Patent number: 9911694
    Abstract: Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Jasmeet S. Chawla
  • Patent number: 9880470
    Abstract: A composition for forming a coating type silicon-containing film, containing one or more silicic acid skeletal structures represented by the formula (1) and one or more silicon skeletal structures represented by the formula (2), wherein the composition contains a coupling between units shown in the formula (2). There can be provided a composition capable of forming a silicon-containing film that has excellent adhesiveness in fine patterning, and can be easily wet etched by a removing liquid which does not cause damage to a semiconductor substrate and a coating type organic film or a CVD film mainly of carbon which is required in the patterning process.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 30, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Seiichiro Tachibana, Yoshinori Taneda, Rie Kikuchi, Tsutomu Ogihara
  • Patent number: 9799750
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Fai Cheng, Han-Ting Tsai, An-Shen Chang, Hui-Min Lin
  • Patent number: 9660047
    Abstract: A method for producing a semiconductor component includes providing a semiconductor body having a first semiconductor material extending to a first surface and at least one trench, the at least one trench extending from the first surface into the semiconductor body, a first insulation layer being arranged in the at least one trench. The method further includes forming a second insulation layer on the first surface having a recess that overlaps in a projection onto the first surface with the at least one trench, forming a mask region in the recess, etching the second insulation layer selectively to the mask region, depositing a third insulation layer over the first surface, and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the at least one trench is exposed at the first surface.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl
  • Patent number: 9627277
    Abstract: A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 9607904
    Abstract: ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 28, 2017
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, INC.
    Inventors: Albert Sanghyup Lee, Paul Besser, Kisik Choi, Edward L Haywood, Hoon Kim, Salil Mujumdar
  • Patent number: 9553147
    Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 24, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ying Zhang, Hua Chung
  • Patent number: 9524968
    Abstract: A fabrication method of semiconductor device having metal gate includes providing a substrate, successively forming a gate insulating layer and a bottom barrier layer on the surface of the substrate, forming a work function layer covering the bottom barrier layer, removing the work function layer, and forming a top barrier layer on the bottom barrier layer to be directly contact with the bottom barrier layer, and forming a metal layer on the top bottom barrier layer.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Ya-Huei Tsai
  • Patent number: 9514948
    Abstract: A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Paul C. Jamison
  • Patent number: 9496372
    Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming first and second gate stacks over first and second portions of a fin feature respectively; filling a space between the first and second gate stacks with a dielectric layer; removing the first and second gate stacks to form first and second trenches respectively; and removing the first portion of the fin feature through the first trench while keeping the second portion of the fin feature in the second trench. The method further includes, after the removing of the first portion, depositing a gate dielectric layer and a gate electrode layer in the first and second trenches.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: November 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Han Lin, Chao-Cheng Chen, Jr-Jung Lin, Ming-Ching Chang
  • Patent number: 9437705
    Abstract: A method of manufacturing a spacer for an electronic memory including a substrate; a first gate structure; a stack including a plurality of layers whereof at least one of the layers is able to store electric charges, the method including depositing a spacer material layer, at least on the area covered by the stack; ion beam machining the spacer material layer, the ion beam machining being carried out with controlled stopping so as to preserve a residual portion of the thickness of the spacer material layer covering the stack; plasma etching the residual portion of the thickness of the spacer material layer.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: September 6, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Anthony De Luca, Christelle Charpin-Nicolle
  • Patent number: 9385120
    Abstract: A method of fabricating a semiconductor device is provided. A sacrificial gate, a hard mask, a spacer and a first interlayer insulating film are formed on a substrate. The hard mask, a part of the spacer, and a part of the first interlayer insulating film are removed to expose an upper portion of the sacrificial gate. A sacrificial insulating layer covers the exposed upper portion of the sacrificial gate. A second interlayer insulating film covers the sacrificial insulating layer, the spacer and the first interlayer insulating film. The sacrificial insulating layer and the second interlayer insulating film are partially removed to expose a top surface of the sacrificial gate. The sacrificial gate and the sacrificial insulating layer are removed to form a trench. A gate structure is formed in the trench.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: July 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun-Jun Bae
  • Patent number: 9378975
    Abstract: Methods herein can be used for removing silicon nitride around fins and other structures without damaging underlying silicon structures. Methods herein also include forming dual layer spacers and L-shaped spacers, as well as other configurations. Techniques include a multi-step process of anisotropic etching of low-k material with high selectivity to silicon nitride, followed by isotropic etching of SiN with high selectivity to the low-k material. Such techniques, for example, can be used to form an L-shaped spacer on a 3-D gate structure, as well as providing a method for completely removing silicon nitride without damaging surrounding or underlying materials.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: June 28, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Blake Parkinson, Alok Ranjan
  • Patent number: 9263465
    Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
  • Patent number: 9263466
    Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
  • Patent number: 9245883
    Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a first gate stack and a second gate stack over different portions of a fin feature formed on a substrate, forming a first dielectric layer in a space between the first and second gat stacks, removing the first gate stack to form a first gate trench, therefore the first gate trench exposes a portion of the fin feature. The method also includes removing the exposed portion of the fin feature and forming an isolation feature in the first gate trench.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Jr-Jung Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 9147653
    Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Jongwook Kye, Harry Levinson
  • Patent number: 9117910
    Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 25, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heedon Jeong, Jae Yup Chung, Heesoo Kang, Donghyun Kim, Sanghyuk Hong, Soohun Hong
  • Patent number: 9099492
    Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: August 4, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kuldeep Amarnath, Michael Hargrove, Srikanth Samavedam
  • Patent number: 9093513
    Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
  • Patent number: 9087921
    Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
  • Patent number: 9059253
    Abstract: Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan, Thomas N. Adam
  • Patent number: 9059235
    Abstract: In one embodiment, a semiconductor device includes a substrate including a trench, and a gate electrode disposed at a position adjacent to the trench on the substrate, the gate electrode having a first side surface located on an opposite side of the trench, and a second side surface located on the same side as the trench. The device further includes a first sidewall insulator disposed on the first side surface, and a second sidewall insulator disposed on the second side surface and a side surface of the trench. The device further includes a source region of a first conductivity type disposed in the substrate on the same side as the first sidewall insulator with respect to the first side surface, and a drain region of a second conductivity type disposed in the substrate on the same side as the second sidewall insulator with respect to the second side surface.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 16, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiyuki Kondo, Shigeru Kawanaka