Portion Of Sidewall Structure Is Conductive Patents (Class 438/596)
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Patent number: 11948978Abstract: Field-effect transistors (FETs) employing edge transistor current leakage suppression to reduce FET current leakage, and related methods, are disclosed. The FET includes a gate that includes extended-length edge gate regions overlapping semiconductor layer edges to form extended length edge conduction channels in edge transistors. In this manner, the threshold voltage of the edges transistors is increased, thus reducing current leakage of the edges transistors and overall current leakage of the FET. In another aspect, a body connection implant that is formed to short a source or drain region to a body of the FET is extended in length to form body connection implant regions underneath at least a portion of the edge gate regions. In this manner, the work functions of the edge gate regions are increased in voltage thus increasing the threshold voltage of the edge transistors and reducing current leakage of the edges transistors and the FET.Type: GrantFiled: April 24, 2020Date of Patent: April 2, 2024Assignee: QUALCOMM INCORPORATEDInventors: Abhijeet Paul, Mishel Matloubian
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Patent number: 11942477Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.Type: GrantFiled: March 6, 2023Date of Patent: March 26, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sun Ki Min
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Patent number: 11784260Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.Type: GrantFiled: July 12, 2022Date of Patent: October 10, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
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Patent number: 11735662Abstract: A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.Type: GrantFiled: June 28, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Sheng Liang, Shih-Hsun Chang
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Patent number: 11563028Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.Type: GrantFiled: September 28, 2020Date of Patent: January 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kohji Kanamori, Seo-Goo Kang, Hyo Joon Ryu, Sang Youn Jo, Jee Hoon Han
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Patent number: 10923599Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.Type: GrantFiled: May 9, 2019Date of Patent: February 16, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Purakh Raj Verma, Ching-Yang Wen, Li Wang, Kai Cheng
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Patent number: 9171951Abstract: According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, a first gate insulator film provided on the channel region, a second gate insulator film provided on the channel region to be adjacent to the first gate insulator film on the source region side of the first gate insulator film, a first gate electrode provided on the first gate insulator film, and a second gate electrode provided on the second gate insulator film. An electrical thickness of the second gate insulator film is less than an electrical thickness of the first gate insulator film. A portion of the first gate electrode is provided on the second gate insulator film. A work function of the second gate electrode is higher than a work function of the first gate electrode.Type: GrantFiled: July 16, 2014Date of Patent: October 27, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Toshitaka Miyata
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Patent number: 9147608Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: September 15, 2014Date of Patent: September 29, 2015Assignee: MICRON TECHNOLOGY, INC.Inventors: Luan C. Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
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Patent number: 9040375Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.Type: GrantFiled: January 28, 2013Date of Patent: May 26, 2015Assignee: INFINEON TECHNOLOGIES DRESDEN GMBHInventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
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Publication number: 20150140800Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.Type: ApplicationFiled: November 18, 2013Publication date: May 21, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei Cheng, Ming Sheng Xu, Duan Quan Liao, Yikun Chen, CHING HWA TEY
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Patent number: 9024427Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.Type: GrantFiled: February 11, 2014Date of Patent: May 5, 2015Assignee: Freescale Semiconductor. IncInventors: Huan Wang, Aipeng Shu, Shu An Yao
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Patent number: 9023726Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.Type: GrantFiled: November 18, 2013Date of Patent: May 5, 2015Assignee: United Microelectronics Corp.Inventors: Wei Cheng, Ming Sheng Xu, Duan Quan Liao, Yikun Chen, Ching Hwa Tey
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Patent number: 9018629Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.Type: GrantFiled: October 5, 2012Date of Patent: April 28, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sachiaki Tezuka, Atsuo Isobe, Takehisa Hatano, Kazuya Hanaoka
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Patent number: 9006073Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.Type: GrantFiled: May 2, 2014Date of Patent: April 14, 2015Assignee: SK Hynix Inc.Inventors: Su Jin Chae, Jin Hyock Kim, Young Seok Kwon
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Patent number: 8980736Abstract: A method of manufacturing a semiconductor device may include: forming active patterns of pillar-shapes upward protruding from a substrate, the active patterns fully doped with dopants of one conductivity type; forming a gate electrode extending in one direction, the gate electrode overlapped with sidewalls of the active patterns; and forming a gate insulating layer between the gate electrode and the active patterns.Type: GrantFiled: February 25, 2014Date of Patent: March 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Jong Un Kim
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Patent number: 8969153Abstract: A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.Type: GrantFiled: July 1, 2013Date of Patent: March 3, 2015Assignee: SanDisk Technologies Inc.Inventors: Donovan Lee, Vinod Purayath, James Kai, George Matamis
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Patent number: 8956929Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.Type: GrantFiled: November 15, 2012Date of Patent: February 17, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
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Patent number: 8946037Abstract: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.Type: GrantFiled: August 1, 2013Date of Patent: February 3, 2015Assignee: Infineon Technologies AGInventors: Ronald Kakoschke, Helmut Tews
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Patent number: 8907464Abstract: A three dimensional (3D) package includes a helix substrate having a columnar part including a top surface, a bottom surface and a sidewall, and a plurality of steps arranged along the sidewall of the columnar part in the form of a helix. Semiconductor integrated circuits (dies) may be attached on supporting surfaces of the steps. The columnar part, the steps and the dies can be covered with a mold compound. I/Os are formed at either the sides of the steps and/or the top and/or bottom of the columnar part.Type: GrantFiled: March 22, 2013Date of Patent: December 9, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Huan Wang, Meiquan Huang, Hejin Liu
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Patent number: 8859363Abstract: Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.Type: GrantFiled: November 8, 2011Date of Patent: October 14, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Daeik Kim, HyeongSun Hong, Yongchul Oh, Yoosang Hwang
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Patent number: 8860140Abstract: The present disclosure provides a TFET, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; a gate stack formed on the channel region, wherein the gate stack comprises: a gate dielectric layer, and at least a first gate electrode and a second gate electrode distributed in a direction from the source region to the drain region and formed on the gate dielectric layer, and the first gate electrode and the second gate electrode have different work functions; and a first side wall and a second side wall formed on a side of the first gate electrode and on a side of the second gate electrode respectively.Type: GrantFiled: June 24, 2011Date of Patent: October 14, 2014Assignee: Tsinghua UniversityInventors: Renrong Liang, Ning Cui, Jing Wang, Jun Xu
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Patent number: 8859362Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: August 8, 2013Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
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Patent number: 8846471Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.Type: GrantFiled: August 12, 2013Date of Patent: September 30, 2014Assignee: Renesas Electronics CorporationInventor: Tatsuyoshi Mihara
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Patent number: 8835295Abstract: A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer.Type: GrantFiled: August 7, 2013Date of Patent: September 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jinmiao J. Shen, Ko-Min Chang, Brian A. Winstead
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Patent number: 8836128Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric is deposited onto the semiconductor dice and trenches are formed therein. A conductive film is deposited onto the first dielectric and the trench surfaces. All planar conductive film is removed from the faces of the semiconductor dice and bottoms of the trenches, leaving only conductive films on the trench walls, whereby “fence conductors” are created therefrom. Thereafter the gap between the conductive films on the trench walls are filled in with insulating material. A top portion of the insulated gap fill is thereafter removed to expose the tops of the fence conductors. Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.Type: GrantFiled: March 15, 2013Date of Patent: September 16, 2014Assignee: Microchip Technology IncorporatedInventor: Paul Fest
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Patent number: 8765558Abstract: A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.Type: GrantFiled: March 22, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Haining S. Yang
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Patent number: 8716095Abstract: A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.Type: GrantFiled: September 19, 2010Date of Patent: May 6, 2014Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huicai Zhong, Zhijiong Luo, Qingqing Liang
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Patent number: 8716079Abstract: In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape on the basis of a material erosion process, wherein a sacrificial material may protect sensitive materials, such as a high-k dielectric material, in the gate opening. In one illustrative embodiment, the sacrificial material may be applied after depositing a work function adjusting species in the gate opening.Type: GrantFiled: September 27, 2010Date of Patent: May 6, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Jens Heinrich, Fernando Koch, Johann Steinmetz
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Patent number: 8623751Abstract: A through-hole electrode substrate related to an embodiment of the present invention is arranged with a semiconductor substrate having a plurality of through-holes, an insulating layer formed with an insulating material on the inner walls of the plurality of through-holes and on at least one surface of the semiconductor substrate, a plurality of through-hole electrodes formed with a metal material inside the through-hole, and a plurality of gas discharge parts formed to contact with each of the plurality of through-hole electrodes which is exposed on at least one surface of the semiconductor substrate, the plurality of gas discharge parts externally discharges gas which is discharged from the inside of the plurality of through-hole electrodes.Type: GrantFiled: May 8, 2012Date of Patent: January 7, 2014Assignee: Dai Nippon Printing Co., Ltd.Inventors: Koichi Nakayama, Yoichi Hitomi, Takamasa Takano
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Patent number: 8575013Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.Type: GrantFiled: October 25, 2011Date of Patent: November 5, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Peter Baars, Matthias Goldbach
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Patent number: 8551823Abstract: This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.Type: GrantFiled: April 29, 2009Date of Patent: October 8, 2013Assignee: Micron Technology, Inc.Inventor: Fernando Gonzalez
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Patent number: 8525232Abstract: A semiconductor structure which includes a semiconductor substrate and a metal gate structure formed in a trench or via on the semiconductor substrate. The metal gate structure includes a gate dielectric; a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; and an aluminum layer to fill the remainder of the trench or via. There is also disclosed a method of forming a semiconductor structure in which a wetting layer is formed from cobalt amidinate or nickel amidinate deposited by a chemical vapor deposition process.Type: GrantFiled: August 10, 2011Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Takeshi Nogami, Keith K. H. Wong, Chih-Chao Yang
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Patent number: 8502325Abstract: A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.Type: GrantFiled: March 28, 2012Date of Patent: August 6, 2013Assignee: International Business Machines CorporationInventors: Leland Chang, Jeffrey W. Sleight, Isaac Lauer, Renee T. Mo
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Patent number: 8501611Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.Type: GrantFiled: July 17, 2012Date of Patent: August 6, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Do Ryu, Si-Young Choi, Yu-Gyun Shin, Tai-Su Park, Dong-Chan Kim, Jong-Ryeol Yoo, Seong-Hoon Jeong, Jong-Hoon Kang
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Patent number: 8481389Abstract: A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.Type: GrantFiled: April 5, 2011Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventors: Ying Zhang, Qingyun Yang, Hongwen Yan
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Patent number: 8470670Abstract: One or more embodiments may relate to a method for making a semiconductor device, including: a method for making a semiconductor device, comprising: providing a substrate; forming a charge storage layer over the substrate; forming a control gate layer over the charge storage layer; forming a mask over the control gate layer; using the mask, etching the control gate layer and the charge storage layer; forming a select gate layer over the etched control gate layer and the etched charge storage layer; forming an additional layer over the select gate layer; etching the additional layer to form sidewall spacers over the select gate layer; and etching the select gate layer.Type: GrantFiled: September 23, 2009Date of Patent: June 25, 2013Assignee: Infineon Technologies AGInventors: John Power, Danny Pak-Chum Shum, Wolfgang Dickenscheid, Robert Strenz
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Patent number: 8450199Abstract: Different types of transistors, such as memory cells, higher voltage, and higher performance transistors, may be formed on the same substrate. A transistor may be formed with a first polysilicon layer covered by a dielectric. A second polysilicon layer over the dielectric may be etched to form a sidewall spacer on the gate of the transistor. The sidewall spacer may be used to form sources and drains and to define sub-lithographic lightly doped drains. After removing the spacer, the underlying dielectric may protect the lightly doped drains.Type: GrantFiled: December 22, 2008Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Fausto Piazza, Alfonso Maurelli
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Patent number: 8440557Abstract: The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation absorbing film of a silicon-rich film under an etching condition using an oxygen gas flow rate corresponding to the extinction coefficient.Type: GrantFiled: July 20, 2010Date of Patent: May 14, 2013Assignee: Spansion LLCInventors: Seiji Yokoyama, Yuuichirou Sekimoto, Sinichi Imada
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Patent number: 8440528Abstract: A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole.Type: GrantFiled: December 15, 2009Date of Patent: May 14, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Masaru Kidoh, Tomoko Fujiwara, Yosuke Komori, Megumi Ishiduki, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Ryota Katsumata, Ryouhei Kirisawa, Junya Matsunami, Hideaki Aochi
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Patent number: 8435878Abstract: A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.Type: GrantFiled: April 6, 2010Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Yanfeng Wang
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Patent number: 8431817Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may be a multi junction solar cell. The optoelectronic device may have a bi-layer electrical interconnect that is physically and electrically connected to sidewalls of the array of nanostructures. The optoelectronic device may be operated as a multi junction solar cell, wherein each junction is associated with one portion of the device. The bi-layer electrical interconnect allows current to pass from one portion to the next. Thus, the bi-layer electrical interconnect may serve as a replacement for a tunnel junction, which is used in some conventional multi junction solar cells.Type: GrantFiled: June 8, 2010Date of Patent: April 30, 2013Assignee: Sundiode Inc.Inventors: James C. Kim, Sungsoo Yi, Danny E. Mars
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Patent number: 8415742Abstract: Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.Type: GrantFiled: April 9, 2012Date of Patent: April 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jingyun Kim, Myoungbum Lee, Kihyun Hwang
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Publication number: 20130049125Abstract: A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.Type: ApplicationFiled: August 29, 2011Publication date: February 28, 2013Inventors: Huicai Zhong, Jun Luo, Qingqing Liang, Huilong Zhu
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Patent number: 8372699Abstract: A method for forming a semiconductor device includes forming a first semiconductor layer over a substrate, forming a first photoresist layer over the first semiconductor layer, and using only a first single mask patterning the first photoresist layer to form a first patterned photoresist layer. The method further includes using the first patterned photoresist layer etching the first semiconductor layer to form a select gate and forming a charge storage layer over the select gate and a portion of the substrate. The method further includes forming a second semiconductor layer over the charge storage layer, forming a second photoresist layer over the second semiconductor layer, and using only a second single mask patterning the second photoresist layer to form a second patterned photoresist layer. The method further includes forming a control gate by anisotropically etching the second semiconductor layer and then subsequently isotropically etching the second semiconductor layer.Type: GrantFiled: February 22, 2010Date of Patent: February 12, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Sung-Taeg Kang, Jane A. Yater
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Patent number: 8350344Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.Type: GrantFiled: March 10, 2011Date of Patent: January 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Min Son, Woon-Kyung Lee
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Patent number: 8334181Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.Type: GrantFiled: July 14, 2010Date of Patent: December 18, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
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Patent number: 8324092Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.Type: GrantFiled: January 5, 2010Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Kan Yasui, Digh Hisamoto, Tetsuya Ishimaru, Shin-Ichiro Kimura
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Patent number: 8310008Abstract: An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.Type: GrantFiled: July 27, 2010Date of Patent: November 13, 2012Assignee: Spansion LLCInventor: Burchell B. Baptiste
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Patent number: 8293600Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer including a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element including memory material is on and in contact with the second electrode layer.Type: GrantFiled: December 6, 2011Date of Patent: October 23, 2012Assignee: Macronix International Co., Ltd.Inventor: Shih-Hung Chen
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Patent number: 8273648Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.Type: GrantFiled: February 9, 2012Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon Ju Kim, James R. Moulic