Interconnecting Plural Devices On Semiconductor Substrate Patents (Class 438/6)
  • Patent number: 10640369
    Abstract: One example provides a microelectromechanical systems (MEMS) device that includes a number of silicon die over-molded with an overmold material, a number of active areas formed on the silicon die, the active areas including at least one sensor to sense a number of attributes of a fluid introduced to the at least one sensor, and a fan-out layer coupled to the silicon die, the fan-out layer including a number of fluid channels formed therein that interface with active areas of the silicon die and allow the fluid to flow to the at least one sensor.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: May 5, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Devin Alexander Mourey, Michael W. Cumbie, Si-lam J. Choy
  • Patent number: 10615161
    Abstract: A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type III-V semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Jeehwan Kim
  • Patent number: 10134695
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Doo Hwan Lee, Ju Hyeon Kim, Hyoung Joon Kim, Joon Sung Kim
  • Patent number: 9922968
    Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of side-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 20, 2018
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 9856137
    Abstract: The present disclosure includes bonded wafer structures and methods of forming bonded wafer structures. One example of a forming a bonded wafer structure includes providing a first wafer (202, 302) and a second wafer (204, 304) to be bonded together via a bonding process that has a predetermined wafer gap (216, 316) associated therewith, and forming a mesa (215, 315, 415) on the first wafer (202, 302) prior to bonding the first wafer (202, 302) and the second wafer (204, 304) together, wherein a height (220, 320, 420) of the mesa (215, 315, 415) is determined based on a target element gap (217, 317) associated with the bonded wafer structure.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: January 2, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Rodney L. Alley, Donald J. Milligan
  • Patent number: 9378940
    Abstract: The present disclosure provides a substrate processing apparatus including: a substrate processing chamber configured to process a substrate on which a target layer to be removed is formed on the surface of an underlying layer; a substrate holding unit provided in the substrate processing chamber and configured to hold the substrate; a mixed liquid supplying unit configured to supply a mixed liquid of sulfuric acid and hydrogen peroxide to the substrate held by the substrate holding unit in a mixing ratio of the hydrogen peroxide and a temperature that does not damage the underlying layer while removing the target layer; and an OH-group supplying unit configured to supply a fluid containing OH-group to the substrate in an amount that does not damage the underlying layer when the mixed liquid and the OH-group are mixed on the substrate.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: June 28, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Hisashi Kawano, Norihiro Ito, Yosuke Hachiya, Jun Nogami, Kotaro Ooishi, Itaru Kanno
  • Patent number: 9275992
    Abstract: Trenches may be formed in layers on a semiconductor substrate for defining electrical components for an electronic device, such as an amplifier. A polishing step may be performed after formation of the trenches and deposition of other layer(s) to define regions for resistors, capacitors, or other elements in a metal layer on a semiconductor substrate. The polishing step may create discontinuities in metal layers on the semiconductor substrate that define electrically isolated regions corresponding to the resistors, capacitor, and other components of the electronic device.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 1, 2016
    Assignee: CIRRUS LOGIC, INC.
    Inventors: Marc L. Tarabbia, Shanjen Pan
  • Patent number: 9181091
    Abstract: Provided are a porous nanostructure and a method of manufacturing the same. The porous nanostructure includes a plurality of pores disposed on an exterior surface of a nanostructure, wherein at least a portion of the plurality of pores extend inside the nanostructure.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-kyung Lee, Dong-mok Whang, Byoung-lyong Choi, Sun-hwak Woo
  • Patent number: 9162880
    Abstract: Systems and methods for transferring a micro device from a carrier substrate are disclosed. In an embodiment, a mass transfer tool includes an articulating transfer head assembly, a carrier substrate holder, and an actuator assembly to adjust a spatial relationship between the articulating transfer head assembly and the carrier substrate holder. The articulating transfer head assembly may include an electrostatic voltage source connection and a substrate supporting an array of electrostatic transfer heads.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: October 20, 2015
    Assignee: LuxVue Technology Corporation
    Inventors: John A. Higginson, Andreas Bibl, David Albertalli
  • Patent number: 9153578
    Abstract: A trimming circuit is configured to carry out a trimming operation on a device portion of an integrated circuit device. The trimming circuit includes: shunt fuses wherein each shunt fuse is coupled in parallel to a trimming resistance, further resistances wherein each further resistance is coupled in parallel to a respective shunt fuse. The circuit is configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 6, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Giuseppe Scilla
  • Patent number: 9130062
    Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: September 8, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenya Hironaga, Masatoshi Yasunaga, Tatsuya Hirai, Soshi Kuroda
  • Patent number: 9087174
    Abstract: Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware design rule check for an electronic design. Various embodiments identify one or more sets of multiple-exposure grids and identify or generate a data structure by using the one or more sets of grids to store design data of shape ends of various ends. Various embodiments perform constant time design rule checking by performing a constant time search process on the data structure to look up from the data structure one or more violations of one or more design rules which include at least one directional design rule. Some aspects are directed at fixing a design rule violation by using at least some grids of the one or more sets of grids.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 21, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shuo Zhang, Vassilios Gerousis
  • Patent number: 9041209
    Abstract: In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Douglas M. Reber, Lawrence N. Herr
  • Patent number: 9018022
    Abstract: A showerhead electrode assembly for use in a capacitively coupled plasma processing apparatus comprising a heat transfer plate. The heat transfer plate having independently controllable gas volumes which may be pressurized to locally control thermal conductance between a heater member and a cooling member such that uniform temperatures may be established on a plasma exposed surface of the showerhead electrode assembly.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: April 28, 2015
    Assignee: Lam Research Corporation
    Inventors: Sang Ki Nam, Rajinder Dhindsa, Ryan Bise
  • Publication number: 20150048424
    Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chun TIEN, Ya-Chi CHOU, Hui-Zhong ZHUANG, Chun-Fu CHEN, Ting-Wei CHIANG, Hsiang Jen TSENG
  • Patent number: 8945939
    Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Ecolab USA Inc.
    Inventors: Amy M. Tseng, Brian V. Jenkins, Robert Mack
  • Patent number: 8936959
    Abstract: An rf MEMS system has a semiconductor substrate, e.g., silicon. The system also has a control module provided overlying one or more first regions of the semiconductor substrate according to a specific embodiment. The system also has a base band module provided overlying one or more second regions of the semiconductor substrate and an rf module provided overlying one or more third regions of the semiconductor substrate. The system also has one or more MEMS devices integrally coupled to at least the rf module.
    Type: Grant
    Filed: February 26, 2011
    Date of Patent: January 20, 2015
    Assignee: mCube Inc.
    Inventor: Xiao (Charles) Yang
  • Patent number: 8932874
    Abstract: The invention is directed towards methods and compositions for identifying the amount of ammonium acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of ammonium acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of ammonium acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the ammonium acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 13, 2015
    Assignee: Nalco Company
    Inventors: Amy M. Tseng, Brian V. Jenkins, Robert M. Mack
  • Patent number: 8828803
    Abstract: A resin sealing method for a plurality of semiconductor chips. The resin sealing method includes a chip holding sheet attaching step of attaching a chip holding sheet through an adhesive ring to a support substrate, a semiconductor chip attaching step of attaching the front side of each semiconductor chip to an adhesive layer constituting the chip holding sheet in an area corresponding to the inside of the adhesive ring, a resin sealing step of sealing all of the semiconductor chips with a mold resin, a support substrate removing step of removing the support substrate from the chip holding sheet on which the semiconductor chips are attached and sealed with the mold resin, and a chip holding sheet peeling step of peeling the chip holding sheet from the front side of each semiconductor chip sealed with the mold resin.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 9, 2014
    Assignee: Disco Corporation
    Inventor: Karl Priewasser
  • Patent number: 8822993
    Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee
  • Patent number: 8741694
    Abstract: Embodiments of the present disclosure describe semiconductor device packaging techniques and devices that incorporate a heat spreader into the insulating material of a packaged semiconductor device. In one embodiment, a device comprising a semiconductor device is coupled to a substrate, and insulating material covers (i) a portion of the semiconductor device and (ii) a portion of the substrate. The device also comprises a heat spreader embedded in the insulating material and the heat spreader is isolated from the substrate at least in part by the insulating material.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: June 3, 2014
    Assignee: Marvell International Ltd.
    Inventors: Chender Chen, Chenglin Liu, Shiann-Ming Liou
  • Patent number: 8735218
    Abstract: A method of producing an electronic module with at least one electronic component and one carrier. A structure is provided on the carrier so that the electronic component can take a desired target position relative to the structure. The structure is coated with a liquid meniscus suitable for receiving the electronic component. Multiple electronic components are provided at a delivery point for the electronic components. The carrier, with the structure, is moved nearby and opposite to the delivery point, where the delivery point delivers one of the electronic components without contact, while the structure on the carrier is moving near the delivery point, so that after a phase of free movement the electronic component at least partly touches the material, and the carrier, with the structure, is moved to a downstream processing point, while the electronic component aligns itself to the structure on the liquid meniscus.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: May 27, 2014
    Assignee: Muehlbauer AG
    Inventors: Michael Max Mueller, Helfried Zabel, Hans-Peter Monser
  • Patent number: 8735180
    Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: May 27, 2014
    Assignee: Nikon Corporation
    Inventor: Kazuya Okamoto
  • Patent number: 8716028
    Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Nalco Company
    Inventors: Amy Tseng, Brian V. Jenkins, Robert M. Mack
  • Patent number: 8703507
    Abstract: A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: April 22, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Douglas M. Reber
  • Patent number: 8703506
    Abstract: A solar cell module manufacturing device is disclosed. The device includes a wire supply portion, a correction portion, and a cutting portion. The supply portion includes a bobbin and wiring material on the bobbin. The correction portion corrects curvature of the wiring material. The correction portion comprises a first pulley that comes in contact with the wiring material which is drawn from the bobbin. The first pulley comprises at a periphery thereof a first groove. The first groove comprises a first basal surface and a pair of first inclined surfaces which are arranged on both sides of the first basal surface. An inclination angle ?1 of the first inclined surface relative to the first basal surface being less than or equal to an inclination angle ?2 of the wiring material which is drawn from the supply portion relative to the first basal surface.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 22, 2014
    Assignee: KYOCERA Corporation
    Inventors: Takafumi Miyake, Koki Oda
  • Publication number: 20140073068
    Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 13, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Kenya HIRONAGA, Masatoshi YASUNAGA, Tatsuya HIRAI, Soshi KURODA
  • Patent number: 8633601
    Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: January 21, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Nitesh Kumbhat, Abhishek Choudhury, Venkatesh V. Sundaram, Rao R. Tummala
  • Patent number: 8633037
    Abstract: A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masayuki Furumiya, Yasutaka Nakashiba
  • Patent number: 8558332
    Abstract: A method of fabricating a spin-current switched magnetic memory element includes providing a wafer having a bottom electrode, forming a plurality of layers, such that interfaces between the plurality of layers are formed in situ, in which the plurality of layers includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers, lithographically defining a pillar structure from the plurality of layers, and forming a top electrode on the pillar structure.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jonathan Zanhong Sun, Rolf Allenspach, Stuart Stephen Papworth Parkin, John Casimir Slonczewski, Bruce David Terris
  • Patent number: 8551830
    Abstract: There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: October 8, 2013
    Assignees: Advantest Corporation, National University Corporation Tohoku University
    Inventors: Tadahiro Ohmi, Koji Kotani, Kazuyuki Maruo, Takahiro Yamaguchi
  • Patent number: 8492172
    Abstract: A compact sensor with which particles floating in the air can be easily detected. A sensor having a microstructure which detects a detection object by contact is used. A microstructure has an opening to be a detection hole corresponding to the size of a detection object, and a pair of electrodes having a bridge structure are provided thereabove or thereunder so as to partially contact with each other.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Konami Izumi, Fuminori Tateishi
  • Patent number: 8486761
    Abstract: A multi-chip light emitting device (LED) uses a low-cost carrier structure that facilitates the use of substrates that are optimized to support the devices that require a substrate. Depending upon the type of LED elements used, some of the LED elements may be mounted on the carrier structure, rather than on the more expensive ceramic substrate. In like manner, other devices, such as sensors and control elements, may be mounted on the carrier structure as well. Because the carrier and substrate structures are formed independent of the encapsulation and other after-formation processes, these structures can be tested prior to encapsulation, thereby avoiding the cost of these processes being applied to inoperative structures.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 16, 2013
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Serge J. Bierhuizen
  • Publication number: 20130164863
    Abstract: A solar cell module manufacturing device is disclosed. The device includes a wire supply portion, a correction portion, and a cutting portion. The supply portion includes a bobbin and wiring material on the bobbin. The correction portion corrects curvature of the wiring material. The correction portion comprises a first pulley that comes in contact with the wiring material which is drawn from the bobbin. The first pulley comprises at a periphery thereof a first groove. The first groove comprises a first basal surface and a pair of first inclined surfaces which are arranged on both sides of the first basal surface. An inclination angle ?1 of the first inclined surface relative to the first basal surface being less than or equal to an inclination angle ?2 of the wiring material which is drawn from the supply portion relative to the first basal surface.
    Type: Application
    Filed: August 30, 2011
    Publication date: June 27, 2013
    Applicant: KYOCERA CORPORATION
    Inventors: Takafumi Miyake, Koki Oda
  • Patent number: 8440472
    Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: May 14, 2013
    Assignee: Nikon Corporation
    Inventor: Kazuya Okamoto
  • Patent number: 8410594
    Abstract: An inter-stacking module system is provided by mounting an integrated circuit on a first substrate, the first substrate having a first bond pad, mounting an inter-stacking module substrate over the integrated circuit, forming an inter-stacking module bonding pad on the inter-stacking module substrate, and connecting bond wires between the inter-stacking module bonding pad and the first bond pad.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: April 2, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Kwang Soon Hwang, Youngcheol Kim, Hun Teak Lee, Koo Hong Lee
  • Patent number: 8394708
    Abstract: A method and system for assembling a quasicrystalline heterostructure. A plurality of particles is provided with desirable predetermined character. The particles are suspended in a medium, and holographic optical traps are used to position the particles in a way to achieve an arrangement which provides a desired property.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 12, 2013
    Assignees: New York University, The Trustees of Princeton University
    Inventors: David G. Grier, Yael Roichman, Weining Man, Paul Michael Chaikin, Paul Joseph Steinhardt
  • Patent number: 8355810
    Abstract: A method and system for estimating context offsets for run-to-run control in a semiconductor fabrication facility is described. In one embodiment, contexts associated with a process are identified. The process has one or more threads, and each thread involves one or more contexts. A set of input-output equations describing the process is defined. Each input-output equation corresponds to a thread and includes a thread offset expressed as a summation of individual context offsets. A state-space model is created that describes an evolution of the process using the set of input-output equations. The state-space model allows to estimate individual context offsets.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: January 15, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Jianping Zou
  • Patent number: 8333005
    Abstract: A method is disclosed for the fabrication of a tunable radio frequency (RF) power output filter that includes fabricating a core body and then forming a plastically deformable metallic shell over the exterior surface of the core body.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: December 18, 2012
    Inventors: James Thomas LaGrotta, Richard T. LaGrotta
  • Patent number: 8304271
    Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: November 6, 2012
    Inventors: Jenn Hwa Huang, Bruce M. Green
  • Patent number: 8304260
    Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device having a buffer circuit. In the method, a plurality of semiconductor elements is formed on a semiconductor substrate. The plurality of semiconductor elements are connected in parallel to each other in the buffer circuit. In the method, driving forces of the formed semiconductor elements is evaluated. In the method, one mask is selected from a plurality of masks based on the evaluating. The plurality of masks are formed in advance to have different wiring mask patterns to cause the numbers of semiconductor elements connected in parallel with each other among the plurality of semiconductor elements of the buffer circuit to be different from each other. In the method, a wiring pattern corresponding to the wiring mask pattern is formed by using the selected one mask.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: November 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Hirayu
  • Patent number: 8304261
    Abstract: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting an intensity of a second light of a second light source on the basis of the light reflectance, the second light has diffusion property, and a thermal treatment unit irradiating the treatment target with the second light having adjusted the intensity of the second light by the light irradiation controller.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: November 6, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tomohiro Kubo
  • Patent number: 8236579
    Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tzu Lu, Hung Chang Hsieh, Kuei Shun Chen, Hsueh-Hung Fu, Ching-Hua Hsieh, Shau-Lin Shue
  • Publication number: 20120164758
    Abstract: An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
    Type: Application
    Filed: March 2, 2012
    Publication date: June 28, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Stephen E. Greco, Kia S. Low
  • Publication number: 20120122248
    Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device having a buffer circuit. In the method, a plurality of semiconductor elements is formed on a semiconductor substrate. The plurality of semiconductor elements are connected in parallel to each other in the buffer circuit. In the method, driving forces of the formed semiconductor elements is evaluated. In the method, one mask is selected from a plurality of masks based on the evaluating. The plurality of masks are formed in advance to have different wiring mask patterns to cause the numbers of semiconductor elements connected in parallel with each other among the plurality of semiconductor elements of the buffer circuit to be different from each other. In the method, a wiring pattern corresponding to the wiring mask pattern is formed by using the selected one mask.
    Type: Application
    Filed: September 16, 2011
    Publication date: May 17, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tsuyoshi Hirayu
  • Publication number: 20120111391
    Abstract: A photovoltaic structure is provided. The photovoltaic structure has photovoltaic elements that can be electrically connected to one another to reduce mismatch. The photovoltaic elements can be electrically connected based on sorting the photovoltaic elements by irradiance level, minimizing mismatch, or maximizing output power. Where sorting is used, the photovoltaic elements can be connected in a serpentine arrangement.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 10, 2012
    Inventors: Mohamed Zakaria Mohamed Ahmed SHAMSELDEIN, Mehrdad Kazerani, Magdy Salama
  • Patent number: 8135485
    Abstract: A method for aligning a substrate to a process center of a support mechanism is provided. The method includes determining substrate thickness after substrate processing at a plurality of orientations and at a plurality of radial distances from a geometric center of the substrate. The method also includes deriving a set of process rate values from substrate thickness and process duration. The method further includes creating for a process rate an off-centered plot, which represents a substantially concentric circle whose points are a circumference of the off-centered plot having substantially the first process rate. The method yet also includes applying a curve-fitting equation to the off-centered plot to determine a set of parameters. The method yet further includes teaching a set of robot arms the set of parameters, thereby enabling the set of robot arms to align another substrate that is supported by the support mechanism with the process center.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: March 13, 2012
    Assignee: Lam Research Corporation
    Inventors: Jack Chen, Andrew D. Bailey, III, Ben Mooring, Stephen J Cain
  • Patent number: 8129201
    Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: March 6, 2012
    Assignee: Nikon Corporation
    Inventor: Kazuya Okamoto
  • Publication number: 20120012753
    Abstract: A solid-state imaging device according to one embodiment includes a plurality of signal output units. Each of the plurality of signal output units includes a first input terminal electrode group that includes a plurality of terminal electrodes for inputting a reset signal, a hold signal, a horizontal start signal, and a horizontal clock signal and a first output terminal electrode that provides output signals. The solid-state imaging device further includes a second input terminal electrode group that includes a plurality of terminal electrodes for receiving the reset signal, the hold signal, the horizontal start signal, and the horizontal clock signal, a plurality of switches that switch an electrode group which is connected with integrating circuits, holding circuits, and a horizontal shift register between the first input terminal electrode group and the second input terminal electrode group, and a second output terminal electrode.
    Type: Application
    Filed: March 26, 2010
    Publication date: January 19, 2012
    Applicant: Hamamatsu Photonics K.K.
    Inventors: Kazuki Fujita, Ryuji Kyushima, Harumichi Mori
  • Publication number: 20110315198
    Abstract: A photoelectric conversion module and a method of manufacturing the same are disclosed. The photoelectric conversion module may include a light-receiving substrate in which a first functional layer having a photoelectrode is formed, a counter substrate that faces the light-receiving substrate and is electrically coupled to the light-receiving substrate and in which a second functional layer having a counter electrode is formed. The photoelectric conversion module may include a sealant formed between the light-receiving substrate and the counter substrate and positioned so as to divide a plurality of unit photoelectric cells formed between the light-receiving substrate and the counter substrate. The photoelectric conversion module may include a plurality of interconnection units electrically connecting adjacent unit photoelectric cells.
    Type: Application
    Filed: March 9, 2011
    Publication date: December 29, 2011
    Applicant: SAMSUNG SDI CO., LTD.
    Inventors: Hyun-Chul Kim, Jung-Suk Song