Abstract: Disclosed are methods and apparatus for detecting defects in a partially fabricated semiconductor device with self-aligned contacts. The self-aligned contacts are formed from a first layer with a plurality of contact portions, a second layer with a plurality of conductive lines that are each aligned proximate to an associated underlying contact portion, and a third insulating layer formed over the conductive lines and their proximate underlying contact portions. The third insulating layer has a plurality of vias formed therein that are each formed alongside a one of the conductive lines and over its proximate underlying contact portion. A charged particle beam is scanned over a portion of the vias to form a voltage contrast image of each via. When a minority of the vias in the image have a significantly different brightness level than a majority of the vias, it is then determined that the minority of vias have defects.

Abstract: A method of measuring the stress migration of vias, and a the structure, the method comprising the following steps. A metal line having a middle and opposing first and second ends is formed. First and second opposing pads electrically connected to the respective opposing first and second ends of the metal line through respective first and second step-width line structures are formed. A third pad connected to the metal line proximate its first end by a first via through a first metal structure is formed. A fourth pad connected to the metal line proximate its second end by a second via through a second metal structure is formed. The first and second vias are equidistant from the respective first and second ends of the metal line. The stress migration of the first via is determined by measuring the: sheet resistance between the first pad and the third pad; and/or the stress migration of the second via is determined by measuring the sheet resistance between the fourth pad and the second pad.

Abstract: The disclosure is directed toward an optical excitation/detection device that includes an arrayed plurality of photodetectors and discrete photoemitters, as well as a method for making such a device. A CMOS fabricated photodetector array includes an arrayed plurality of photoreceptor areas and photoemitter areas, wherein each photoreceptor area includes a CMOS integrated photoreceptor and each photoemitter area includes at least two buried electric contact pads. The CMOS array is selectively etched back at the locations of the photoemitter areas for regions to reveal the buried contact pads. A plurality of discrete semiconductor photoemitter devices (such as, for example, light emitting diodes) are inserted into, and mechanically retained within, the regions of the CMOS fabricated photodetector array.

Abstract: A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Abstract: A test mode control circuit for reconfiguring a device pin of an integrated circuit chip which is initially configured in a test mode includes an input register for applying trim/configuring data to one or more components on an integrated circuit chip; a device pin; an output register for receiving output data from an integrated circuit on an integrated circuit chip which integrated circuit has had one or more of its elements trimmed/reconfigured; an I/O logic circuit for controlling the device pin to operate as a test pin to selectively deliver the trim/configuring data to the input register and receive output data form the output register; a programmable ray including a plurality of logic state elements for permanently mapping a selected set of the trim/configuring data from the input register, the programmable array including a test bit; and a switching system for applying the trim/configuring data to the one or more components on the integrated circuit when the test bit is in a first, test mode and for ap

Abstract: A polymer memory device includes two organic adhesion layers that facilitate an integral package comprising a lower and an upper electrode and the ferroelectric polymer memory structure. The ferroelectric polymer memory structure includes crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure includes spin-on and/or Langmuir-Blodgett deposited compositions. A memory system allows the polymer memory device to interface with various existing hosts.

Abstract: There is provided a method of fabricating a semiconductor device whereby fine patterns are formed with high dimensional accuracy by means of multiple exposures, using a phase shift mask and a trim mask. Phases are periodically assigned to shifter patterns within a given range from patterns generated with the phase shift mask, respectively.

Abstract: A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract: The intensity of the light emitted from the light-emitting diode on wafer is measured and then the potential difference between the terminals of the light-emitting element, and the plasma current flowing thereinto are derived from measured light intensity. Since the use of a camera enables non-contact measurement of emitted light intensity, the lead-in terminals for lead wires that are always required in conventional probing methods become unnecessary. In addition, since the target wafer does not require lead wire connection, wafers can be changed in the same way as performed for etching.

Abstract: A chip module element having an array of capacitors, a planar interconnect structure coupled to the array of capacitors, and a multilayer circuit structure coupled to the planar interconnect structure. The planar interconnect structure includes a plurality of conductive elements (e.g., z-connections and conductive posts) electrically communicating the capacitors and the multilayer circuit structure. A plurality of conductive pins is coupled to the multilayer circuit structure. The array of capacitors is capable of being charged by providing an electrical current which passes from the pins, through the multilayer circuit structure, through the conductive elements, and to the capacitors. A method for making a chip module element comprising forming an array of capacitors, electrically testing the capacitors in the array to determine which capacitors are defective and which are acceptable, and storing data of the defective capacitors in an information storage medium.

Abstract: A package structure and method for making devices of system-in-a-package (SiP). Substrates with integrated and assembled elements can be aligned and pre-bonded together, and fluidic encapsulating materials is applied to seal the rest opening of pre-bonded interface of substrates. Three dimensional and protruding microstructures, elements, and MEMS devices can be accommodated and protected inside a spatial space formed by the bonded substrates. By applying the technologies of flip-chip, chip-scale-packaging, and wafer-level-packaging in conjunction with present invention, then plural elements and devices can be packaged together and become a system device in wafer-level-system-in-a-package (WLSiP) format.

Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.

Abstract: A method of forming metal posts. A fixture having an array of wire guide heads is provided. A conductive wire is threaded through a hole in each wire guide heads. The wire guide heads have a transient electric arcing mechanism for heating the conductive wire so that a teardrop shaped blob of material is formed at the tip of the conductive wire. The wire guide heads on the fixture are pulled towards a substrate, thereby forming a plurality of metal posts over the substrate. The technique of forming metal posts finds applications in the manufacturing of printed circuit board, package substrate (carrier) and silicon wafer.

Abstract: A wiring editing method for a semiconductor package of this invention includes the steps of assuming virtual circular arcs R1 to R4 in consideration of a clearance around a predetermined via 11a in a designated area on a virtual plane, drawing a regular polygon 12 circumscribing each of the virtual circular arcs R1 to R4, drawing a tangent from a via 11 crossed by one of the virtual circular arcs R1 to R4 to the crossing virtual circular arc and connecting to the regular polygon 12 circumscribing the crossing virtual circular arc to thereby form a wiring pattern 13 and moving or omitting redundant line segments forming the regular polygon 12 in the wiring pattern 13 to change a wiring route when an offset occurs in the wiring pattern 13 passing between the vias 11 inside the designated area.

Abstract: A semiconductor device producing method and a semiconductor device producing system employs a processing apparatus provided with a dust particle detecting apparatus. The dust particle detecting apparatus measures the condition of adhesion of dust particles adhering to a work at least before or after processing the work, manages the condition of incremental adhesion of dust particles to the work resulting from processing for each lot of works or for each work on the basis of the measured condition of adhesion of dust particles measured before or after processing the work, and determines the time when the processing apparatus is to be cleaned or the cycle of cleaning the processing apparatus on the basis of the managed condition of adhesion of dust particles.

Abstract: Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device structures and thereby potentially expose the structures in an adverse manner. Typical methods include the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a portion of the substrate with a capping insulating layer such as silicon nitride layer. The capping insulating layer is then covered with an upper interlayer insulating layer different from the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then dry-etched in sequence to form a first narrow contact hole that exposes the substrate, but preferably does not expose the interconnection patterns.

Abstract: First, a pattern of electrodes or interconnects is formed on a semiconductor substrate. Next, a first insulating film, which will be dry-etched at a relatively high rate and exhibit relatively high planarity, is deposited over the substrate as well as over the pattern. Subsequently, a second insulating film, which will be dry-etched at a relatively low rate and exhibit relatively low planarity, is deposited over the first insulating film. Thereafter, a multilayer structure, including a ferroelectric film, is formed on the second insulating film and then dry-etched and patterned, thereby forming an electronic device out of the multilayer structure.

Abstract: An automatic wiring method for a semiconductor package includes: a provisional wiring step for sequentially specifying a plurality of lines of the terminals from the innermost periphery to the outermost periphery of bonding pads, connecting the bonding pads to predetermined vias present on the specified line of the terminal with line segments, and provisionally determining a wiring route for each line of the terminal such that the line segment passes through between the vias in each line of the terminal at equal intervals; and a wiring formation step for forming the wiring based on a design rule such that the wiring pattern passes through between the lines of the terminals with uniform intervals between wires based on the provisionally wired wiring routes.

Abstract: Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed an etch stop layer interposed between a first dielectric layer and second dielectric layer within a non active product region of a substrate, but not within an active product region of the substrate. Within the dual damascene method, an endpoint for forming a trench within a dual damascene aperture within the active product region is sensed by reaching the etch stop layer when forming a dummy trench within the non active product region.

Abstract: A method for producing a probe unit for contacting an electronic circuit such as a wafer or a die having a predetermined pattern of contact pads deployed in a common plane. The method employes a base plate of made of a material capable of surface uplift when irradiated. On the surface of the base plate locations corresponding to said contact pads are determined. Further, the base plate is irradiated at the determined locations by means of a laser. This results in forming conical surface uplifts. The method further includes plating the conical surface uplifts with an electrically conductive material and providing means for electical connection between said plated conical surface uplifts and an external device.

Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation. Since each die attach site includes a die attached thereto, the structural integrity of the mounting substrate is maintained and there is greater volume control of encapsulation material in the transfer molding operation to prevent waste and shortage of the encapsulation material.

Abstract: An apparatus includes a carbon nanotube coupled with a first device and a second device of an integrated circuit, wherein electrons can flow between the first device and the second device along the carbon nanotube. Doped amorphous carbon is deposited on the integrated circuit structure. The doped amorphous carbon is planarizing and patterned to form a trench. Carbon based precursor material is deposited in the trench. The carbon based precursor material is converted into the carbon nanotube, wherein the carbon nanotube connects the first device with the second device.

Abstract: An electric-circuit fabricating system for fabricating an electric circuit, by performing a working operation on a circuit substrate, including a substrate holding device to hold the substrate, an imaging device to image a surface of the substrate on which the working operation is to be performed, an imaging control device to control the imaging device to take an image of a substrate-position fiducial mark provided on the substrate, and obtaining substrate-position information on the basis of the image, and a working device to perform the working operation on the substrate, on the basis of the substrate-position information, and wherein the imaging control device is operable to control the imaging device to take an image of a substrate ID mark provided on the substrate as held by the substrate holding device, for obtaining substrate identifying information identifying the substrate, on the basis of the image of the substrate ID mark.

Abstract: Within both a system for managing a work-in-process (WIP) workload within a fabrication facility and a method for managing the work-in-process (WIP) workload within the fabrication facility, there is determined from an overall routing sequence for fabricating the work-in-process (WIP) workload within the fabrication facility a series of routing sub-sequences which correspond with a series of service codes. By using the series of service codes for routing the work-in-process (WIP) workload within the fabrication facility there may be realized operational efficiencies when fabricating the work-in-process (WIP) workload within the fabrication facility.

Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 &mgr;m or smaller, and can be cut off without causing damage to a layer beneath the fuses.

Abstract: A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

Abstract: An integrated circuit having programmable fuse provisions separate from critical circuitry, for storing chip specific operational information necessary for proper integrated circuit operation. These separate provisions include a fuse block which contains the programmable fuse. The fuse block is positioned adjacent to a current source input which is used to provide current to the programmable fuse for purposes of programming the programmable fuse with the chip specific operational information.

Abstract: A process for manufacturing a semiconductor device includes the formation of tungsten contact plugs suitable for very small geometry devices. As part of the process a tungsten barrier layer is deposited into vias and covering the walls of the vias by a process of ionized metal plasma deposition. The tungsten layer deposited in this manner provides a barrier layer, adhesion layer, and nucleation layer for the subsequent chemical vapor deposition of tungsten contact plug material. Together the two layers of tungsten form contact plugs having a low resistance even when used in the fabrication of very small geometry devices.

Abstract: One or more contact elements for transmitting calibration data during the calibration of a sensor of the sensor device are electrically connected to a signal processing unit of the sensor. The contact element has a contact region in a groove of a housing part of the sensor device. A sealing compound, which seals the contact region, is introduced into the groove and a cover is brought into contact with the sealing compound in the groove. The groove, the sealing compound, and the cover are configured and they interact in such a way that the chamber communicates only with a working medium which is to be sensed by the sensor.

Abstract: A silicon layer is etched using a plasma etcher equipped with an endpoint control device. CF4 and N2 are provided to the plasma etcher at lower flow rates than those typically used during fixed time etching processes. The endpoint control device monitors optical emissions from the etching chamber at a particular wavelength to detect a predetermined change in intensity. When the change in intensity is detected, the etching is terminated.

Abstract: A fuse link redundancy structure to implement redundant circuits within an integrated circuit has an insulating layer over a conductive layer of the fuse link is sufficiently thin and transparent to allow destruction of the conductive layer by an intense laser light. The redundancy structure has a fusible link formed of a layer of a conductive material deposited upon an insulating layer such as field oxide on the semiconductor substrate and connected between the redundant circuits and other circuits present on the integrated circuit. The layer of conductive material is either formed of a metal such as Aluminum or Tungsten, a heavily doped polycrystalline silicon, or an alloy of a metal such as Tungsten and a heavily doped polycrystalline silicon. A hard mask layer is placed upon the layer of conductive material during transistor processing to protect the layer of conductive material during formation of self-aligned sources and drains of transistors of the integrated circuit.

Abstract: A multichip module includes an interposer formed from a semiconductor material and having a plurality of interconnections formed on a surface of the interposer. A plurality of integrated circuits is mounted on the interposer and is electrically coupled to the interconnections. One or more repeater circuits are disposed along a length of at least one of the plurality of interconnections. A lid seals the plurality of integrated circuits from environmental insults. As a result, RC transmission line effects and crosstalk effects are reduced for signals propagating from one of the integrated circuits to another across the surface of the interposer. Additionally, thermal coefficient of expansion mismatch is reduced or eliminated between the integrated circuits and interposer.

Abstract: A probe card, a test method and a test system for testing semiconductor wafers are provided. The test system includes the probe card, a tester for generating test signals, and a wafer prober for placing the wafers and probe card in physical contact. The probe card includes contacts for electrically engaging die contacts on the wafer. The probe card also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the probe card contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple dice in parallel. Reading of the dice can be performed in groups up to the limit of the tester resources. In addition to expanding tester resources, the multiplex circuit maintains the individuality of each die, and permits defective dice to be electrically disconnected.

Abstract: Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (21), in conjunction with which, by means of a solder-deposit carrier (25) which is provided with a structured, electrically conductive coating (12) with bond pads (17) for the arranging of solder deposits (28) and their transfer to correspondingly arranged bond pads (22) of a substrate (21), an electrical check of the wiring structure of the substrate (21) takes place during the transfer of the solder deposits (28).

Abstract: A high density interconnect land grid array package device combines various electronic packaging techniques in a unique way to create a very thin, electrically and thermally high performance package for single or multiple semiconductor devices. A thin and mechanically stable substrate or packaging material (12) is selected that also has high thermal conductivity. Cavities (14) in the substrate or packaging material (12) accommodate one or more semiconductor devices that are attached directly to the substrate or packaging material. At least one of said semiconductor devices includes at least one optical receiver and/or transmitter. A thin film overlay (18) having multiple layers interconnects the one or more semiconductor devices to an array of pads (20) on a surface of the thin film overlay facing away from the substrate or packaging material.

Abstract: Microstructures, including a plurality of spaced structural members which are bendable under an external force, undergo a treating method using a first treating liquid, to prevent permanent deformation, by removing the microstructure from the first treating liquid to an environment having a pressure less than atmospheric pressure; or moving the microstructure from the first treating liquid to a second treating liquid having a smaller surface tension than the first treating liquid, and then removing the microstructure from the second liquid; or drying the microstructure removed from the first treating liquid by exposing same to a liquid vapor having a smaller surface tension than the first treating liquid; or removing the microstructure from the first treating liquid to the atmosphere, and drying the microstructure using an energy beam of high intensity or an ultrasonic wave.

Abstract: A method of fabricating a semiconductor device characterized in that the method includes the steps of forming basic structures of unit FETs on each of ‘m’ active layer regions more than the number of designed unit FETs and determining the number ‘n’ of desired basic structures on the basis of a drain current value of the semiconductor device predicted from a measured value of the drain current characteristics of one of the basic structures. The contact holes for electrical connections to electrodes of each of the unit FETs are formed for only the regions on ‘n’ basic structures in an inter-layer insulating film. In this manner, there is provided a method of fabricating a semiconductor device, the method being capable of improving degraded characteristics after the characteristics of TEG-FET have been measured.

Abstract: Disclosed is a ferroelectric random access memory device having ferroelectric capacitors. The FRAM device according to the present invention prevents the polymer by using the TiN layer as an etching (or hard) mask and prevents the Ti atoms from being diffused into the ferroelectric layer by applying the thermal treatment to the TiN pattern on the Pt upper electrode. Furthermore, adhesive strength between the capping oxide layer and the Pt upper electrode is improved by the oxidation of the TiN pattern.

Abstract: A method is described for progressively forming a fuse access openings in integrated circuits which are built with redundancy and use laser trimming to remove and insert circuit sections. The fuses are formed in a polysilicon layer and covered by one or more relatively thin insulative layers. An etch stop is patterned over the fuse in a higher level polysilicon layer or a first metallization layer. Additional insulative layers such as inter-metal dielectric layers are then formed over the etch stop. A first portion of the laser access window is then etched during the via etch for the top metallization level. The etch stop prevents removal of the insulation subjacent to it. Cumulative thickness non-uniformities in the relatively thick upper insulative layers are thus removed from the fuse window. The etch stop is removed during patterning of the top level metallization.

Abstract: A semiconductor device according to the present invention is formed on a semiconductor chip and has a common module and a plurality of selectable modules. Each selectable module on the semiconductor chip performs a defined function and has a separate input power terminal. The device also has a voltage pad for connecting to a first voltage source having a first voltage level, so that the voltage pad supplies power to the input power terminal of each selectable module. The output of each selectable module may be connected to one common output pad, or alternatively, may be connected to a dedicated output pad. Also connected to each selectable module is a die/sort pad used for disconnecting a corresponding selectable module from the first voltage source. In the wiring between the first voltage source and the selectable modules, there is provided a plurality of fuses, each fuse having first and second terminals.

Abstract: A method of patterning a layer on sidewalls of a trench in a substrate for integrated circuits includes the steps of forming an insulator layer on sidewalls of a trench in a substrate with a horizontal top surface above the sidewalls, recessing a masking material such as an organic photoresist in the trench below the top surface of the substrate such that a portion of the insulator layer on the sidewalls of the substrate is exposed, and etching the insulator layer with a gaseous hydrogen flouride-ammonia mixture. The masking material and the substrate are composed of a different material than the insulator layer.

Abstract: The disclosed device and method can inspect the CMOS integrated circuit devices at high precision on the basis of the static current of the voltage supply connected thereto. A CMOS integrated circuit comprises: at least one CMOS circuit having at least one P-channel MOS transistor and at least one N-channel MOS transistor; a first pad connected to a source of the P-channel MOS transistor; a second pad connected to a source of the N-channel MOS transistor; a third pad connected to an N-type substrate or an N-type well formed with the P-channel MOS transistor; and a fourth pad connected to a P-type substrate or a P-type well formed with the N-channel MOS transistor.

Abstract: A variety of test structures may be fabricated with aluminum runners and overlying dielectrics. The dielectrics are removed and bumps are observed upon the aluminum runners. Unevenness in the bump distribution is a predictor of long term reliability problems. A test structure may be utilized to design integrated mass production fabrication processes.

Abstract: This invention relates to a process for amplifying and detecting any desired specific nucleic acid sequence that exists in a nucleic acid or mixture thereof. The process comprises treating single strand RNA or separated complementary strands of DNA target with a molar excess of oligonucleotide complement pairs in which these oligonucleotide complement pairs have sequences complementary to the target, under hybridizing conditions. In one embodiment, the oligonucleotide complement pairs may have a gap of one or more bases which may be repaired (filled) by enzymes. The oligonucleotide complement pairs are joined together, forming joined, oligonucleotide product. The target/joined product hybrid nucleic acids are then denatured to single strands again, at which point both the target and the joined products can form hybrids with new oligonucleotide complement pairs. The steps of the reaction may be carried out stepwise or simultaneously and can be repeated as often as desired.

Abstract: A method of packaging a semiconductor device (10) partitions a distribution substrate (20, 40) into regions (31-34) such that attachment points (22) for electrically coupling to the semiconductor device lie in a first region (31). A first set of conductors are routed from a portion of the attachment points to terminals in a second region (32). Another portion of the attachment points are assigned to available routing channels of the second region for disposing a second set of conductors across the second region to a third region (33). Partitioning improves routing efficiency without requiring objects to be located on grid points or restricting the angles of the routing channels.

Abstract: A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3.times.3 block of the first pads.

Abstract: To form in a batch manner a thin-film wiring pattern in high precision over an entire region of a ceramics multilayer wiring board containing distortion and deformation, a correction amount of the ceramics multilayer wiring board (rotation angle and movement amount of position of this ceramics multilayer wiring board) is calculated in a computer by applying, for instance, the least squares method to positional coordinate values of each of the LSI mounting areas of the ceramics multilayer board and also to positional coordinate values corresponding thereto on a photomask. A support apparatus for supporting the multilayer wiring board is controlled based upon the calculated correction amount, so that the multilayer wiring board can be aligned with respect to the photomask.

Abstract: An apparatus (400) enclosing a portion of a substrate (401) is used for affixing at least one component to a corresponding circuit of the substrate when a manufacturing line (800) ceases to operate. The apparatus includes a conveyor (400), heating elements (102), and a controller (816) for controlling operation of the apparatus (400). The conveyor is used for indexing the substrate periodically through the apparatus. The heating elements are used for dividing the portion of the substrate enclosed by the apparatus into controllable temperature zones (902). The controller is adapted to cause each of the plurality of heating elements to dynamically adjust the temperature of each of the controllable temperature zones upon the indexing process of the manufacturing line (800) ceasing to operate, until at least one component of each circuit enclosed by the apparatus has been adequately affixed to its corresponding circuit.

Abstract: In order to modify a combination of logic gates based on relationships between physical locations of the logic gates in a semiconductor integrated circuit which has already been subjected to layout design in the middle of design of the semiconductor integrated circuit, circuit portions whose combination is to be modified are specified, then the circuit portions are transformed into logically equivalent intermediate representations (NAND2s, IVs, etc.), then anew combination of the logic gates is generated based on the intermediate representation, and then the prior combination of the logic gates is replaced with the new combination of the logic gates.