Abstract: A compact laser programmable fuse structure has a central line and two sets of fuses extending from opposite sides of the central line. An opening through a passivation layer exposes the fuses and overlies the central line. In one embodiment, the opening also exposes the portions of the central line. The central line is made of fuse material or another material for which the opening does not create reliability problems. In one embodiment of the invention, the central line and the fuses are parts of a single contiguous region of polysilicon. This fuse structure has a length that is about half the length of conventional fuse structure having the same number of fuses because two fuses, one on either side of the central line, fit within a length used for a single fuse in conventional fuse structures.

Abstract: A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: Each circuit block of a plurality of circuit blocks on a semiconductor substrate is imaged in an exposure field defined by a reticle. The circuit blocks are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The circuit blocks are globally interconnected by depositing a blanket metal layer, masking the metal layer and etching the metal layer using a stitching reticle having an exposure field overlapping the plurality of circuit blocks. The combination of reticle-imaged circuit blocks allows each individual circuit block to be fabricated independently, using independent imaging resolution, layout rules, design rules, different polysilicon sizes and source/drain region sizes and the like. In addition different reticles, including different reticle types, resolutions and qualities may be used to construct the various circuit blocks.

Abstract: An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been created. The method is a two step process, in which a first stripping step is in a plasma containing O.sub.2 and H.sub.2 O and a second stripping step is in a plasma containing O.sub.2.

Abstract: A process of Pb/Sn evaporation eliminates haloes in the manufacture of solder bump interconnects. This robust process of forms solder bump interconnects and reduces critical molebdnum mask sensitivity. Vacuum evaporation through which Pb/Sn C4 pads are deposited is performed by maintaining parallel temperature gradients between the molybdenum mask and silicon wafer, thus resulting in elimination of connecting haloes and yield losses.

Abstract: In a process for arranging printed conductors on the surface of a semiconductor component, printed conductors connect wire ranges that are designed as polygons. The polygons are composed of individual edge points. With regard to each of these edge points, it is determined whether it can be connected by a printed conductor running parallel to the coordinate system or diagonally to the coordinate system. Additional edge points may also have a "not connectable" status.

Abstract: A method for manufacturing ferroelectric thin-film which is used as a memory cell for an FRAM includes the steps of: (a) forming a lower electrode, a ferroelectric thin-film and an upper Pt electrode on a substrate in sequence; (b) forming a photoresist on the upper Pt electrode; (c) patterning the photoresist in a predetermined pattern; and (d) etching the substrate, the step (d) including the steps of installing a holder to which a predetermined DC self bias voltage is generated in a chamber of a plasma etching apparatus around which an RF coil is wound, of injecting Ar, chloric and fluoric gases of a predetermined composition ratio into the chamber, of applying a RF power of a predetermined frequency and power to the RF coil to generate an inductively coupled plasma in the chamber, and of etching down the substrate from the upper Pt electrode to the ferroelectric thin-film to a predetermined depth by the plasma of the Ar, chloric and fluoric gases using the photoresist as a mask.

Abstract: A display device matrix comprising a plurality of aluminum scanning line electrodes and a plurality of associated chromium bonding pads, wherein each scanning line electrode has an associated repairing conductive layer which can connected the scanning line electrode with its associated bonding pad should a connection failure otherwise prevent electrical connection between the two.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming fuses (40) and conductive pads (46) above a semiconductor substrate (43); depositing a layer of cap oxide (44) over the fuses and the conductive pads; sintering the cap oxide; etching back the layer of cap oxide until the top surface of an insulator (42) over the fuses and the top surfaces of the conductive pads are exposed; performing electrical tests (48) by way of the conductive pads; trimming (50) at least a part of the fuses with a laser beam; depositing a silicon nitride layer (52) overall; depositing a mask coating over the silicon nitride; patterning the mask coating (54) to expose the conductive pads; and etching the mask coating and the silicon nitride layer to expose the conductive pads.