Abstract: A sacrificial layer is formed in a recess of a substrate, and leads extending from the substrate into an area of the sacrificial layer are formed. A cut is formed from the bottom surface of the substrate, the cut extending from the bottom surface to the area of the sacrificial layer via the substrate, then the sacrificial layer is removed. A probe unit can be obtained having the leads whose front portions extend beyond the edge of the substrate. A through conductor may be formed in a through hole formed in a substrate. Leads may be formed on a photosensitive etching glass substrate to thereafter selectively etch the chemically cutting type glass.

Abstract: Bumping a substrate having a metal layer thereon may include forming a barrier layer on the substrate including the metal layer and forming a conductive bump on the barrier layer. Moreover, the barrier layer may be between the conductive bump and the substrate, and the conductive bump may be laterally offset from the metal layer. After forming the conductive bump, the barrier layer may be removed from the metal layer thereby exposing the metal layer while maintaining a portion of the barrier layer between the conductive bump and the substrate. Related structures are also discussed.

Abstract: The invention enhances the reliability of a semiconductor device. A semiconductor device includes: a semiconductor substrate that includes an active element region, an integrated circuit having an active element in the active element region, and an electrode electrically connected to the integrated circuit; a resin layer that is formed on the surface of the semiconductor substrate where the electrode is also formed, so as to avoid the electrode; a wiring layer that extends from the electrode and across the top of the resin layer, and includes a plurality of electrically connecting portions; and an external terminal that is provided on the electrically connecting portions. The plurality of electrically connecting portions includes a first electrically connecting portion and a second electrically connecting portion. The surface area of the first electrically connecting portion is larger than the surface area of the second electrically connecting portion.

Abstract: In a method of forming a conductive line for a semiconductor device using a carbon nanotube and a semiconductor device manufactured using the method, the method includes activating a surface of an electrode of the semiconductor device using surface pretreatment to create an activated surface of the electrode, forming an insulating layer on the activated surface of the electrode, and forming a contact hole through the insulating layer to expose a portion of the activated surface of the electrode, and supplying a carbon-containing gas onto the activated surface of the electrode through the contact hole to grow a carbon nanotube, which forms the conductive line, on the activated surface of the electrode. Alternatively, the activation step of the surface of the electrode may be replaced with a formation of a catalytic metal layer on the surface of the electrode.

Abstract: A main object of the present invention is to provide a manufacturing method of a thin-film structural body removing a sacrifice film without removing other insulating films. In order to achieve the above-mentioned object, upon forming an anchor hole (52) which forms an opening on the surface of a wiring (45), two etching steps are employed on a sacrifice film (51). In the first etching step, the sacrifice film (51) is partially removed by a dry etching process with an anisotropy above a wiring (45) with the sacrifice film (51) being left. In the second etching step, the remaining sacrifice film (51) above the wiring (45) is removed by a wet etching process with an isotropic.

Abstract: A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a metal base, an insulative base, a routing line and an interconnect, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, the routing line is disposed on a side of the insulative base that faces towards the chip, and the interconnect extends through a via in the insulative base and electrically connects the metal base and the routing line, forming an opening that extends through the insulative base and exposes the pad, forming a connection joint that electrically connects the routing line and the pad, and etching the metal base such that an unetched portion of the metal base forms a pillar that overlaps and is aligned with the via and contacts the interconnect, wherein a conductive trace includes the routing line, the interconnect and the pillar.

Abstract: Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component substrate, such as a semiconductor die or other substrate, has dielectric material disposed on a surface thereof, surrounding but not covering interconnect elements, such as bond pads, on that surface. A second semiconductor component substrate, such as a carrier substrate with interconnect elements such as terminal pads, is adhered to the first semiconductor component substrate, forming a semiconductor package assembly having interconnect voids between the corresponding interconnect elements. A flowable conductive material is then injected into each interconnect void using an injection needle that passes through one of the substrates into the interconnect void, forming a conductive interconnect between the bond pads and terminal pads of the substrates.

Abstract: Spring structures are subjected to pre-release and post-release annealing to tune their tip height to match a specified target. Post-release annealing increases tip height, and pre-release annealing decreases tip height. The amount of tuning is related to the annealing temperature and/or time. Annealing schedules are determined for a pre-fabricated cache of unreleased spring structures such that finished spring structures having a variety of target heights can be economically produced by releasing/annealing the cache according to associated annealing schedules. Selective annealing is performed using lasers and heat absorbing/reflecting materials. Localized annealing is used to generate various spring structure shapes. Both stress-engineered and strain-engineered spring structures are tuned by annealing.

Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump.

Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up, wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the semiconductor dice.

Abstract: An electronic device and coupled flexible circuit board and method of manufacturing. The electronic device is coupled to the flexible circuit board by a plurality of Z-interconnections. The electronic device includes a substrate with electronic components coupled to it. The substrate also has a plurality of device electrical contacts coupled to its back surface that are electrically coupled to the electronic components. The flexible circuit board includes a flexible substrate having a front surface and a back surface and a plurality of circuit board electrical contacts coupled to the front surface of the flexible substrate. The plurality of circuit board electrical contacts correspond to plurality of device electrical contacts. Each Z-interconnection is electrically and mechanically coupled to one device electrical contact and a corresponding circuit board electrical contact.

Abstract: Microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, a method includes placing a plurality of singulated radiation responsive dies on a support member, electrically connecting circuitry of the radiation responsive dies to contacts of the support member, and forming a barrier on the support member between adjacent radiation responsive dies without an adhesive attaching the barrier to the support member. The barrier is formed on the support member after electrically connecting the circuitry of the dies to the contacts of the support member. The barrier can encapsulate at least a portion of the wire-bonds.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming an interconnection line over a ssubstrate. The interconnection line functions as a first electrode. A first insulating layer is formed on the substrate including the metal interconnection line. An electrode layer and an oxide layer are formed on the first insulating layer. A photoresist pattern is formed on the oxide layer. The oxide layer and the electrode layer are etched using the photoresist pattern as an etching mask. As a result, a second electrode and an oxide layer pattern, which are stacked, are formed over the interconnection line. At least the electrode layer is etched using a wet etching technique. The photoresist pattern is then removed.

Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.

Abstract: A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.

Abstract: A ball grid array for a flip-chip assembly is disclosed. The ball grid array includes a plurality of bumps bonded between an active surface of a semiconductor die and a top surface of a printed circuit board or any type of substrate carrier. The plurality of balls include at least one bump having a core material and an outer layer. The rigidity of the core material is greater than that of the material of the outer layer. Additionally, the melting temperature of the core material is higher than the material of the outer layer. By this arrangement, the core material with an outer layer provides bumps that are substantially uniform in height. In addition, the balls only procure marks or deformation to the core material during burn-in testing and reflow.

Abstract: The present invention relates generally to permanent interconnections between electronic devices, such as integrated circuit packages, chips, wafers and printed circuit boards or substrates, or similar electronic devices. More particularly it relates to high-density electronic devices. The invention describes means and methods that can be used to counteract the undesirable effects of thermal cycling, shock and vibrations and severe environment conditions in general. For leaded devices, the leads are oriented to face the thermal center of the devices and the system they interact with. For leadless devices, the mounting elements are treated or prepared to control the migration of solder along the length of the elements, to ensure that those elements retain their desired flexibility.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a conductive trace and a substrate, wherein the chip includes first and second opposing major surfaces and a conductive pad, the pad extends to the first surface of the chip, the substrate includes first and second opposing major surfaces, a conductive terminal and a dielectric base, the conductive terminal extends through the dielectric base to the first and second surfaces of the substrate, a cavity extends from the first surface of the substrate into the substrate, the first surfaces of the chip and the substrate face in a first direction, the second surfaces of the chip and the substrate face in a second direction, and the chip extends into the cavity, and then electrically connecting the conductive terminal to the pad using the conductive trace.

Abstract: A fabrication method of a window-type ball grid array (WBGA) semiconductor package is provided. With a chip being mounted over an opening formed through a substrate and electrically connected to the substrate by bonding wires through the opening, a molding process is performed to form a first encapsulant for encapsulating the chip. Then, a printing process is performed to form a second encapsulant for filling the opening and encapsulating the bonding wires. Finally, a plurality of solder balls are implanted on the substrate at area outside the second encapsulant. By implementing the molding process first and then the printing process, problems such as chip cracks, bond pad contamination and delamination generated in the prior art, can be eliminated.

Abstract: A multilayer ceramic substrate has a first conductive pattern that is transfer-printed on a ceramic substrate using an intaglio plate made of a flexible resin. The intaglio plate has a plurality of grooves with different depts. A first insulation layer is on the first conductive pattern, and a second conductive pattern is on the insulating layer. The two conductive patterns are coupled by a via.

Abstract: A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a very low dielectric constant. Additional benefits are realized by electrically insulating the wires against short-circuiting, by cushioning, the wires with a low modulus sheath, and by protecting chip bond pad metallization.

Abstract: A ball grid array semiconductor packaging technology is provided, which is characterized in that openings of a solder mask are formed on a given edge of a die attachment area, and entire or partial width of each opening is disposed outside the die attachment area. Accordingly, air within the opening of the solder mask is sufficiently eliminated during die bonding process, so as to prevent void formation as adhesive is filled into the opening. Therefore, in the follow-up steps, high temperature in reflowing process will not cause popcorn as in the prior-art, so as to remain good quality of the semiconductor package.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.

Abstract: Various aspects of the invention provide methods of manufacturing probe cards and test systems which may test microelectronic components using such probe cards. In one specific example, a probe card may be manufactured by forming a plurality of blind holes in a substrate, with each hole having a closed bottom spaced from a back of the substrate by a back thickness. An electrically conductive metal may be deposited on the substrate to fill the holes and define an overburden on the substrate. The metal in each hole may define a conductor. At least a portion of the overburden may be removed to electrically isolate each of the conductors from one another. A portion of the substrate including the back thickness is removed to define an array of pins extending outwardly from a remaining thickness of the substrate, with each pin being an exposed length of one of the conductors.

Abstract: A circuit device manufacturing method is provided, wherein contaminants attached to the top surfaces of conductive patterns 21 are removed using plasma to thereby improve the adhesion of conductive patterns 21 to a sealing resin 28. By selective etching of a conductive foil 10, separation grooves 11 are formed, thereby forming conductive patterns 21. A semiconductor element 22A and other circuit elements are mounted onto desired locations of conductive patterns 21 and electrically connected with conductive patterns 21. By irradiating plasma onto conductive foil 10 from above, contaminants attached to the surfaces of separation grooves 11 are removed.

Abstract: A method of fabricating an interconnect line comprises forming a wall, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at the bottom to form the interconnect line having a pre-determined gap between the substrate and a bottom of the line.

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, and the pillars are disposed outside the peripheries of the chips and aligned with one another. The conductive bond contacts and electrically connects the pillars.

Abstract: There are provided the steps of forming a wiring pattern in an area except packaging area on a mounted body, the package area in which electronic parts is mounted, mounting the electronic parts in the packaging area of the mounted body to direct a surface of the electronic parts, of which a connection terminal is formed, upward, and forming an insulating film which covers the electronic parts and the wiring pattern.

Abstract: An integrated circuit package having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body are proposed. It is a characteristic feature of the proposed encapsulating mold that the encapsulating-body cavity formed in the upper mold further includes a constricted cutaway portion in the rim thereof The constricted cutaway portion can be either uniform in thickness or formed in a multi-step staircase-like shape. During the molding process, the resin used to form the encapsulating body would flow into this constricted cutaway portion; and within the constricted cutaway portion, the resin would more quickly absorb the heat of the upper mold, thus increasing its viscosity and retarding its flowing speed. As a result, the resin would less likely to flash onto those surface parts of the substrate beyond the encapsulating body.

Abstract: A process for fabricating a flip-chip substrate with metal bumps thereon. A flip-chip substrate is provided with conductive points thereon and a conductive film is formed over the surface of the flip-chip substrate to cover the conductive points. A photoresist layer is formed over the conductive layer and then patterned to form openings exposing the underlying conductive points. A copper plating is performed to fill the openings as copper bumps. The photoresist layer and the conductive film are removed. Finally, a solder mask layer is formed over the flip-chip substrate and exposing the copper bumps and an anti-oxidation treatment is performed to finish exposing the copper bumps.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, providing a conductive trace and a metal base, wherein the conductive trace includes a routing line and a contact terminal, the routing line is disposed outside the metal base, the contact terminal extends from the routing line through the metal base, the contact terminal includes a plated metal that contacts and extends through the metal base, the plated metal forms a peripheral sidewall portion of the contact terminal, and the plated metal surrounds a central surface area without extending into the central surface area, then mechanically attaching the chip to the conductive trace, removing a portion of the metal base that contacts the plated metal, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: In one embodiment, the present invention includes an apparatus having a metal layer with a pad disposed above a substrate; and a cap disposed above the metal layer having a first portion to provide for contact with a probe and a second portion to provide a bonding surface, and the cap is electrically coupled to the pad.

Abstract: The specification describes interconnection techniques for interconnecting large arrays of micromechanical devices on a silicon platform. The problem of interconnection congestion is overcome by routing the interconnections through the substrate. The through interconnections are made by etching vias through the substrate by RIE, oxidizing the via sidewalls, and filling the vias with polysilicon.

Abstract: An interconnect assembly and methods for making and using the assembly. An exemplary embodiment of an aspect of the invention includes a contact element which includes a base portion adapted to be adhered to a substrate and a beam portion connected to and extending from the base portion. The beam portion is designed to have a geometry which substantially optimizes stress across the beam portion when deflected (e.g. it is triangular in shape) and is adapted to be freestanding. An exemplary embodiment of another aspect of the invention involves a method for forming a contact element. This method includes forming a base portion to adhere to a substrate of an electrical assembly and forming a beam portion connected to the base portion. The beam portion extends from the base portion and is designed to have a geometry which substantially evenly distributes stress across the beam portion when deflected and is adapted to be freestanding.

Abstract: A semiconductor device is disclosed in which a heat sink is difficult to warp and which is inexpensive.

Abstract: A gold-silver alloy bonding wire for a semiconductor device is provided. The bonding wire contains: a Au-Ag alloy including 5-40% Ag by weight in Au having a purity of 99.999% or greater; at least one element of a first group consisting of Pd, Rh, Pt, and Ir in an amount of about 50-10,000 ppm by weight; at least one element of a second group consisting of B, Be, and Ca in an amount of about 1-50 ppm by weight; at least one element of a third group consisting of P, Sb, and Bi in an amount of about 1-50 ppm by weight; and at least one element of a fourth group consisting of Mg, TI, Zn, and Sn in an amount of about 5-50 ppm by weight. The bonding wire is highly reliable with a strong tensile strength at room temperature and high temperature and favourable bondability. When the bonding wire is looped, no rupture occurs in a ball neck region. Also, no chip cracking occurs since the ball is soft.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A method for fabricating a chip size package having a metal runner capable of preventing split generation due to stress in a solder mask made of a polymer such as BCB. The disclosed method includes steps of forming a stress buffer layer on a semiconductor chip having a plurality of bonding pads to expose a bonding pad; applying negative type photoresist on the stress buffer layer; forming a photoresist pattern having a convex cross section and defining a metal runner formative region by exposing and developing the photoresist; forming a predetermined metal layer having a height similar to that of the photoresist pattern on the metal runner formative region; removing the photoresist pattern to form a metal runner being in contact with the bonding pads of the semiconductor chip and having a concave cross section; forming a solder mask to expose a ball land of the metal runner on the stress buffer layer including the metal runner; and adhering a solder ball on the exposed ball.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a conductive trace and an insulative base, wherein the chip includes a conductive pad and the insulative base contacts the conductive trace on a side opposite the chip, then forming a through-hole that extends through the insulative base and exposes the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: Provided is a method for producing a probe capable of keeping sure electric conduction between the probe and a conductive pad. The method comprises the steps of: applying photo resists onto the front and rear faces of a conductive plate-form material which is to make a probe; masking one face of the plate-form material with a first mask, and masking the other face of the plate-form material with a second mask; subjecting the photo resists to exposure to light and development, and step of using the photo resists remaining in the exposure and development step as mask materials to etch the plate-form material.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a conductive trace and an insulative base, wherein the chip includes a conductive pad, the conductive trace includes a bumped terminal, the bumped terminal includes a cavity that extends through the insulative base, and the insulative base contacts the conductive trace on a side opposite the chip, then forming a through-hole that extends through the insulative base and exposes the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, an insulative adhesive that attaches the chip to the conductive trace or an encapsulant that encapsulates the chip fills the cavity and provides compressible mechanical support for the bumped terminal.

Abstract: To improve the connection reliability at the time of packaging a semiconductor device and to make the method management easy in a semiconductor device manufacturing method. The semiconductor device comprises: a tub 1e for supporting a semiconductor chip 2; a sealing body 3 formed by sealing the semiconductor chip 2 with a resin; a plurality of leads 1a made of a copper alloy, exposed to the back face 3a of the sealing body 3, and having a soldered layer 8 on the exposed mounted face 1d; and wires 4 for connecting the pads 2a of the semiconductor chip 2 and the corresponding leads 1a.

Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad/via.

Abstract: A semiconductor chip assembly includes a semiconductor chip, a conductive trace, a connection joint, an insulative adhesive and an encapsulant. The conductive trace includes a routing line and a pillar. The routing line extends within and outside a periphery of the chip, and the pillar is disposed outside the periphery of the chip and extends away from the chip. The connection joint contacts and electrically connects the routing line and the pad. The adhesive is sandwiched between the routing line and the chip and contacts a surface of the routing line that faces away from the chip, thereby interlocking the routing line to the assembly. The encapsulant extends into a channel in the pillar, thereby interlocking the pillar to the assembly.

Abstract: The invention relates to a method for fabricating a microcontact spring on a substrate (1) with at least one contact pad (2) and a first insulator layer (13) with a window above the contact pad (2).

Abstract: A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover, the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.