Beam Lead Formation Patents (Class 438/611)
  • Patent number: 10276480
    Abstract: A substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar. The dielectric layer has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed adjacent to the first surface of the dielectric layer. The second circuit layer is disposed adjacent to the second surface of the dielectric layer and electrically connected to the first circuit layer. The second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads. The at least one conductive pillar is tapered toward the second circuit layer and disposed on one of the pads. A portion of the second surface of the dielectric layer is exposed from the second surface layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 30, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10236221
    Abstract: Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication while still allowing thick isolation layers to be deployed, in examples of the disclosure a pre-formed solid layer of dielectric material is bonded to the substrate over the first transformer coil or capacitive plate. The preformed solid layer is formed from a thick layer of solid dielectric material, which is ground to the required thickness, either prior to being bonded to the circuit substrate, or thereafter. Such techniques result in a thick isolation layer that is formed more quickly and with lower outgassing risk than conventional spin-coating or deposition techniques.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 19, 2019
    Assignee: Analog Devices Global
    Inventor: Alan John Blennerhassett
  • Patent number: 10170429
    Abstract: Package structures and methods for forming the same are provided. A package structure includes a package component including a first bump. The package structure also includes an intermetallic compound (IMC) on the first bump. The package structure further includes an integrated circuit die including a second bump on the IMC. The integrated circuit die and the package component are bonded together through the first bump and the second bump. The IMC extends from the first bump to the second bump to provide good physical and electrical connections between the first bump and the second bump.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Heng-Chi Huang, Chien-Chen Li, Kuo-Lung Li, Cheng-Liang Cho, Che-Jung Chu, Kuo-Chio Liu
  • Patent number: 9368462
    Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen Wu, Ming-Che Ho, Wen-Hsiung Lu, Chia-Wei Tu, Chung-Shi Liu
  • Patent number: 9153394
    Abstract: The invention concerns a method for the fabrication, on a plane substrate, of a microswitch actuatable by a magnetic field, comprising: a) the etching, in the upper face of the plane substrate, of cavities forming a hollow model of two strips, these cavities having vertical flanks extending perpendicularly to the plane of the substrate to form vertical faces of the strips, b) the filling of the cavities by a magnetic material to form the strips, then c) the etching in the substrate, by a method of isotropic etching, of a well that extends between the vertical faces of the strips and beneath and around one distal end of at least one of the strips to open out an air gap between these strips and make this distal end capable of being shifted between a closed position and an open position.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 6, 2015
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Henri Sibuet, Yannick Vuillermet
  • Patent number: 8975762
    Abstract: A semiconductor device includes a substantially rectangular semiconductor chip having an obverse surface, a first long side, a second long side opposite the first long side, a first short side and a second short side, and a plurality of bump electrodes. A wiring substrate has a main surface, a first side disposed outside of the semiconductor chip and extending substantially parallel with the first long side, a second side disposed outside of the semiconductor chip and extending substantially parallel with the second long side, and a plurality of wiring groups, each including a plurality of wirings. A semiconductor chip is mounted on the wiring substrate such that the obverse surface of the semiconductor chip is faced to the main surface of the wiring substrate and the first long side is located between the first side of the wiring substrate and the second long side, in a plan view.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hidenori Egawa
  • Patent number: 8916421
    Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: December 23, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhiwei Gong, Navjot Chhabra, Glenn G. Daves, Scott M. Hayes
  • Patent number: 8815731
    Abstract: A semiconductor package and a method for fabricating the same. The semiconductor package includes a first substrate including a first pad, a second substrate spaced apart from the first substrate and where a second pad is formed to face the first pad, a first bump electrically connecting the first pad to the second pad, and a second bump mechanically connecting the first substrate to the second substrate is disposed between the first substrate where the first pad is not formed and the second substrate where the second pad is not formed. A coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: August 26, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Young Lyong Kim, Hyeongseob Kim, Jongho Lee, Eunchul Ahn
  • Patent number: 8796132
    Abstract: Disclosed herein is a system and method for mounting semiconductor packages by forming one or more interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a target package. Mounting the interconnect may comprise ultrasonically welding the interconnects to the mounting pads, and the interconnect may be mounted via a mounting node on the end of the interconnect, wherein the mounting node may be formed by an electric flame off process. The interconnects may be trimmed to one or more substantially uniform heights, optionally using a laser or contact-type trimming system, and the tails of the interconnects may be supported during trimming. A top package may be bonded on the trimmed ends of the interconnects. During mounting, a support plate may be used to support the package, and a mask maybe used during interconnect mounting.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chung Sung, Yung Ching Chen, Chien-Hsun Lee, Chen-Hua Yu, Mirng-Ji Lii
  • Patent number: 8790965
    Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 29, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Dae Keun Park
  • Publication number: 20140138814
    Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.
    Type: Application
    Filed: October 9, 2013
    Publication date: May 22, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Abderrezak Marzaki, Yoann Goasduff, Virginie Bidal, Pascal Fornara
  • Patent number: 8703598
    Abstract: A manufacturing method of a lead frame substrate includes: applying a photosensitive resist or a dry film to first and second surfaces of a metal plate; pattern-exposing the photosensitive resist or the dry film, and then developing the first surface and the second surface to form on the first surface a first resist pattern for forming a connection post and to form on the second surface a second resist pattern for forming a wiring pattern; etching the first surface partway down the metal plate to form the connection post; filling the first surface with a pre-molding resin to a thickness with which the etched surface is buried; removing the pre-molding resin uniformly in a thickness direction of the pre-molding resin until a bottom surface of the connection post is exposed; and etching the second surface to form a wiring pattern.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 22, 2014
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Susumu Maniwa, Takehito Tsukamoto, Junko Toda
  • Patent number: 8697538
    Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Winbond Electronics Corp.
    Inventor: Lu-Ping Chiang
  • Patent number: 8686574
    Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: April 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Hidenori Egawa
  • Patent number: 8603861
    Abstract: Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: December 10, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Nelson Tam, Albert Wu, Chien-Chuan Wei
  • Patent number: 8586417
    Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: November 19, 2013
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: John A. Hughes, Christy A. Hagerty, Santos Nazario-Camacho, Keith K. Sturcken
  • Patent number: 8535986
    Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: September 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Liang Kng Ian Koh, Richard Mangapul Sinaga
  • Patent number: 8530276
    Abstract: The invention pertains to a method for manufacturing a microelectronic device on a substrate comprising at least one first electrical component and one second electrical component distributed respectively in first and second levels stacked one on top of the other on the substrate, this method comprising: the manufacture of at least one first arm and one second arm of different lengths, each of these arms directly and mechanically linking an electrical pad to a fixed anchoring point on the substrate, and the electrical pad is made inside the first level and then shifted, prior to the electrical connection of the second component, to a position of connection wherein the upper face of the electrical pad is in contact with the interior of the second level parallel to the substrate.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: September 10, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Thierry Hilt, Herve Boutry, Remy Franiatte, Stephane Moreau
  • Patent number: 8524593
    Abstract: An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 3, 2013
    Assignee: Semigear Inc
    Inventors: Chunghsin Lee, Jian Zhang
  • Patent number: 8519534
    Abstract: At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 27, 2013
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eugene M. Chow, Eric Peeters
  • Patent number: 8426963
    Abstract: A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first power chip has a first surface and a second surface opposing to the first surface. A first control electrode and a first main power electrode are disposed on the first surface, and a second main power electrode is disposed on the second surface. The second surface is disposed on the carrier, and electrically connected to the carrier through the second main power electrode. The second power chip has a third surface and a fourth surface opposing to the third surface. A third main power electrode is disposed on the third surface, and a fourth main power electrode is disposed on the fourth surface. The fourth surface is disposed on the first power chip. The first conductive sheet is electrically connected to the first main power electrode and the fourth main power electrode.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: April 23, 2013
    Assignee: Delta Electronics, Inc.
    Inventors: Jian-Hong Zeng, Shou-Yu Hong
  • Patent number: 8409924
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, David Chau, Gregory M Chrysler, Devendra Natekar
  • Patent number: 8409978
    Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 2, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, KiYoun Jang, HunTeak Lee
  • Patent number: 8390126
    Abstract: A module (20) can include a first substrate (12) comprised of a first material, at least a second substrate (22) comprised of at least a second material, selectively applied solder (14) of a first composition residing between the first substrate and at least the second substrate, and selectively applied solder (16) of at least a second composition residing between the first substrate and at least the second substrate. Preferably, no crack will exist in the module as a result of a reflow process of the solder due to the CTE mismatch between the first and second substrates. The different selectively applied solder compositions can have different melting points and can be solder balls, solder paste, solder preform or any other known form of solder.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: March 5, 2013
    Assignee: Motorola Mobility LLC
    Inventors: Vahid Goudarzi, Juli A. Abdala, Gulten Goudarzi
  • Patent number: 8384230
    Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: February 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hidenori Egawa
  • Patent number: 8258014
    Abstract: According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: September 4, 2012
    Assignee: Infineon Technologies AG
    Inventors: Cynthia Blair, Donald Fowlkes
  • Publication number: 20120217628
    Abstract: The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps.
    Type: Application
    Filed: February 24, 2011
    Publication date: August 30, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua CHOU, Yi-Jen LAI, Chun-Jen CHEN, Perre KAO
  • Patent number: 8237270
    Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: August 7, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazuhiro Kobayashi, Junichi Nakamura, Kentaro Kaneko
  • Patent number: 8198131
    Abstract: Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: June 12, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yi Weng, Chi-Chih Chu, Chien-Yuan Tseng
  • Patent number: 8179692
    Abstract: A board includes a board body; a first conductor provided at a first surface of the board body; and an electrically conductive connection terminal having a spring property. The connection terminal includes a first end part fixed to the first conductor; a second end part to be connected to a first object of connection to be placed opposite the first surface of the board body; and a projection part provided on the first end part so as to project toward the first conductor.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: May 15, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yoshihiro Ihara
  • Patent number: 8158508
    Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: April 17, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Ming-Ta Lei, Chuen-Jye Lin
  • Publication number: 20120068331
    Abstract: At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 22, 2012
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Eugene M. Chow, Eric Peeters
  • Patent number: 8132709
    Abstract: A semiconductor device comprises a semiconductor element having electrodes, a metal member, wires that electrically connect the semiconductor element and the metal member and/or electrodes within the semiconductor element, wherein the wires constitute at least a first wire loop and a second wire loop, the first wire loop is bonded at one end to a first bonding point and at the other end to a second bonding point, and has a flat part which includes the surface of a boll part and the wire located contiguously the ball part surface, and the second wire loop connects the surface of the ball part and a third bonding point.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: March 13, 2012
    Assignee: Nichia Corporation
    Inventors: Tadao Hayashi, Yoshiharu Nagae
  • Publication number: 20120043653
    Abstract: Disclosed herein is a lead pin for a package substrate. The lead pin for the package substrate according to the exemplary embodiment of the present invention includes a head part having one surface opposite to the package substrate and the other surface that is an opposite side to the one surface; and a connection pin having a pin shape bonded to the other surface of the head part, wherein the head part has a concave depression part toward the package substrate.
    Type: Application
    Filed: November 30, 2010
    Publication date: February 23, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Jae Oh, Jin Won Choi, Ki Taek Lee
  • Patent number: 8080859
    Abstract: The present invention relates to a semiconductor component that has a substrate and a projecting electrode. The projecting electrode has a substrate face, which faces the substrate and which comprises a first substrate-face section separated from the substrate by a gap. The gap allows a stress-compensating deformation of the projecting electrode relative to the substrate. The substrate face of the projecting electrode further comprises a second substrate-face section, which is in fixed mechanical and electrical connection with the substrate. Due to a smaller footprint of mechanical connection between the projecting electrode and the substrate, the projecting electrode can comply in three dimensions to mechanical stress exerted, without passing the same amount of stress on to the substrate, or to an external substrate in an assembly. This results in an improved lifetime of an assembly, in which the semiconductor component is connected to an external substrate by the projecting electrode.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: December 20, 2011
    Assignee: NXP B.V.
    Inventors: Joerg Jasper, Ute Jasper, legal representative
  • Patent number: 8034644
    Abstract: Methods of making a light emitter are disclosed herein. An embodiment of a method comprises fabricating a line of first leads, the line of first leads comprising a plurality connected individual first leads; fabricating a line of second leads, the line of second leads comprising a plurality of connected individual second leads; physically connecting the line of first leads to the line of second leads, wherein a first individual first lead is adjacent a first individual second lead; attaching a light emitting device to the first individual first lead; electrically connecting the light emitting device to the first individual second lead; encapsulating a portion of the individual first lead and a portion of the individual second lead as a single unit; and separating the encapsulated first individual lead and the second individual lead from the first line of leads and the second line of leads.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: October 11, 2011
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Kean Loo Keh, Lig Yi Yong, Kum Soon Wong
  • Patent number: 8026600
    Abstract: An interconnection structure suitable for use as an IC package, probe head or other electrical termination of high density where uninterrupted controlled impedance is desired is described.
    Type: Grant
    Filed: January 2, 2009
    Date of Patent: September 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy
  • Patent number: 8017452
    Abstract: A circuit element is disposed on an organic substrate and is connected to a wiring pattern provided on the organic substrate. Internal connection electrodes are formed on a support of a conductive material through electroforming such that the internal connection electrodes are integrally connected to the support. First ends of the internal connection electrodes integrally connected by the support are connected to the wiring pattern. After the circuit element is resin-sealed, the support is removed so as to separate the internal connection electrodes from one another. Second ends of the internal connection electrodes are used as external connection electrodes on the front face, and external connection electrodes on the back face are connected to the wiring pattern.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: September 13, 2011
    Assignee: Kyushu Institute of Technology
    Inventors: Masamichi Ishihara, Hirotaka Ueda
  • Patent number: 7985631
    Abstract: A method for packaging an integrated circuit. A barrier metal pattern is disposed on a baseplate. A conductive layer is disposed on the barrier metal pattern. A photoresist having a pattern is applied to the conductive layer. A via is then disposed on the conductive layer. An integrated circuit is coupled to the via and encapsulated. Then, at least a part of the baseplate is removed. An integrated circuit package is produced by the method.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: July 26, 2011
    Assignee: Broadcom Corporation
    Inventor: Tonglong Zhang
  • Patent number: 7982320
    Abstract: An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 19, 2011
    Assignee: Semigear Inc.
    Inventors: Chunghsin Lee, Jian Zhang
  • Publication number: 20110140266
    Abstract: An electrostatic capacitance-type input device includes: a first translucent conductive film that configures a first electrode that extends in a first direction in an input area on a substrate and second electrodes that extend in a second direction intersecting the first direction in the input area and are disconnected in intersection portions with the first electrode; an interlayer insulating film that is formed at least in areas overlapping the intersection portions; and a second translucent conductive film that configures relay electrodes formed on the interlayer insulating film to have sheet resistance lower than that of the first translucent conductive film and electrically connecting the second electrodes disconnected in the intersection portion by being electrically connected to the second electrodes in an area in which the interlayer insulating film is not formed and a peripheral wiring extending in a peripheral area of the substrate located to the outer side of the input area.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 16, 2011
    Applicant: SONY CORPORATION
    Inventor: Mutsumi Matsuo
  • Patent number: 7960211
    Abstract: Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 14, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Manolito Galera, Leocadio Morona Alabin
  • Patent number: 7923304
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside the conductive pillar; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: April 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, JoHyun Bae, Junghoon Shin
  • Patent number: 7915088
    Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: March 29, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazuhiro Kobayashi, Junichi Nakamura, Kentaro Kaneko
  • Patent number: 7915081
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, David Chau, Gregory M. Chrysler, Devendra Natekar
  • Publication number: 20110042802
    Abstract: A semiconductor device includes an electrode pad and an external connection terminal. The external connection terminal contains Sn equal to or more than 50 wt %, Sn and Pb equal to or more than 90 wt % in total, or Pb equal to or more than 85 wt %, and the surface thereof is coated with an Au layer. The thickness of the Au layer is preferably equal to or more than 10 nm and equal to or less than 1 ?m. The weight of the Au layer is preferably equal to or less than 0.6% of the weight of the external connection terminal.
    Type: Application
    Filed: July 19, 2010
    Publication date: February 24, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Fumiyoshi Kawashiro
  • Patent number: 7884006
    Abstract: Resilient spring contacts for use in wafer test probing are provided that can be manufactured with a very fine pitch spacing and precisely located on a support substrate. The resilient contact structures are adapted for wire bonding to an electrical circuit on a space transformer substrate. The support substrates with attached spring contacts can be manufactured together in large numbers and diced up and tested before attachment to a space transformer substrate to improve yield. The resilient spring contacts are manufactured using photolithographic techniques to form the contacts on a release layer, before the spring contacts are epoxied to the support substrate and the release layer removed. The support substrate can be transparent to allow alignment of the contacts and testing of optical components beneath. The support substrate can include a ground plane provided beneath the spring contacts for improved impedance matching.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 8, 2011
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Bruce Jeffrey Barbara
  • Patent number: 7838971
    Abstract: An apparatus and a method for packaging semiconductor devices. Disclosed are multi-die packaging apparatuses and techniques, especially useful for integrated circuit dice involving insulative substrates, such as silicon-on-insulator (SOI), where grounding of a base layer is not reasonably practical. Disclosed is a means for effectively grounding all layers of an integrated circuit device regardless of whether the device makes direct contact with a die-attach paddle.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: November 23, 2010
    Assignee: Atmel Corporation
    Inventor: Ken M. Lam
  • Publication number: 20100270668
    Abstract: A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.
    Type: Application
    Filed: April 28, 2009
    Publication date: October 28, 2010
    Applicant: WAFER-LEVEL PACKAGING PORTFOLIO LLC
    Inventor: Phil P. Marcoux
  • Patent number: RE42542
    Abstract: An electronic device and coupled flexible circuit board and method of manufacturing. The electronic device is coupled to the flexible circuit board by a plurality of Z-interconnections. The electronic device includes a substrate with electronic components coupled to it. The substrate also has a plurality of device electrical contacts coupled to its back surface that are electrically coupled to the electronic components. The flexible circuit board includes a flexible substrate having a front surface and a back surface and a plurality of circuit board electrical contacts coupled to the front surface of the flexible substrate. The plurality of circuit board electrical contacts correspond to plurality of device electrical contacts. Each Z-interconnection is electrically and mechanically coupled to one device electrical contact and a corresponding circuit board electrical contact.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: July 12, 2011
    Assignee: Transpacific Infinity, LLC
    Inventor: Ponnusamy Palanisamy