Abstract: A substrate processing method includes: providing a substrate including a first region and a second region into a chamber; forming a deposit film on the first region and the second region of the substrate by generating a first plasma from a first processing gas, and selectively etching the first region with respect to the second region by generating a second plasma from the second processing gas containing an inert gas. The first processing gas is a mixed gas including a first gas containing carbon atoms and fluorine atoms and a second gas containing silicon atoms.

Abstract: A porous thin film includes a framework that includes a plurality of pores. The pores extend from an opening located at an upper surface of the framework to a bottom surface contained in the framework. A pore-coating film is formed on sidewalls and the bottom surface of the pores.

Abstract: A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.

Abstract: A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

Abstract: The present disclosure provides a method for preparing a semiconductor device with a copper-manganese liner. The method includes forming an opening structure in a first dielectric layer, wherein the opening structure has a first portion, a second portion and a third portion disposed between and physically connecting the first portion and the second portion; forming a lining material lining the first portion and the second portion of the opening structure and completely filling the third portion of the opening structure, wherein the lining material includes copper-manganese (CuMn); filling the first portion and the second portion of the opening structure with a conductive material after the lining material is formed; and performing a planarization process on the lining material and the conductive material.

Abstract: This application relates to a memory device and a method for manufacturing the same, including: a substrate on which an insulation structure and a plurality of first active structures are formed is provided. The plurality of first active structures are arranged at intervals in the insulation structure. A word line conductive layer is formed on the substrate by a physical vapor deposition process. The word line conductive layer is patterned and etched to obtain a plurality of word line structures arranged in parallel and at intervals and filling slots located between adjacent word line structures. The filling slots comprise first filling slots that expose both parts of top surfaces of the first active structures and parts of the top surface of the insulation structure. Second active structures are formed in the first filling slots, and isolation structures are formed in the first filling slots.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Abstract: A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Abstract: A planarization dielectric layer is formed over the semiconductor device on a semiconductor substrate. A device contact via structure is formed through the planarization dielectric layer. A planar dielectric spacer liner is formed over the planarization dielectric layer, and is patterned to provide an opening over the device contact via structure. An etch stop dielectric liner and a via-level dielectric layer are formed over the planar dielectric spacer liner. An interconnect via cavity may be formed through the via-level dielectric layer by a first anisotropic etch process that may be selective to the etch stop dielectric liner, and may be subsequently extended by a second anisotropic etch process that etches the etch stop dielectric liner. An interconnect via structure may be formed in the interconnect via cavity. A bottom periphery of the interconnect via structure may be self-aligned to the opening in the planar dielectric spacer liner.

Abstract: A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a bottom surface of the trench extending through the second dielectric layer, and forming a second opening in a bottom surface of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method further includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with the conductive material to form a conductive via.

Abstract: A reflective mask cleaning apparatus according to an embodiment comprises a first supply section configured to supply a first solution containing at least one of an organic solvent and a surfactant to a ruthenium-containing capping layer provided in a reflective mask; and a second supply section configured to supply at least one of a reducing solution and an oxygen-free solution to the capping layer. A reflective mask cleaning apparatus according to an alternative embodiment comprises a third supply section configured to supply a plasma product produced from a reducing gas to a ruthenium-containing capping layer provided in a reflective mask; and a second supply section configured to supply at least one of a reducing solution and an oxygen-free solution to the capping layer.

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

Abstract: Provided is a technique of forming an aluminum film that has high flatness and less cavities. Step S11 is forming a first film having a thickness that is equal to or greater than 0.1 ?m and less than 1 ?m, by sputtering a material onto a substrate. Step S12 is reflowing the first film by heating the first film. Step S13 is forming a second film by sputtering the material onto the first film that has been reflowed. Step S14 is reflowing the second film by heating the second film. Step S15 is forming a third film by sputtering the material onto the second film that has been reflowed. Step S16 is reflowing the third film by heating the third film.

Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

Abstract: The disclosure provides a FDSOI semiconductor structure and methods to fabricate it. The structure includes source and drain regions and gates respectively in an NMOS area and a PMOS area, a first oxide film layer formed on sidewalls of the source and drain contact holes, a metal layer deposited to fill the source and drain contact holes, a second oxide film layer formed on sidewalls of the gate contact holes, a metal layer deposited to fill the gate contact holes. Further the method includes growing an oxide film layer on the sidewalls of the contact holes between completing the contact etching process and filling the contact holes with the metal layer, followed by removing with etching the oxide film layer from the gates. Sizes of contact holes can be adjusted thereby.

Abstract: A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Abstract: A method of converting films is disclosed. A method of modifying films is also disclosed. Some methods advantageously convert films from a first elemental composition to a second elemental composition. Some methods advantageously modify film properties without modifying film composition.

Abstract: A semiconductor device including a first interconnection line having a first end and extending in a first direction; a first blocking pattern at the first end of the first interconnection line and adjacent to the first interconnection line in the first direction; a second interconnection line spaced apart from the first interconnection line in a second direction crossing the first direction and extending in the first direction, the second interconnection line having a second end; and a second blocking pattern at the second end of the second interconnection line and adjacent to the second interconnection line in the first direction, wherein a width of the first blocking pattern in the first direction is different from a width of the second blocking pattern in the first direction.

Abstract: Methods of wordline separation in semiconductor devices (e.g., 3D-NAND) are described. A metal film is deposited in the wordlines and on the surface of a stack of spaced oxide layers. The metal film is removed by high temperature oxidation and etching of the oxide or low temperature atomic layer etching by oxidizing the surface and etching the oxide in a monolayer fashion. After removal of the metal overburden, the wordlines are filled with the metal film.

Abstract: A method includes forming a first insulating layer having one or more vias formed in at least a portion of the first insulating layer. The vias are filled with a first metallic material. A cap layer is deposited on a top surface of the first insulating layer and a top surface of the one or more vias and a second insulating layer is deposited on a top surface of the cap layer. One or more openings are formed in the second insulating layer and the cap layer. A self-assembled monolayer is formed on an exposed top surface of the first metallic material in the one or more vias. A barrier layer is formed on at least the exposed surface of the one or more openings. The self-assembled monolayer is removed and the one or more openings are filled with a second metallic material.

Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.

Abstract: A method for manufacturing a photoelectric converter includes a first step of preparing a semiconductor substrate including a metal oxide semiconductor (MOS) transistor, a second step of forming a plurality of interlayer insulating films above the semiconductor substrate, and a third step of forming a photoelectric conversion portion above the semiconductor substrate. The second step includes a step of forming a first film containing hydrogen. The third step includes a step of forming a first electrode, a step of forming a photoelectric conversion film, and a step of forming a second electrode. The method includes a step of performing heat treatment between the step of forming the first film and the step of forming the photoelectric conversion film.

Abstract: A process of depositing a silicon nitride (SiN) film on a nitride semiconductor layer is disclosed. The process includes steps of: (a) loading an epitaxial substrate including the nitride semiconductor layer into a reaction furnace at a first temperature and converting an atmosphere in the furnace into nitrogen (N2); (b) raising the temperature in the furnace to a second temperature while keeping pressure in the furnace at a first pressure higher than 30 kPa; (c) converting the atmosphere in the furnace to ammonia (NH3) at the second temperature; and (d) beginning the deposition by supplying SiH2Cl2 as a source gas for silicon (Si) at a second pressure lower than 100 Pa. A feature of the process is that a time span from when the temperature in the furnace reaches the critical temperature to the supply of SiH2Cl2 is shorter than 20 minutes, where the first pressure becomes the equilibrium pressure at the critical temperature.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: Described are semiconductor devices and methods of making semiconductor devices with a barrier layer comprising cobalt and manganese nitride. Also described are semiconductor devices and methods of making same with a barrier layer comprising CoMn(N) and, optionally, an adhesion layer.

Abstract: A photodetector includes: a substrate having a first doping type; a first semiconductor region having a second doping type, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region having the first doping type, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.

Abstract: Methods of wordline separation in semiconductor devices (e.g., 3D-NAND) are described. A metal film is deposited in the wordlines and on the surface of a stack of spaced oxide layers. The metal film is removed by high temperature oxidation and etching of the oxide or low temperature atomic layer etching by oxidizing the surface and etching the oxide in a monolayer fashion. After removal of the metal overburden, the wordlines are filled with the metal film.

Abstract: Methods and apparatus to form fully self-aligned vias are described. Portions of first conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed portions of the first conductive lines and pillars are formed from the first metal film. A second insulating layer is deposited around the pillars. The pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.

Abstract: Methods and apparatus to form fully self-aligned vias are described. A first metal film is formed in the recessed first conductive lines and on the first insulating layer of a substrate comprising alternating conductive lines and a first insulating layer. Pillars and a sheet are formed from the first metal film. Some of the pillars and a portion of the sheet are selectively removed and a second insulating layer is deposited around the remaining pillars and sheet. The remaining pillars and sheet are removed to form vias and a trench in the second insulating layer. A third insulating layer is deposited in the vias and trench and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer.

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Abstract: Described are semiconductor devices and methods of making semiconductor devices with a barrier layer comprising cobalt and manganese nitride. Also described are semiconductor devices and methods of making same with a barrier layer comprising CoMn(N) and, optionally, an adhesion layer.

Abstract: In a Cu wiring manufacturing method for manufacturing Cu wiring that fills a recess formed in a predetermined pattern on a surface of an interlayer insulating film of a substrate, a MnOx film that becomes a self-formed barrier film by reaction with the interlayer insulating film is formed at least on a surface of the recess by ALD. A CuOx film that becomes a liner film is formed on a surface of the MnOx film by CVD or ALD. An annealing process is performed on the substrate on which the CuOx film is formed and the CuOx film is reduced to a Cu film by oxidation-reduction reaction between the MnOx film and the CuOx film. A Cu-based film is formed on the Cu film obtained by reducing the CuOx film by PVD to fill the Cu-based film in the recess.

Abstract: A method of forming a hard mask includes depositing step for depositing a titanium nitride film on a surface of a to-be-processed object; adsorbing step for adsorbing oxygen-containing molecules onto a surface of the titanium nitride film; and heating step for heating the titanium nitride film to a predetermined temperature.

Abstract: Recrystallization and grain growth of an interconnect metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 600° C., for example, for short anneal times of five to 180 minutes by forming a metal stress locking layer on the interconnect metal before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the interconnect metal by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing or wet etching leaving the metal interconnect with low stress and improved grain size and texture. Annealing can be done in a forming gas or nitrogen gas atmosphere.

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ALD) layer on the conductive region and the opening sidewalls; a second ALD layer on a portion of the first ALD layer, and a third ALD layer within the opening and on the first ALD layer. Other embodiments are described herein.

Abstract: One innovation includes an IR sensor having an array of sensor pixels to convert light into current, each sensor pixel of the array including a photodetector region, a lens configured to focus light into the photodetector region, the lens adjacent to the photodetector region so light propagates through the lens and into the photodetector region, and a substrate disposed with photodetector region between the substrate and the lens, the substrate having one or more transistors formed therein. The sensor also includes reflective structures positioned between at least a portion of the substrate and at least a portion of the photodetector region and such that at least a portion of the photodetector region is between the one or more reflective structures and the lens, the one or more reflective structures configured to reflect the light that has passed through at least a portion of the photodetector region into the photodetector region.

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.

Abstract: A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/MnN on sidewalls and a bottom surface of the via; and filling the via with metal.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.

Abstract: A thin film that has a predetermined composition and containing predetermined elements is formed on a substrate by performing a cycle of steps a predetermined number of times, said cycle comprising: a step wherein a first layer containing the predetermined elements, nitrogen and carbon is formed on the substrate by alternately performing, a predetermined number of times, a process of supplying a first source gas containing a predetermined element and a halogen group to the substrate and a process of supplying a second source gas containing a predetermined element and an amino group to the substrate; a step wherein a second layer is formed by modifying the first layer by supplying an amine-based source gas to the substrate; and a step wherein a third layer is formed by modifying the second layer by supplying a reaction gas that is different from the source gases to the substrate.

Abstract: The invention relates to a process for producing multi-layer bodies which carry at least one metal layer. The invention further relates to multi-layer products having at least three layers, comprising a substrate layer made of a substrate and containing special copolycarbonates, a metal layer and at least one additional layer.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a method in which a selection is made for a first major constituent, a second major constituent and a minor constituent for forming a desired material. The method can include mixing the first major constituent, the second major constituent and the minor constituent in a single mixing step to provide a mixture of constituents. The method can include drying the mixture of constituents to provide a dried mixture of constituents and calcining the dried mixture of constituents to provide a calcinated mixture of constituents. The method can include processing the calcinated mixture of constituents to provide a powder of constituents. Other embodiments are disclosed.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: A method is provided for forming an interconnect structure for use in semiconductor devices. The method starts with forming a low-k bulk dielectric layer on a substrate and then forming a trench in the low-k bulk dielectric layer. A liner layer is formed on the low-k bulk dielectric layer being deposited conformally to the trench. A copper layer is formed on the liner layer filling the trench. Portions of the copper layer and liner layer are removed to form an upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer. A metal containing dielectric layer is formed on the upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer.

Abstract: A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.