Contacting Multiple Semiconductive Regions (i.e., Interconnects) Patents (Class 438/618)
  • Patent number: 11140785
    Abstract: A flexible printed circuit board includes a base layer and a pattern line. At least one communication hole penetrating opposite surfaces of the base layer. The pattern line includes two conductive circuit layers formed on the opposite surfaces of the base layer. At least one conductive pole are formed in the at least one communication hole and electrically connects the two conductive circuit layers. A gap being is formed between the conductive pole and the base layer.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: October 5, 2021
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Xian-Qin Hu, Cheng-Jia Li
  • Patent number: 11131933
    Abstract: A metal resist cleaning liquid including a solvent and formic acid.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: September 28, 2021
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Tomoya Kumagai, Takahiro Akiyoshi
  • Patent number: 11094613
    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a semiconductor substrate, a plurality of interconnecting layers, a first connector, and a second connector. The semiconductor substrate includes a plurality of semiconductor devices therein. The interconnecting layers are disposed over the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed over the plurality of interconnecting layers and extends to be in contact with a first level of the plurality of interconnecting layers. The second connector is disposed over the plurality of interconnecting layers and substantially leveled with the first connector.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Hsien-Wei Chen, Ming-Fa Chen, Sen-Bor Jan
  • Patent number: 11088076
    Abstract: A semiconductor die includes at least one first semiconductor device located on a first substrate, a first pad-level dielectric layer which is a diffusion barrier overlying the at least one first semiconductor device, and first bonding structures including a respective first metallic bonding pad embedded in the first pad-level dielectric layer. Each of the first bonding structures includes a metallic fill material portion having a horizontal distal surface that is located within a horizontal plane including a horizontal distal surface of the first pad-level dielectric layer, and a metallic liner laterally surrounding the metallic fill material portion and vertically spaced from the horizontal plane by a vertical recess distance.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 10, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Teruo Okina
  • Patent number: 11056445
    Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Wen Lee, Hsien-Wen Liu, Shin-Puu Jeng
  • Patent number: 11056387
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first substrate; forming a semiconductor structure having a first conductive contact over a front side of the first substrate; and forming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to a second end of the first conductive contact. The 3D integrated wiring structure can include a first substrate; a dielectric layer in the first substrate; a semiconductor structure over the front side of the first substrate, having a first conductive contact; and a second conductive contact at the backside of the first substrate, and the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: July 6, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu
  • Patent number: 10888856
    Abstract: A honeycomb structure including: a pillar-shaped honeycomb structure portion having an outer peripheral wall and partition walls disposed on an inner side of the outer peripheral wall and defining a plurality of cells extending from one end face to another end face to form flow paths; and at least an electrode portion disposed on an outer surface of the outer peripheral wall of the pillar-shaped honeycomb structure portion, wherein the pillar-shaped honeycomb structure portion is formed of ceramics containing either or both of Si and SiC, the electrode portion contains either or both of a metal and a metal compound in addition to an oxide, and a volume ratio of the oxide on an inner peripheral side of the electrode portion is higher than a volume ratio of the oxide on an outer peripheral side of the electrode portion.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: January 12, 2021
    Assignee: NGK Insulators, Ltd.
    Inventors: Takefumi Kimata, Takahiro Tomita
  • Patent number: 10892338
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: January 12, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Jae Gon Lee
  • Patent number: 10886173
    Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: January 5, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Robert Clark, Kandabara Tapily, Kai-Hung Yu
  • Patent number: 10872861
    Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC. KAOHSIUNG, TAIWAN
    Inventors: Yong-Da Chiu, Shiu-Chih Wang, Shang-Kun Huang, Ying-Ta Chiu, Shin-Luh Tarng, Chih-Pin Hung
  • Patent number: 10854474
    Abstract: Described herein is a technology or a method for pre-fabricating pre-cut plating lines on a lead frame with use of a pre-cut etchback process to minimize burrs during a semiconductor package singulation process. A package includes: a chip, and a lead frame that mounts the chip. The lead frame further includes pre-fabricated pre-cut plating lines that are etched back on the lead frame to form an opening slot on a periphery of the lead frame. The opening slot allows a saw blade to cut through a prepreg material, without touching or cutting a conductive material of the lead frame.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erma Gallenero Gardose, Liya Flores Aquino
  • Patent number: 10818727
    Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoungsu Son, Seung Pil Ko, Jung Hyuk Lee, Shinhee Han, Gwan-Hyeob Koh, Yoonjong Song
  • Patent number: 10804274
    Abstract: A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Zheng Xu, Dexin Kong, Kangguo Cheng
  • Patent number: 10797161
    Abstract: Methods for forming semiconductor structures are provided. The method includes forming a gate structure over a substrate and forming a source/drain structure adjacent to the gate structure. The method further includes forming a mask structure over the gate structure and forming a contact over the source/drain structure. The method further includes selectively forming a metal-containing layer over a top surface of the contact and forming a dielectric layer over the substrate and covering the gate structure and the contact. The method further includes forming a trench through the dielectric layer and the metal-containing layer to expose the top surface of the contact and forming a conductive structure in the trench.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal A. Khaderbad, Sung-Li Wang, Yasutoshi Okuno
  • Patent number: 10790287
    Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 29, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sung-Kwan Kang, Gill Yong Lee, Sang Ho Yu, Shih Chung Chen, Jeffrey W. Anthis
  • Patent number: 10784201
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Bernhard Sell, Oleg Golonzka
  • Patent number: 10784152
    Abstract: A manufacturing method of a semiconductor device is disclosed, including: providing a first wafer and a second wafer that are bonded, a back surface of the first substrate of the first wafer is provided with a passivation layer; performing a photolithography and etching process to form a first opening; forming a hard mask layer, the hard mask layer covers at least a sidewall surface of the first opening; performing an etching process to form a second opening; performing a photolithography and etching process to form a third opening; and forming an interconnection layer. A back surface of a first substrate is provided with a passivation layer, after a first opening is formed, a hard mask layer is formed on a sidewall surface of the first opening, and a maskless etching process is performed to form a second opening, thereby simplifying the process, eliminating one photomask and reducing the production cost.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 22, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Heng Liu
  • Patent number: 10763306
    Abstract: A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: September 1, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Dai-Ying Lee, Erh-Kun Lai
  • Patent number: 10741454
    Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Guo, Ekmini A. De Silva, Nicolas Loubet, Indira Seshadri, Nelson Felix
  • Patent number: 10732501
    Abstract: The present application relates to a method for permanently repairing defects of absent material of a photolithographic mask, comprising the following steps: (a) providing at least one carbon-containing precursor gas and at least one oxidizing agent at a location to be repaired of the photolithographic mask; (b) initiating a reaction of the at least one carbon-containing precursor gas with the aid of at least one energy source at the location of absent material in order to deposit material at the location of absent material, wherein the deposited material comprises at least one reaction product of the reacted at least one carbon-containing precursor gas; and (c) controlling a gas volumetric flow rate of the at least one oxidizing agent in order to minimize a carbon proportion of the deposited material.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Jens Oster, Kinga Kornilov, Tristan Bret, Horst Schneider, Thorsten Hofmann
  • Patent number: 10727165
    Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventors: Paul S. Ho, Tengfei Jiang
  • Patent number: 10727124
    Abstract: A method for manufacturing a semiconductor device includes forming a conductive via extending vertically from a conductive layer, and depositing a first dielectric layer on the conductive layer and on lateral sides the conductive via. In the method, the conductive via is recessed with respect to a top surface of the first dielectric layer. An etch stop layer is deposited on the top surface of the first dielectric layer and on a top surface of the conductive via, and a second dielectric layer is deposited on the etch stop layer. The method also includes removing portions of the etch stop layer and the second dielectric layer to create a plurality of trenches spaced apart from each other. A trench of the plurality of trenches is formed over and exposes at least part of the conductive via, and a conductive material is deposited in the plurality of trenches.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Benjamin D. Briggs
  • Patent number: 10727121
    Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 28, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Robert L. Bruce, Cyril Cabral, Jr., Gregory M. Fritz, Eric A. Joseph, Michael F. Lofaro, Hiroyuki Miyazoe, Kenneth P. Rodbell, Ghavam Shahidi
  • Patent number: 10720359
    Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via, and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Tobias Herzig
  • Patent number: 10720391
    Abstract: A method of forming a buried local interconnect is disclosed including, among other things, forming a first sacrificial layer embedded between a first semiconductor layer and a second semiconductor layer, forming a plurality of fin structures above the second semiconductor layer, forming a mask layer having an opening positioned between an adjacent pair of the fin structures, removing a portion of the second semiconductor layer exposed by the opening to expose the first sacrificial layer and define a first cavity in the second semiconductor layer, removing portions of the first sacrificial layer positioned between the first semiconductor layer and the second semiconductor layer to form lateral cavity extensions of the first cavity, forming a first liner layer in the first cavity, and forming a conductive interconnect in the first cavity over the first liner layer.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bipul C. Paul, Lars W. Liebmann, Ruilong Xie
  • Patent number: 10692727
    Abstract: A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurpreet Lugani, Kyle B. Campbell, Mario J. Di Cino, Aaron W. Freese, Alex Kogan, Kevin R. Shea
  • Patent number: 10684247
    Abstract: Aspects of a biosensor platform system and method are described. In one embodiment, the biosensor platform system includes a fluidic system and tunneling biosensor interface coupled to the fluidic system. The tunneling biosensor interface may include a transducing electrode array having at least one dielectric thin film deposited on an electrode array. The biosensor platform system may further include processing logic operatively coupled to the transducing electrode array. In operation, the application of an electromagnetic field at an interface between an electrode and an electrolyte in the system, for example, may result in the transfer of charge across the interface. The transfer of charge is, in turn, characterized by electromagnetic field-mediated tunneling of electrons that may be assisted by exchange of energy with thermal vibrations at the interface. Various analytes, for example, and other compositions can be identified by analysis of the transfer of charge.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 16, 2020
    Assignee: THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIO
    Inventor: Chaitanya Gupta
  • Patent number: 10685875
    Abstract: A semiconductor device includes a first semiconductor substrate, a first insulating film provided at the first semiconductor substrate and including a first recess portion on a surface portion thereof, a first metal film provided at the first recess portion and having a first surface exposed from the first insulating film, a second semiconductor substrate, a second insulating film provided at the second semiconductor substrate and including a second recess portion on a surface portion thereof, a second metal film provided at the second recess portion and having a second surface exposed from the second insulating film, first anti-diffusion films, and second anti-diffusion films provided at outer circumferential portions of the first anti-diffusion films. The second surface is joined to the first surface. The first anti-diffusion films are provided at the first recess portion and the second recess portion and cover the first metal film and the second metal film.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: June 16, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masaaki Hatano
  • Patent number: 10679941
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu
  • Patent number: 10672649
    Abstract: Advanced dual damascene interconnects have been provided in which a metallic seed liner composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located on sidewall surfaces and a bottom wall of a first metallic structure that is present in a via portion of a combined via/line opening that is present in an interconnect dielectric material layer. The first metallic structure is composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity. In some embodiments, a second metal structure is present on a topmost surface of the first metallic structure. The second metallic structure is composed of an electrically conductive metal or metal alloy that differs from the electrically conductive metal or metal alloy of the first metallic structure.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theo Standaert
  • Patent number: 10655991
    Abstract: In order to improve the characteristic precision of a sensor, an electronic circuit board on which a detection unit that measures a physical quantity is mounted is integrally formed together with a housing so as to reduce mounting variability. This physical-quantity detection device 300 is characterized by having a circuit board 400 and a housing 302 that accommodates said circuit board 400, wherein the circuit board 400 is provided with one or more detection units 602 that detect physical quantities of a gas being measured 30 that passes through a main channel 124, the circuit board 400 is also provided with a circuit unit that performs a computation on the physical quantity detected by each detection unit 602, the housing 302 is formed from a molded resin, and the circuit board 400 is integrally formed together with the housing 302.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 19, 2020
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Takayuki Yogo, Hiroaki Hoshika, Takahiro Miki
  • Patent number: 10651087
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first substrate; forming a semiconductor structure having a first conductive contact over a front side of the first substrate; and forming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to a second end of the first conductive contact. The 3D integrated wiring structure can include a first substrate; a dielectric layer in the first substrate; a semiconductor structure over the front side of the first substrate, having a first conductive contact; and a second conductive contact at the backside of the first substrate, and the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu
  • Patent number: 10636751
    Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 28, 2020
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE & TECHNOLOGY
    Inventors: Yohei Hori, Yongxun Liu, Shinichi Ouchi, Tetsuji Yasuda, Meishoku Masahara, Toshifumi Irisawa, Kazuhiko Endo, Hiroyuki Ota, Tatsuro Maeda, Hanpei Koike, Yasuhiro Ogasahara, Toshihiro Katashita, Koichi Fukuda
  • Patent number: 10629721
    Abstract: A source/drain contact includes a first portion arranged on a substrate and extending between a first gate and a second gate; a second portion arranged on the first portion and extending over the first gate and the second gate, the second portion including a partially recessed liner and a metal disposed on the partially recessed liner, and the partially recessed liner arranged on an endwall of the second portion and in contact with the first portion; and an oxide disposed around the second portion and on the first gate and the second gate.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty
  • Patent number: 10622309
    Abstract: The present disclosure relates to a transmission line structure embedded in a back-end-of-line (BEOL) body that has a cavity. The transmission line structure includes a signal transmission line, a ground plane and a shielding line. The signal transmission line and the first shielding line are formed on a same metallization level, and the ground plane is formed underneath and electrically connected to the first shielding line. A side surface of the signal transmission line and a side surface of the first shielding line, which faces the side surface of the signal transmission line, are exposed to the cavity of the BEOL body, and not covered by any high resistivity conductive coating.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 14, 2020
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Dirk Robert Walter Leipold, Julio C. Costa, Baker Scott, Danny W. Chang
  • Patent number: 10615053
    Abstract: Described herein is a technology or a method for pre-fabricating pre-cut plating lines on a lead frame with use of a pre-cut etchback process to minimize burrs during a semiconductor package singulation process. A package includes: a chip, and a lead frame that mounts the chip. The lead frame further includes pre-fabricated pre-cut plating lines that are etched back on the lead frame to form an opening slot on a periphery of the lead frame. The opening slot allows a saw blade to cut through a prepreg material, without touching or cutting a conductive material of the lead frame.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erma Gallenero Gardose, Liya Flores Aquino
  • Patent number: 10607885
    Abstract: Techniques and mechanisms for providing electrical insulation of a through-substrate interconnect (TI). In an embodiment, the TI extends between a first side of the substrate and a second side of the substrate opposite the first side. The substrate has formed therein a conductive shell structure that extends at least partially around a periphery of the TI. A first dielectric liner structure is disposed between the conductive shell structure and a bulk material of the substrate. A second dielectric liner structure is disposed between the conductive shell structure and the TI. In another embodiment, a voltage of the conductive shell structure is allowed to float while the TI exchanges a signal or a supply voltage.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: March 31, 2020
    Assignee: INTEL CORPORATION
    Inventors: Tanay Karnik, William Wahby
  • Patent number: 10607884
    Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Oleg Golonzka, Swaminathan Sivakumar, Charles H. Wallace, Tahir Ghani
  • Patent number: 10599244
    Abstract: According to one embodiment, a display device includes a display panel including a display area and a non-display area including a first area and a second area. The display panel includes a first substrate, a second substrate including a contact hole crossing a borderline, a protection layer provided over the display area and the first area, and a connecting material. An outer edge of the protection layer includes one first outer edge located on the borderline, another first outer edge located on the borderline opposed to the one first outer edge across the contact hole, and a second outer edge provided in the first area, connected to an end of the one first outer edge and extending along the contact hole.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Japan Display Inc.
    Inventors: Koichi Miyasaka, Yoshikatsu Imazeki, Yoichi Kamijo, Shuichi Osawa, Yoshihiro Watanabe
  • Patent number: 10580691
    Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: March 3, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Kaoru Maekawa, Jeffrey Smith, Nicholas Joy, Gerrit J. Leusink, Kai-Hung Yu
  • Patent number: 10505045
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure includes a gate electrode layer formed over the gate dielectric later and a gate contact structure formed over the gate electrode layer. The gate contact structure includes a first conductive layer formed over the gate electrode layer, a barrier layer formed over the first conductive layer and a second conductive layer over the barrier layer. The second conductive layer is electrically connected to the gate electrode layer by the first conductive layer.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsun Wang, Kuo-Yi Chao, Rueijer Lin, Chen-Yuan Kao, Mei-Yun Wang
  • Patent number: 10455707
    Abstract: Described herein are printed circuit boards (PCBs), PCB assemblies, and methods of manufacture thereof, which allow free placement of electrical components. The PCBs may have electrical pads that may couple to components through via-based connections and without the use of solder. The electrical components may be physically attached to the PCBs through tight fitting, lamination, and/or the use of adhesives. The distance between adjacent vias may be reduced, as accidental short-circuit risks due to solder bridging and similar effects are mitigated when the soldering process is bypassed. The PCB design and component placement may be flexible as to allow the use of electrical components with custom shape and/or customized terminal placement.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: October 22, 2019
    Assignee: APPLE INC.
    Inventors: Kenneth Leland Kiplinger, Mark J. Beesley, Shawn Xavier Arnold, Shyam Harindralal Ratnayake, Meng Chi Lee
  • Patent number: 10453746
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
  • Patent number: 10440836
    Abstract: Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 8, 2019
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 10359369
    Abstract: A test structure is presented for use in metrology measurements of a sample pattern. The test structure comprises a main pattern, and one or more auxiliary patterns. The main pattern is formed by a plurality of main features extending along a first longitudinal axis and being spaced from one another along a second lateral axis. The one or more auxiliary patterns are formed by a plurality of auxiliary features associated with at least some of the main features such that a dimension of the auxiliary feature is in a predetermined relation with a dimension of the respective main feature. This provides that a change in a dimension of the auxiliary feature from a nominal value affects a change in non-zero order diffraction response from the test structure in a predetermined optical measurement scheme, and this change is indicative of a deviation in one or more parameters of the main pattern from nominal value thereof.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: July 23, 2019
    Assignee: NOVA MEASURING INSTRUMENTS LTD.
    Inventors: Gilad Barak, Oded Cohen
  • Patent number: 10361090
    Abstract: A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Kimin Jun, Patrick Morrow, Donald Nelson
  • Patent number: 10354975
    Abstract: An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: July 16, 2019
    Assignee: Raytheon Company
    Inventors: Edward R. Soares, John J. Drab
  • Patent number: 10347832
    Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 9, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yoshihisa Kagawa
  • Patent number: 10312188
    Abstract: An integrated circuit (IC) structure including an interconnect structure is disclosed. The interconnect structure may include a first etch stop layer (ESL) positioned between an initial via layer and a first metal layer of the interconnect structure. The ESL may be positioned adjacent to and surround a metal wire in the first metal layer. A method of forming an interconnect structure is also disclosed. The method may include forming an opening in a first dielectric layer above a substrate; forming a sacrificial semiconductor material in the opening; forming an ESL on the first dielectric layer and sacrificial semiconductor material; forming a second dielectric layer on the ESL; forming an opening in the second dielectric layer to expose a portion of the ESL; removing the exposed portion of the ESL; removing the sacrificial semiconductor material; and forming a conductive material in the openings to form an interconnect structure.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi P. Srivastava, Sunil K. Singh
  • Patent number: 10297532
    Abstract: A stacked interconnect structure includes a first conductive layer, a second conductive layer, and a first dielectric layer disposed between the first and second conductive layers and having an air gap in a portion of the first dielectric layer that separates the first and second conductive layers. A second dielectric layer is parallel to the first conductive layer, a third dielectric layer overlays a portion of the second dielectric layer and contacts two opposing surfaces of the second conductive layer. A first via extends into the air gap of the first dielectric layer, wherein the second conductive layer is separated from the first via by a portion of the third dielectric layer that extends from a given surface of the third dielectric layer to the second dielectric layer, and a second via that extends from the given surface of the third dielectric layer to the second conductive layer.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 21, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: Thomas J. Knight