Contacting Multiple Semiconductive Regions (i.e., Interconnects) Patents (Class 438/618)
  • Patent number: 10692727
    Abstract: A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurpreet Lugani, Kyle B. Campbell, Mario J. Di Cino, Aaron W. Freese, Alex Kogan, Kevin R. Shea
  • Patent number: 10684247
    Abstract: Aspects of a biosensor platform system and method are described. In one embodiment, the biosensor platform system includes a fluidic system and tunneling biosensor interface coupled to the fluidic system. The tunneling biosensor interface may include a transducing electrode array having at least one dielectric thin film deposited on an electrode array. The biosensor platform system may further include processing logic operatively coupled to the transducing electrode array. In operation, the application of an electromagnetic field at an interface between an electrode and an electrolyte in the system, for example, may result in the transfer of charge across the interface. The transfer of charge is, in turn, characterized by electromagnetic field-mediated tunneling of electrons that may be assisted by exchange of energy with thermal vibrations at the interface. Various analytes, for example, and other compositions can be identified by analysis of the transfer of charge.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 16, 2020
    Assignee: THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIO
    Inventor: Chaitanya Gupta
  • Patent number: 10685875
    Abstract: A semiconductor device includes a first semiconductor substrate, a first insulating film provided at the first semiconductor substrate and including a first recess portion on a surface portion thereof, a first metal film provided at the first recess portion and having a first surface exposed from the first insulating film, a second semiconductor substrate, a second insulating film provided at the second semiconductor substrate and including a second recess portion on a surface portion thereof, a second metal film provided at the second recess portion and having a second surface exposed from the second insulating film, first anti-diffusion films, and second anti-diffusion films provided at outer circumferential portions of the first anti-diffusion films. The second surface is joined to the first surface. The first anti-diffusion films are provided at the first recess portion and the second recess portion and cover the first metal film and the second metal film.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: June 16, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masaaki Hatano
  • Patent number: 10679941
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu
  • Patent number: 10672649
    Abstract: Advanced dual damascene interconnects have been provided in which a metallic seed liner composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located on sidewall surfaces and a bottom wall of a first metallic structure that is present in a via portion of a combined via/line opening that is present in an interconnect dielectric material layer. The first metallic structure is composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity. In some embodiments, a second metal structure is present on a topmost surface of the first metallic structure. The second metallic structure is composed of an electrically conductive metal or metal alloy that differs from the electrically conductive metal or metal alloy of the first metallic structure.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theo Standaert
  • Patent number: 10655991
    Abstract: In order to improve the characteristic precision of a sensor, an electronic circuit board on which a detection unit that measures a physical quantity is mounted is integrally formed together with a housing so as to reduce mounting variability. This physical-quantity detection device 300 is characterized by having a circuit board 400 and a housing 302 that accommodates said circuit board 400, wherein the circuit board 400 is provided with one or more detection units 602 that detect physical quantities of a gas being measured 30 that passes through a main channel 124, the circuit board 400 is also provided with a circuit unit that performs a computation on the physical quantity detected by each detection unit 602, the housing 302 is formed from a molded resin, and the circuit board 400 is integrally formed together with the housing 302.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 19, 2020
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Takayuki Yogo, Hiroaki Hoshika, Takahiro Miki
  • Patent number: 10651087
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first substrate; forming a semiconductor structure having a first conductive contact over a front side of the first substrate; and forming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to a second end of the first conductive contact. The 3D integrated wiring structure can include a first substrate; a dielectric layer in the first substrate; a semiconductor structure over the front side of the first substrate, having a first conductive contact; and a second conductive contact at the backside of the first substrate, and the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu
  • Patent number: 10636751
    Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 28, 2020
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE & TECHNOLOGY
    Inventors: Yohei Hori, Yongxun Liu, Shinichi Ouchi, Tetsuji Yasuda, Meishoku Masahara, Toshifumi Irisawa, Kazuhiko Endo, Hiroyuki Ota, Tatsuro Maeda, Hanpei Koike, Yasuhiro Ogasahara, Toshihiro Katashita, Koichi Fukuda
  • Patent number: 10629721
    Abstract: A source/drain contact includes a first portion arranged on a substrate and extending between a first gate and a second gate; a second portion arranged on the first portion and extending over the first gate and the second gate, the second portion including a partially recessed liner and a metal disposed on the partially recessed liner, and the partially recessed liner arranged on an endwall of the second portion and in contact with the first portion; and an oxide disposed around the second portion and on the first gate and the second gate.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty
  • Patent number: 10622309
    Abstract: The present disclosure relates to a transmission line structure embedded in a back-end-of-line (BEOL) body that has a cavity. The transmission line structure includes a signal transmission line, a ground plane and a shielding line. The signal transmission line and the first shielding line are formed on a same metallization level, and the ground plane is formed underneath and electrically connected to the first shielding line. A side surface of the signal transmission line and a side surface of the first shielding line, which faces the side surface of the signal transmission line, are exposed to the cavity of the BEOL body, and not covered by any high resistivity conductive coating.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 14, 2020
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Dirk Robert Walter Leipold, Julio C. Costa, Baker Scott, Danny W. Chang
  • Patent number: 10615053
    Abstract: Described herein is a technology or a method for pre-fabricating pre-cut plating lines on a lead frame with use of a pre-cut etchback process to minimize burrs during a semiconductor package singulation process. A package includes: a chip, and a lead frame that mounts the chip. The lead frame further includes pre-fabricated pre-cut plating lines that are etched back on the lead frame to form an opening slot on a periphery of the lead frame. The opening slot allows a saw blade to cut through a prepreg material, without touching or cutting a conductive material of the lead frame.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erma Gallenero Gardose, Liya Flores Aquino
  • Patent number: 10607885
    Abstract: Techniques and mechanisms for providing electrical insulation of a through-substrate interconnect (TI). In an embodiment, the TI extends between a first side of the substrate and a second side of the substrate opposite the first side. The substrate has formed therein a conductive shell structure that extends at least partially around a periphery of the TI. A first dielectric liner structure is disposed between the conductive shell structure and a bulk material of the substrate. A second dielectric liner structure is disposed between the conductive shell structure and the TI. In another embodiment, a voltage of the conductive shell structure is allowed to float while the TI exchanges a signal or a supply voltage.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: March 31, 2020
    Assignee: INTEL CORPORATION
    Inventors: Tanay Karnik, William Wahby
  • Patent number: 10607884
    Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Oleg Golonzka, Swaminathan Sivakumar, Charles H. Wallace, Tahir Ghani
  • Patent number: 10599244
    Abstract: According to one embodiment, a display device includes a display panel including a display area and a non-display area including a first area and a second area. The display panel includes a first substrate, a second substrate including a contact hole crossing a borderline, a protection layer provided over the display area and the first area, and a connecting material. An outer edge of the protection layer includes one first outer edge located on the borderline, another first outer edge located on the borderline opposed to the one first outer edge across the contact hole, and a second outer edge provided in the first area, connected to an end of the one first outer edge and extending along the contact hole.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Japan Display Inc.
    Inventors: Koichi Miyasaka, Yoshikatsu Imazeki, Yoichi Kamijo, Shuichi Osawa, Yoshihiro Watanabe
  • Patent number: 10580691
    Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: March 3, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Kaoru Maekawa, Jeffrey Smith, Nicholas Joy, Gerrit J. Leusink, Kai-Hung Yu
  • Patent number: 10505045
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure includes a gate electrode layer formed over the gate dielectric later and a gate contact structure formed over the gate electrode layer. The gate contact structure includes a first conductive layer formed over the gate electrode layer, a barrier layer formed over the first conductive layer and a second conductive layer over the barrier layer. The second conductive layer is electrically connected to the gate electrode layer by the first conductive layer.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsun Wang, Kuo-Yi Chao, Rueijer Lin, Chen-Yuan Kao, Mei-Yun Wang
  • Patent number: 10455707
    Abstract: Described herein are printed circuit boards (PCBs), PCB assemblies, and methods of manufacture thereof, which allow free placement of electrical components. The PCBs may have electrical pads that may couple to components through via-based connections and without the use of solder. The electrical components may be physically attached to the PCBs through tight fitting, lamination, and/or the use of adhesives. The distance between adjacent vias may be reduced, as accidental short-circuit risks due to solder bridging and similar effects are mitigated when the soldering process is bypassed. The PCB design and component placement may be flexible as to allow the use of electrical components with custom shape and/or customized terminal placement.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: October 22, 2019
    Assignee: APPLE INC.
    Inventors: Kenneth Leland Kiplinger, Mark J. Beesley, Shawn Xavier Arnold, Shyam Harindralal Ratnayake, Meng Chi Lee
  • Patent number: 10453746
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
  • Patent number: 10440836
    Abstract: Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 8, 2019
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 10361090
    Abstract: A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Kimin Jun, Patrick Morrow, Donald Nelson
  • Patent number: 10359369
    Abstract: A test structure is presented for use in metrology measurements of a sample pattern. The test structure comprises a main pattern, and one or more auxiliary patterns. The main pattern is formed by a plurality of main features extending along a first longitudinal axis and being spaced from one another along a second lateral axis. The one or more auxiliary patterns are formed by a plurality of auxiliary features associated with at least some of the main features such that a dimension of the auxiliary feature is in a predetermined relation with a dimension of the respective main feature. This provides that a change in a dimension of the auxiliary feature from a nominal value affects a change in non-zero order diffraction response from the test structure in a predetermined optical measurement scheme, and this change is indicative of a deviation in one or more parameters of the main pattern from nominal value thereof.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: July 23, 2019
    Assignee: NOVA MEASURING INSTRUMENTS LTD.
    Inventors: Gilad Barak, Oded Cohen
  • Patent number: 10354975
    Abstract: An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: July 16, 2019
    Assignee: Raytheon Company
    Inventors: Edward R. Soares, John J. Drab
  • Patent number: 10347832
    Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 9, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yoshihisa Kagawa
  • Patent number: 10312188
    Abstract: An integrated circuit (IC) structure including an interconnect structure is disclosed. The interconnect structure may include a first etch stop layer (ESL) positioned between an initial via layer and a first metal layer of the interconnect structure. The ESL may be positioned adjacent to and surround a metal wire in the first metal layer. A method of forming an interconnect structure is also disclosed. The method may include forming an opening in a first dielectric layer above a substrate; forming a sacrificial semiconductor material in the opening; forming an ESL on the first dielectric layer and sacrificial semiconductor material; forming a second dielectric layer on the ESL; forming an opening in the second dielectric layer to expose a portion of the ESL; removing the exposed portion of the ESL; removing the sacrificial semiconductor material; and forming a conductive material in the openings to form an interconnect structure.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi P. Srivastava, Sunil K. Singh
  • Patent number: 10297532
    Abstract: A stacked interconnect structure includes a first conductive layer, a second conductive layer, and a first dielectric layer disposed between the first and second conductive layers and having an air gap in a portion of the first dielectric layer that separates the first and second conductive layers. A second dielectric layer is parallel to the first conductive layer, a third dielectric layer overlays a portion of the second dielectric layer and contacts two opposing surfaces of the second conductive layer. A first via extends into the air gap of the first dielectric layer, wherein the second conductive layer is separated from the first via by a portion of the third dielectric layer that extends from a given surface of the third dielectric layer to the second dielectric layer, and a second via that extends from the given surface of the third dielectric layer to the second conductive layer.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 21, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: Thomas J. Knight
  • Patent number: 10262963
    Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: April 16, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventor: Paul M. Enquist
  • Patent number: 10242911
    Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
  • Patent number: 10224338
    Abstract: A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Soh Yun Siah
  • Patent number: 10224242
    Abstract: Semiconductor devices with low-resistivity metallic interconnect structures are provided. For example, a sacrificial dielectric layer is formed on a substrate, and patterned to form an opening in the sacrificial dielectric layer. The opening is filled with a metallic material to form a metallic interconnect structure, and the sacrificial dielectric layer is removed to expose the metallic interconnect structure. A heat treatment process is applied to the exposed metallic interconnect structure to modulate a microstructure of the metallic material of the metallic interconnect structure from a first microstructure to a second microstructure. A conformal liner layer is selectively deposited on exposed surfaces of the metallic interconnect structure, subsequent to the heat treatment process.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephan A. Cohen
  • Patent number: 10211155
    Abstract: Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 10170450
    Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventors: Eric Beyne, Joeri De Vos, Stefaan Van Huylenbroeck
  • Patent number: 10128182
    Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10121873
    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Teng Liao, Yi-Wei Chiu, Xi-Zong Chen, Chia-Ching Tsai
  • Patent number: 10115586
    Abstract: A method is provided for depositing a planarization layer over features on a substrate using sequential polymerization chemical vapor deposition. According to one embodiment, the method includes providing a substrate containing a plurality of features with gaps between the plurality of features, delivering precursor molecules by gas phase exposure to the substrate, adsorbing the precursor molecules on the substrate to at least substantially fill the gaps with a layer of the adsorbed precursor molecules, and reacting the precursor molecules to form a polymer layer that at least substantially fills the gaps.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: October 30, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Jacques Faguet, Bruce A. Altemus, Kazuya Ichiki
  • Patent number: 10090386
    Abstract: Provided are a graphene-metal bonding structure, a method of manufacturing the graphene-metal bonding structure, and a semiconductor device including the graphene-metal bonding structure. According to example embodiments, a graphene-metal bonding structure includes: a graphene layer; a metal layer on the graphene layer; and an intermediate material layer between the graphene layer and the metal layer. The intermediate material layer forms an edge-contact with the metal layer from boundary portions of a material contained in the intermediate material layer that contact the metal layer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeho Lee, Hyeonjin Shin, Minhyun Lee, Changseok Lee
  • Patent number: 10051736
    Abstract: A printed wiring board includes a conductor layer including a conductor circuit, a resin insulating layer formed on the conductor layer and having a via opening reaching to the conductor circuit of the conductor layer, and a via conductor formed in the via opening of the resin insulating layer such that the via conductor is connecting to the conductor circuit of the conductor layer. The conductor circuit of the conductor layer has a first conductor portion and a second conductor portion integrally formed such that the first conductor portion is connected to the via opening of the resin insulating layer, that the second conductor portion is surrounding the first conductor portion and that the first conductor portion has a thickness which is greater than a thickness of the second conductor portion.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: August 14, 2018
    Assignee: IBIDEN CO., LTD.
    Inventor: Teruyuki Ishihara
  • Patent number: 10043824
    Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor on an insulator (SOI) substrate having a bottom substrate, a buried oxide layer on the bottom substrate, and a semiconductor layer on the buried oxide layer. The semiconductor device also includes a first dielectric layer disposed on the semiconductor layer, a first contact structure extending from a top surface of the first dielectric layer through the semiconductor layer and the buried oxide layer and contacting the bottom substrate, and a first trench extending into the semiconductor layer. A width of the first trench is smaller than a width of the first contact structure. The first dielectric layer seals the first trench at or near the top of the first trench to form a vacuum gap.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 7, 2018
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Chun-Ting Yang, Ho-Chien Chen
  • Patent number: 10035978
    Abstract: The present invention makes it possible to provide a semiconductor element cleaning method that is characterized in that: a hard mask pattern is formed on a substrate that has a low relative permittivity film and at least one of a cobalt, a cobalt alloy, or a tungsten plug; and a cleaning liquid that contains 0.001-20% by mass of an alkali metallic compound, 0.1-30% by mass of quaternary ammonium hydroxide, 0.01-60% by mass of a organic water-soluble solvent, 0.0001-0.1% by mass of hydrogen peroxide, and water is subsequently used on a semiconductor element in which, using the hard mask pattern as a mask, the hard mask, the low relative permittivity film, and a barrier insulating film are dry etched, and dry etch residues are removed.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 31, 2018
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Toshiyuki Oie, Kenji Shimada
  • Patent number: 10032901
    Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: July 24, 2018
    Assignee: Vishay-Siliconix
    Inventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
  • Patent number: 10002785
    Abstract: A semiconductor process for providing a metal layer uses the following steps: A barrier dielectric layer is deposited on a semiconductor layer comprising an exposed metal line. A via layer is formed on top of the barrier dielectric layer comprising at least one via. A non-conformal film is deposited on top of the via layer thereby forming a void in the at least one via, and at least one trench is etched into the non-conformal film thereby opening the void, and creating a dual-damascene layer.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 19, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Justin Hiroki Sato, Andrew Alexander Taylor
  • Patent number: 9996725
    Abstract: A sensor assembly that includes a silicon substrate and a sensor integrally formed on or in its top surface. Bond pads are formed at the substrate top surface and electrically coupled to the sensor. A trench is formed into the top surface, extending toward but not reaching the substrate's bottom surface. Conductive first traces each extend from one of the bond pads and down into the trench. One or more holes are formed into the bottom surface of the substrate and extend toward but do not reach the top surface. The one or more holes terminate at the bottom of the trench in a manner exposing the conductive first traces. Conductive second traces each extend from one of the conductive first traces at the bottom of the trench, along a sidewall of the one or more holes, and along the bottom surface of the silicon substrate.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: June 12, 2018
    Assignee: Optiz, Inc.
    Inventor: Vage Oganesian
  • Patent number: 9984858
    Abstract: Methods of etching and smoothening films by exposing to a halogen-containing plasma and an inert plasma within a bias window in cycles are provided. Methods are suitable for etching and smoothening films of various materials in the semiconductor industry and are also applicable to applications in optics and other industries.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 29, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Keren Jacobs Kanarik, Samantha Tan, Thorsten Lill, Meihua Shen, Yang Pan, Jeffrey Marks, Richard Wise
  • Patent number: 9960129
    Abstract: A method of forming a hybrid bonding structure includes depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive structure, and the etch stop layer contacts the conductive structure. The method further includes depositing a dielectric material over the etch stop layer. The method further includes depositing a first diffusion barrier layer over the dielectric material. The method further includes forming an opening extending through the etch stop layer, the dielectric material and the diffusion barrier layer. The method further includes lining the opening with a second diffusion barrier layer. The method further includes depositing a conductive pad on the second diffusion barrier layer in the opening, wherein a surface of the first diffusion barrier layer is aligned with a surface of the conductive pad.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Szu-Ying Chen, Chen-Jong Wang, Chih-Hui Huang, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9932671
    Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, Patricio E. Romero, Scott B. Clendenning, Grant M. Kloster, Florian Gstrein, Harsono S. Simka, Paul A. Zimmerman, Robert L. Bristol
  • Patent number: 9929017
    Abstract: An etching method according to an embodiment, includes performing etching on a material having tungsten (W) as a main component by using as an etchant a chemical solution having hydrogen peroxide as a main component. The chemical solution contains 12 ppm or more and 100,000 ppm or less of W.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nagisa Takami, Yoshihiro Uozumi
  • Patent number: 9882047
    Abstract: A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9875927
    Abstract: A method for forming patterns for semiconductor device includes following steps. A substrate including a hard mask layer and a sacrificial layer is provided. A plurality of mandrel patterns are formed on the substrate. A spacer is respectively formed on sidewalls of the mandrel patterns. The mandrel patterns are removed to form a plurality of spacer patterns directly formed on the sacrificial layer. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion of the first blocking layers are formed on the substrate. The sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers, and the second blocking layers serving as etching masks to form a patterned hard mask layer on the substrate.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Hao Fu, Home-Been Cheng, Ci-Dong Chu, Tsung-Yin Hsieh
  • Patent number: 9852984
    Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Wei, Sudharshanan Raghunathan
  • Patent number: 9847261
    Abstract: A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: December 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Junli Wang, Chih-Chao Yang
  • Patent number: 9831174
    Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan