Contacting Multiple Semiconductive Regions (i.e., Interconnects) Patents (Class 438/618)
  • Patent number: 10354975
    Abstract: An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: July 16, 2019
    Assignee: Raytheon Company
    Inventors: Edward R. Soares, John J. Drab
  • Patent number: 10347832
    Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 9, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yoshihisa Kagawa
  • Patent number: 10312188
    Abstract: An integrated circuit (IC) structure including an interconnect structure is disclosed. The interconnect structure may include a first etch stop layer (ESL) positioned between an initial via layer and a first metal layer of the interconnect structure. The ESL may be positioned adjacent to and surround a metal wire in the first metal layer. A method of forming an interconnect structure is also disclosed. The method may include forming an opening in a first dielectric layer above a substrate; forming a sacrificial semiconductor material in the opening; forming an ESL on the first dielectric layer and sacrificial semiconductor material; forming a second dielectric layer on the ESL; forming an opening in the second dielectric layer to expose a portion of the ESL; removing the exposed portion of the ESL; removing the sacrificial semiconductor material; and forming a conductive material in the openings to form an interconnect structure.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi P. Srivastava, Sunil K. Singh
  • Patent number: 10297532
    Abstract: A stacked interconnect structure includes a first conductive layer, a second conductive layer, and a first dielectric layer disposed between the first and second conductive layers and having an air gap in a portion of the first dielectric layer that separates the first and second conductive layers. A second dielectric layer is parallel to the first conductive layer, a third dielectric layer overlays a portion of the second dielectric layer and contacts two opposing surfaces of the second conductive layer. A first via extends into the air gap of the first dielectric layer, wherein the second conductive layer is separated from the first via by a portion of the third dielectric layer that extends from a given surface of the third dielectric layer to the second dielectric layer, and a second via that extends from the given surface of the third dielectric layer to the second conductive layer.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 21, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: Thomas J. Knight
  • Patent number: 10262963
    Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: April 16, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventor: Paul M. Enquist
  • Patent number: 10242911
    Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
  • Patent number: 10224242
    Abstract: Semiconductor devices with low-resistivity metallic interconnect structures are provided. For example, a sacrificial dielectric layer is formed on a substrate, and patterned to form an opening in the sacrificial dielectric layer. The opening is filled with a metallic material to form a metallic interconnect structure, and the sacrificial dielectric layer is removed to expose the metallic interconnect structure. A heat treatment process is applied to the exposed metallic interconnect structure to modulate a microstructure of the metallic material of the metallic interconnect structure from a first microstructure to a second microstructure. A conformal liner layer is selectively deposited on exposed surfaces of the metallic interconnect structure, subsequent to the heat treatment process.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephan A. Cohen
  • Patent number: 10224338
    Abstract: A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Soh Yun Siah
  • Patent number: 10211155
    Abstract: Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 10170450
    Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventors: Eric Beyne, Joeri De Vos, Stefaan Van Huylenbroeck
  • Patent number: 10128182
    Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10121873
    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Teng Liao, Yi-Wei Chiu, Xi-Zong Chen, Chia-Ching Tsai
  • Patent number: 10115586
    Abstract: A method is provided for depositing a planarization layer over features on a substrate using sequential polymerization chemical vapor deposition. According to one embodiment, the method includes providing a substrate containing a plurality of features with gaps between the plurality of features, delivering precursor molecules by gas phase exposure to the substrate, adsorbing the precursor molecules on the substrate to at least substantially fill the gaps with a layer of the adsorbed precursor molecules, and reacting the precursor molecules to form a polymer layer that at least substantially fills the gaps.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: October 30, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Jacques Faguet, Bruce A. Altemus, Kazuya Ichiki
  • Patent number: 10090386
    Abstract: Provided are a graphene-metal bonding structure, a method of manufacturing the graphene-metal bonding structure, and a semiconductor device including the graphene-metal bonding structure. According to example embodiments, a graphene-metal bonding structure includes: a graphene layer; a metal layer on the graphene layer; and an intermediate material layer between the graphene layer and the metal layer. The intermediate material layer forms an edge-contact with the metal layer from boundary portions of a material contained in the intermediate material layer that contact the metal layer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeho Lee, Hyeonjin Shin, Minhyun Lee, Changseok Lee
  • Patent number: 10051736
    Abstract: A printed wiring board includes a conductor layer including a conductor circuit, a resin insulating layer formed on the conductor layer and having a via opening reaching to the conductor circuit of the conductor layer, and a via conductor formed in the via opening of the resin insulating layer such that the via conductor is connecting to the conductor circuit of the conductor layer. The conductor circuit of the conductor layer has a first conductor portion and a second conductor portion integrally formed such that the first conductor portion is connected to the via opening of the resin insulating layer, that the second conductor portion is surrounding the first conductor portion and that the first conductor portion has a thickness which is greater than a thickness of the second conductor portion.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: August 14, 2018
    Assignee: IBIDEN CO., LTD.
    Inventor: Teruyuki Ishihara
  • Patent number: 10043824
    Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor on an insulator (SOI) substrate having a bottom substrate, a buried oxide layer on the bottom substrate, and a semiconductor layer on the buried oxide layer. The semiconductor device also includes a first dielectric layer disposed on the semiconductor layer, a first contact structure extending from a top surface of the first dielectric layer through the semiconductor layer and the buried oxide layer and contacting the bottom substrate, and a first trench extending into the semiconductor layer. A width of the first trench is smaller than a width of the first contact structure. The first dielectric layer seals the first trench at or near the top of the first trench to form a vacuum gap.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 7, 2018
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Chun-Ting Yang, Ho-Chien Chen
  • Patent number: 10035978
    Abstract: The present invention makes it possible to provide a semiconductor element cleaning method that is characterized in that: a hard mask pattern is formed on a substrate that has a low relative permittivity film and at least one of a cobalt, a cobalt alloy, or a tungsten plug; and a cleaning liquid that contains 0.001-20% by mass of an alkali metallic compound, 0.1-30% by mass of quaternary ammonium hydroxide, 0.01-60% by mass of a organic water-soluble solvent, 0.0001-0.1% by mass of hydrogen peroxide, and water is subsequently used on a semiconductor element in which, using the hard mask pattern as a mask, the hard mask, the low relative permittivity film, and a barrier insulating film are dry etched, and dry etch residues are removed.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 31, 2018
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Toshiyuki Oie, Kenji Shimada
  • Patent number: 10032901
    Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: July 24, 2018
    Assignee: Vishay-Siliconix
    Inventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
  • Patent number: 10002785
    Abstract: A semiconductor process for providing a metal layer uses the following steps: A barrier dielectric layer is deposited on a semiconductor layer comprising an exposed metal line. A via layer is formed on top of the barrier dielectric layer comprising at least one via. A non-conformal film is deposited on top of the via layer thereby forming a void in the at least one via, and at least one trench is etched into the non-conformal film thereby opening the void, and creating a dual-damascene layer.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 19, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Justin Hiroki Sato, Andrew Alexander Taylor
  • Patent number: 9996725
    Abstract: A sensor assembly that includes a silicon substrate and a sensor integrally formed on or in its top surface. Bond pads are formed at the substrate top surface and electrically coupled to the sensor. A trench is formed into the top surface, extending toward but not reaching the substrate's bottom surface. Conductive first traces each extend from one of the bond pads and down into the trench. One or more holes are formed into the bottom surface of the substrate and extend toward but do not reach the top surface. The one or more holes terminate at the bottom of the trench in a manner exposing the conductive first traces. Conductive second traces each extend from one of the conductive first traces at the bottom of the trench, along a sidewall of the one or more holes, and along the bottom surface of the silicon substrate.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: June 12, 2018
    Assignee: Optiz, Inc.
    Inventor: Vage Oganesian
  • Patent number: 9984858
    Abstract: Methods of etching and smoothening films by exposing to a halogen-containing plasma and an inert plasma within a bias window in cycles are provided. Methods are suitable for etching and smoothening films of various materials in the semiconductor industry and are also applicable to applications in optics and other industries.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 29, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Keren Jacobs Kanarik, Samantha Tan, Thorsten Lill, Meihua Shen, Yang Pan, Jeffrey Marks, Richard Wise
  • Patent number: 9960129
    Abstract: A method of forming a hybrid bonding structure includes depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive structure, and the etch stop layer contacts the conductive structure. The method further includes depositing a dielectric material over the etch stop layer. The method further includes depositing a first diffusion barrier layer over the dielectric material. The method further includes forming an opening extending through the etch stop layer, the dielectric material and the diffusion barrier layer. The method further includes lining the opening with a second diffusion barrier layer. The method further includes depositing a conductive pad on the second diffusion barrier layer in the opening, wherein a surface of the first diffusion barrier layer is aligned with a surface of the conductive pad.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Szu-Ying Chen, Chen-Jong Wang, Chih-Hui Huang, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9932671
    Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, Patricio E. Romero, Scott B. Clendenning, Grant M. Kloster, Florian Gstrein, Harsono S. Simka, Paul A. Zimmerman, Robert L. Bristol
  • Patent number: 9929017
    Abstract: An etching method according to an embodiment, includes performing etching on a material having tungsten (W) as a main component by using as an etchant a chemical solution having hydrogen peroxide as a main component. The chemical solution contains 12 ppm or more and 100,000 ppm or less of W.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nagisa Takami, Yoshihiro Uozumi
  • Patent number: 9882047
    Abstract: A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9875927
    Abstract: A method for forming patterns for semiconductor device includes following steps. A substrate including a hard mask layer and a sacrificial layer is provided. A plurality of mandrel patterns are formed on the substrate. A spacer is respectively formed on sidewalls of the mandrel patterns. The mandrel patterns are removed to form a plurality of spacer patterns directly formed on the sacrificial layer. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion of the first blocking layers are formed on the substrate. The sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers, and the second blocking layers serving as etching masks to form a patterned hard mask layer on the substrate.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Hao Fu, Home-Been Cheng, Ci-Dong Chu, Tsung-Yin Hsieh
  • Patent number: 9852984
    Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Wei, Sudharshanan Raghunathan
  • Patent number: 9847261
    Abstract: A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: December 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Junli Wang, Chih-Chao Yang
  • Patent number: 9831174
    Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
  • Patent number: 9831117
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Tsung-Min Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 9825262
    Abstract: Disclosed is an organic light emitting display apparatus in which an anode electrode, an organic emission layer, a cathode electrode, and an auxiliary electrode connected to the cathode electrode and disposed on the same layer as that of the anode electrode are disposed in an active area of the substrate, a signal pad and a pad electrode connected to the signal pad and covering a top of the signal pad are disposed in a pad area of the substrate, and a top of the pad electrode has lower oxidation rate than the top of the signal pad.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: November 21, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Joon Suk Lee, Se June Kim, So Jung Lee, Jin-Hee Jang, Jong Hyeok Im, Jae Sung Lee
  • Patent number: 9799558
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a sacrificial layer over the first dielectric layer. The method further includes forming an opening in the sacrificial layer and etching the first dielectric layer to form a via hole through the opening. The method further includes forming a conductive structure in the via hole and the opening and removing the sacrificial layer to expose an upper portion of the conductive structure. The method further includes forming a second dielectric layer around the upper portion of the conductive material.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsi-Wen Tien, Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao
  • Patent number: 9793415
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a semiconductor layer, a gate electrode on the semiconductor layer, a first insulating layer between the semiconductor layer and the gate electrode; a second insulating layer on the gate electrode, source and drain electrodes corresponding to both ends of the semiconductor layer and disposed on the second insulating layer, and a doping layer disposed along contact holes of the first and second insulating layers, which expose the both ends of the semiconductor layer, such as, between the both ends of the semiconductor layer and the source and drain electrodes.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 17, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junghyun Kim, Kiwan Ahn
  • Patent number: 9790084
    Abstract: A micromechanical sensor device includes an evaluation circuit formed in a first substrate, and an MEMS structure which is situated in a cavity delimited by a second substrate and a third substrate, the MEMS structure and the second substrate being situated on top of each other, the MEMS structure being functionally connected to the evaluation circuit via a contact area, the contact area between the MEMS structure and the first substrate being situated essentially centrally on the second substrate and essentially centrally on the first substrate and has an essentially punctiform configuration, proceeding radially from the contact area, a clearance being formed between the first substrate and the second substrate.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: October 17, 2017
    Assignee: ROBERT BOSCH GMBH
    Inventors: Arnd Kaelberer, Jochen Reinmuth
  • Patent number: 9786556
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 10, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Weiting Wang, Fumiharu Nakajima, Yoko Yokoyama, Sadatoshi Murakami
  • Patent number: 9768131
    Abstract: A wiring (3) comprising electrical conductors (4, 5, 6, 7) is formed in a dielectric layer (2) on or above a semiconductor substrate (1), an opening is formed in the dielectric layer to uncover a contact pad (8), which is formed by one of the conductors, and a further opening is formed in the dielectric layer to uncover an area of a further conductor (5), separate from the contact pad. The further opening is filled with an electrically conductive material (9), and the dielectric layer is thinned from a side opposite the substrate, so that the electrically conductive material protrudes from the dielectric layer.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: September 19, 2017
    Assignee: AMS AG
    Inventors: Jochen Kraft, Karl Rohracher, Martin Schrems
  • Patent number: 9754906
    Abstract: The present disclosure relates to a package substrate. The package substrate includes a patterned conductive layer and conductive pillars. Each of the conductive pillars includes a first portion and a second portion, where the first portion contacts the patterned conductive layer at one end of the first portion, and the second portion is adjacent to another end of the first portion. A thickness of the first portion is greater than a thickness of the second portion. Side surfaces of the first portion are substantially coplanar to side surfaces of the second portion.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 5, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Chuan Tsai, Chih-Cheng Lee
  • Patent number: 9754859
    Abstract: A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: September 5, 2017
    Assignee: Infineon Technologies AG
    Inventors: Walter Rieger, Franz Hirler, Martin Poelzl, Manfred Kotek
  • Patent number: 9748177
    Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: August 29, 2017
    Assignee: INTEL CORPORATION
    Inventors: Weng Hong Teh, Vinodhkumar Raghunathan
  • Patent number: 9741577
    Abstract: A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Junli Wang, Chih-Chao Yang
  • Patent number: 9728583
    Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: August 8, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Moazzem Hossain, Nicholas Rizzo
  • Patent number: 9728451
    Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: August 8, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chen-Chao Wang, Ying-Te Ou
  • Patent number: 9721883
    Abstract: Integrated circuits and manufacturing methods of the same are disclosed. The integrated circuit includes a transistor, a first dielectric layer, an etch stop layer, a first via and a first conductive layer. The first dielectric layer is disposed between the transistor and the etch stop layer. The first via is disposed in the first dielectric layer and the etch stop layer, and electrically connected to the transistor. The first conductive layer is in contact with the first via, wherein the first via is disposed between the first conductive layer and the transistor, and the etch stop layer is aside a portion of the first via adjacent to the first conductive layer.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Lung Lai, Chen-Chieh Chiang, Chi-Cherng Jeng, Shiu-Ko JangJian
  • Patent number: 9698055
    Abstract: A method includes etching a semiconductor substrate to form a semiconductor strip and trenches on opposite sidewalls of the semiconductor strip. A spacer is formed on a sidewall of the semiconductor strip which is used as an etching mask to extend the trenches down into the semiconductor substrate. A dielectric material is filled into the trenches and then planarized to form insulation regions in the trenches. The insulation regions are recessed. After the recessing, top surfaces of the insulation regions are lower than a top surface of the semiconductor strip and a gate structure may be formed thereon.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Ryan Chia-Jen Chen, Srisuda Thitinun
  • Patent number: 9691615
    Abstract: After forming a material stack including, from bottom to top, a dielectric material layer, a transfer layer, a hard mask layer and a neutral layer over a substrate, the neutral layer and the hard mask layer is patterned to create trenches therein that correspond to areas where unnecessary lines generated by a self-assembly of a self-assembling material subsequently formed and/or unnecessary portions of such lines are present. The self-assembling material is applied over the top surfaces of the patterned neutral layer and the transfer layer to form a self-aligned lamellar structure including alternating first and second domains. The second domains are removed selective to the first domains to provide a directed self-assembly (DSA) pattern of the first domains. Portions of the first domains not intersecting the trenches can be transferred into the patterned hard mask layer, resulting in a composite pattern of a pattern of trenches and the DSA pattern.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Joy Cheng, Gregory S. Doerk, Michael A. Guillorn, HsinYu Tsai
  • Patent number: 9677172
    Abstract: Methods for forming a liner layer are provided herein. In some embodiments, a method of forming a liner layer on a substrate disposed in a process chamber, the substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method includes exposing the substrate to a cobalt precursor gas and to a ruthenium precursor gas to form a cobalt-ruthenium liner layer on the first surface of the substrate and on the sidewall and bottom surface of the opening.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: June 13, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tae Hong Ha, Wei Lei, Kie Jin Park
  • Patent number: 9653323
    Abstract: A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 16, 2017
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Raymond Lim
  • Patent number: 9646899
    Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 9, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Kyle K. Kirby, Luke G. England, Jaspreet S. Gandhi
  • Patent number: 9640388
    Abstract: In a method for forming a fluorocarbon-based insulating film to be in contact with a metal, a microwave is irradiated to the metal to which moisture is adhered in a hydrogen-containing atmosphere. Then plasma CVD using a fluorocarbon-based gas is performed on the metal to which the microwave is irradiated to form the insulating film.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 2, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Kasai, Kotaro Miyatani, Takuya Kurotori, Kenichi Kote, Yutaka Fujino, Akira Tanihara, Kohei Kawamura
  • Patent number: 9633897
    Abstract: The present disclosure relates to a method of forming an interconnect structure. In some embodiments, the method is performed by forming a trench within a first dielectric layer and forming sacrificial spacers along sidewalls of the trench. The trench is filled with a conductive material, and the sacrificial spacers are removed after the trench has been filled with the conductive material. A second dielectric layer is formed over the first dielectric layer to leave an air-gap in a region from which the sacrificial spacers were removed.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin