Abstract: For fabricating an interconnect structure within a dielectric material comprised of at least one dielectric reactant element, an interconnect opening formed within the dielectric material is filled with a conductive fill material comprised of first and second dopant elements that are different. A diffusion barrier material, that surrounds the conductive fill material, is formed from a reaction of the first dopant element and a dielectric reactant element. Also, a boundary material, that surrounds the conductive fill material, is formed from a reaction of the second dopant element and a dielectric reactant element. The boundary material prevents diffusion of a dielectric reactant element from the dielectric material into the conductive fill material.

Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.

Abstract: Isolation regions 12 are formed on a silicon substrate 10 to isolate NMOS and PMOS regions in which to form NMOS and PMOS transistors respectively. A silicon oxide film 14 and an amorphous silicon film 16 are formed as a gate insulating film on the silicon substrate 10. N-type impurities are injected into the NMOS regions (FIG. 1A). A WSi film 22 is formed on the amorphous silicon film 16, and N-type impurities are injected only into the PMOS regions of the film 16 (FIG. 1C). A silicon oxide film 28 and a silicon nitride film 30 are formed on the WSi film 22 and then etched into gate electrodes (FIG. 1E).

Abstract: The present invention provides a method of photochemically producing a vertical interconnect between a first and a second thin-film microelectronic device in an vertical interconnect area which comprises an overlap of a stack of a first electrically conducting area, optionally an organic electrically semiconducting area, an organic electrically insulating area comprising adapted photoresist material and a second organic electrically conducting area, wherein the organic electrically insulating area is removed within the overlapping area and substituted by an electrically conducting area which is extended from at least said first or said second electrically conducting area. The method is useful in the manufacture of electronic devices, preferably integrated circuits, consisting substantially of organic materials.

Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.

Abstract: An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×1017 cm−2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C.

Abstract: A smart power device and method for fabricating the same is disclosed in which an impact ionization to a drain region is reduced thereby securing a wide SOA (Safe Operation Area) and improving current driving characteristics.

Abstract: A conductive connection forming method includes forming a first layer including a first metal on a substrate and forming a second layer including a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material including the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may include annealing the first and second layer. An exemplary first metal includes copper, and an exemplary second metal includes aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer. An integrated circuit includes a semiconductive substrate, a layer including a first metal over the substrate, and a layer of alloy material within the first metal including layer.

Abstract: The method of the present invention includes providing a silicon substrate having an impurity region, forming an inter-layer insulating film having a contact hole in the impurity region and forming a titanium film and titanium nitride film in the contact hole. The method of the present invention further includes conducting a heat treatment to cause a reaction between the titanium film and the silicon substrate and forming a tungsten plug on the titanium nitride film in the contact hole. The device of the present invention including the bit lines are made up of a first inter-layer insulating film on the substrate having a first contact hole over the impurity region, a titanium film in the first contact hole, a titanium nitride film on the titanium film, a titanium silicide film on the silicon substrate wherein the titanium silicide film does not include an agglomerate, a tungsten plug on the titanium nitride film in the first contact hole and a circuit element on the first inter-layer insulating film.

Abstract: A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a non-conformal film on the structure including the plurality of patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by the second resist; and removing the second resist and the non-conformal film.

Abstract: A method of forming a local interconnect includes forming at least two transistor gates over a semiconductor substrate. A local interconnect layer is deposited to overlie at least one of the transistor gates and interconnect at least one source/drain region of one of the gates with semiconductor substrate material proximate another of the transistor gates. In one aspect, a conductivity enhancing impurity is implanted into the local interconnect layer in at least two implanting steps, with one of the implantings providing a peak implant location which is deeper into the layer than the other. Conductivity enhancing impurity is diffused from the local interconnect layer into semiconductor substrate material therebeneath. In one aspect, conductivity enhancing impurity is implanted through the local interconnect layer into semiconductor substrate material therebeneath.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: In a semiconductor device having a metal wiring conductor connected to a contact hole formed through an interlayer insulator layer formed on a lower level circuit, a lower level tungsten film is deposited under a condition giving an excellent step coverage so as to fill the contact hole, and an upper level tungsten film is further deposited under a condition of forming a film having a stress smaller than that of the lower level tungsten film. The metal wiring conductor is formed of a double layer which is composed of the lower level tungsten film and the upper level tungsten film, and therefore, has a reduced stress in the whole of the film. Thus, there is obtained the tungsten film wiring conductor which fills the inside of the contact hole with no void and therefore has a high reliability, and which has a low film stress. In addition, the number of steps in the manufacturing process can be reduced.

Abstract: A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a non-conformal film on the structure including the plurality of patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by the second resist; and removing the second resist and the non-conformal film.

Abstract: A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

Abstract: A capacitively sensed micromachined component includes an electrically insulative substrate (120) having a first side (121) and a second side (122) opposite the first side. The component also includes a first layer (130) adjacent to the second side of the electrically insulative substrate where at least a first portion of the first layer located adjacent to the second side of the electrically insulative substrate is infra-red light absorbing and is also electrically conductive. The component further includes a diffusion and chemical barrier layer (240) encapsulating the first layer and the electrically insulative substrate. The component still further includes a capacitively sensed micromachined device (310) on the diffusion and chemical barrier layer.

Abstract: An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes with a process employing a W-Salicide combined with ion mixing implantation. The contact integration technique realizes junctions having low contact resistance (RC), with ultra-shallow contact junction depth (XJC) and high doping concentration in the silicide contact interface (Nc).

Abstract: A method of fabricating a self-aligned silicide (salicide). A gate and a source/drain region are formed in the substrate. An ion implantation process is performed to dope surfaces of the gate and the source/drain region with metal ions. A thermal process is performed to have the metal ions react with silicon in surfaces of the gate and the source/drain region, so as to form silicide layers on the gate and the source/drain region. The metal ions include cobalt ions, titanium ions, nickel ions, platinum ions and palladium ions.

Abstract: A method for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided.

Abstract: A method for forming a gate electrode of a semiconductor device, which improves thermal stability of a tungsten/polysilicon structure. The method for forming a gate electrode of a semiconductor device includes: sequentially forming a first insulating film, a polysilicon layer and a tungsten layer on a semiconductor substrate; adding oxygen to the tungsten layer; forming a second insulating film on the tungsten layer to which oxygen is added; and selectively removing the second insulating film, the tungsten layer, the polysilicon layer and the first insulating film to form a gate electrode.

Abstract: A semiconductor device comprises impurity diffusion layers formed in a semiconductor substrate and containing a metal element, whose siliciding activation energy is less than 1.8 eV, at a concentration of more than 1×1011 atoms/cm2 and less than 1×1015 atoms/cm2, an insulating film formed on the semiconductor substrate, contact holes formed in the insulating film on the impurity diffusion layers, and contact plugs formed via the contact holes. Accordingly, there is provided the semiconductor device that has a connection structure between an impurity-containing semiconductor layer and a conductive film and is capable of suppressing a leakage current generated at a contact portion between the impurity diffusion layer and the conductive film.

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a substrate (1) with an electrically insulating layer (2) above it; providing an interconnect (WL) having a lower conductive layer (3) and an upper conductive layer (4) on the insulating layer (2), the lower conductive layer (3) consisting of silicon of a first conduction type (n); embedding the interconnect (WL) in an electrically insulating structure (5, 8); reversing the doping of at least one first section (A1; A2) of the lower conductive layer (3) of the interconnect (WL) to the second conduction type (p); and at least partially uncovering a second section (A3) of the lower conductive layer (3) of the interconnect (WL) of the first conduction type (n); and selectively etching the second section (A3) of the lower conductive layer (3) of the interconnect (WL) of the first conduction type (n), with the first section (A1; A2) acting as an etching stop.

Abstract: A method for reducing the resistivity in a gate electrode is described. In one embodiment of the present invention, a silicon layer is formed on a substrate. A tungsten silicide layer is then formed on the silicon layer. The tungsten silicide layer is implanted with boron ions and an anneal is performed. The tungsten silicide layer and silicon layer are then patterned to form a gate electrode.

Abstract: In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.

Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.

Abstract: In order to provide a method of fabricating a high melting point metal wiring layer improved to be capable of forming a thin line without employing a mask, a gate oxide film is formed on a semiconductor substrate. A silicon layer is formed on the gate oxide film. A high melting point metal layer is formed on the silicon layer. A mixed layer of the silicon layer and the high melting point metal layer is formed on a portion for defining a wiring layer. Remaining parts of the silicon layer and the high melting point metal layer other than those forming the mixed layer are removed by etching thereby forming a wiring layer. The wiring layer is heat-treated.

Abstract: The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1−x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

Abstract: An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes with a process employing a W-Salicide combined with ion mixing implantation. The contact integration technique realizes junctions having low contact resistance (RC), with ultra-shallow contact junction depth (XJC) and high doping concentration in the silicide contact interface (NC).

Abstract: A smart power device and method for fabricating the same is disclosed in which an impact ionization to a drain region is reduced thereby securing a wide SOA (Safe Operation Area) and improving current driving characteristics.

Abstract: In a method of fabricating a semiconductor device in which a metal film is formed that is to serve as the diffusion barrier layer material of a plug electrode material that is used when forming a plug electrode on a diffusion layer electrode or a gate electrode in which a metal silicide layer has been formed, increase in the resistance of the plug electrode is prevented. Immediately after the formation of a plug hole by a dry etching method, silicon ions are implanted with an acceleration voltage of at least 20 KeV and at a dosage of at least 1×1013 atoms/cm2, following which a titanium film and a titanium nitride film are formed as the metal film by a sputtering method without carrying out etching by an RF etching method.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: An integrated raised contact formation method to achieve ultra shallow junction devices is described. Semiconductor device structures are provided in and on a substrate and covered with a dielectric layer. The dielectric layer is etched through to form first openings to the substrate. The surface of the substrate exposed within the first openings is amorphized. A silicon layer is selectively formed on the amorphized substrate surface. Then, ions are implanted into the silicon layer to form raised contacts. Thereafter, the dielectric layer is etched through to form second openings to gates. The first and second openings are filled with a conducting layer to complete formation of contacts in the fabrication of an integrated circuit device.

Abstract: A silicon oxide film and a doped polysilicon film are successively formed on a silicon substrate. Then, a doped polysilicon-germanium film is formed on the doped polysilicon film as a film having a higher impurity activation rate than polysilicon. Then, a barrier film, a metal film and another barrier film are successively formed on the doped polysilicon-germanium film. Thus obtained is a method of manufacturing a semiconductor device comprising a polymetal gate capable of suppressing increase of gate resistance also when an impurity introduced into a semiconductor film diffuses into the barrier films.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).

Abstract: Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.

Abstract: A method of forming a contact pad on a semiconductor wafer is achieved. A first photoresist layer is formed on the surface of a substrate, expect in a region where the contact pad will be formed. A nitrogen ion implantation is performed on the substrate uncovered by the first photoresist layer, followed by the complete removal of the first photoresist layer. Next, a silicon oxide layer is grown on the substrate, except in the region for the formation of the contact pad. Two adjacent MOS transistors are formed on the silicon oxide layer. A conductive layer is formed on the surface of the substrate to cover the two MOS transistors as well as to fill in the gap between the two MOS transistors. A patterned second photoresist layer is subsequently formed on the surface of the conductive layer to define the patterns of the contact pad.

Abstract: The present invention is directed to a simplified, CVD-less method of forming a barrier layer for a metal layer which prevents metal contamination in an integrated circuit. The invention utilizes a sacrificial multilayer dielectric structure and selective etching to form the top barrier layer. An opening is etched in the structure and a plating layer is deposited in the opening. A first unneeded portion of the structure along with an unneeded portion of the plating layer is removed utilizing an etchant that is selective for the first unneeded structural portion. A Cu layer is deposited and implanted with barrier material to form the top barrier layer. A second unneeded portion of the structure along with an unneeded portion of the top barrier layer is removed utilizing an etchant that is selective for the second unneeded structural portion. The resulting structure is a metal interconnect structure having an overlying top barrier layer which is produced without using CVD techniques.

Abstract: A method of forming conducting diffusion barriers by depositing an initial film and implanting ions to modify the film is provided. An initial film having good step coverage is deposited over a semiconductor substrate. The initial material need not have the desired properties for a conducting diffusion barrier, but preferably contains one or more elements to be used in forming a desired film with the appropriate properties. The initial material is deposited by CVD, PECVD or IMP deposition. Ions are preferably implanted using plasma immersion ion implantation (PIII), although other methods are also provided. The method of the present invention produces binary, ternary, quaternary and other more complex films, while providing adequate step coverage.

Abstract: Disclosed is a method using the implantation of ionized titanium for the formation of an electrical contact having a metal silicide diffusion barrier. The electrical contact is created by the steps of etching a contact opening over an active region on an in-process integrated circuit wafer, implanting metal ions into the contact opening, and annealing the contact opening to form a titanium silicide layer at the bottom of the contact opening adjacent to the underlying active region. In a further step, a titanium nitride layer is formed on the surface of the contact opening above the metal silicide layer, and the remainder of the contact opening is then filled by depositing tungsten into the contact opening. The method is especially useful for forming contacts having a high aspect ratio and for forming self-aligned contacts as it is capable of forming a uniform silicide layer at the bottom of a narrow contact opening.

Abstract: A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer. Generally, boron is doped to the polycrystalline silicon after the step of the plasma doping of germanium. The process of plasma doping of germanium comprises the step of forming germanium contained plasma and enhancing bias electric potential to substrate for the formulated germanium plasma to be accelerated and injected to the polycrystalline silicon layer revealed. If the present invention is applied to CMOS transistor device, doping mask for the germanium plasma doping can be used.

Abstract: The present invention provides a semiconductor device having: at least a first diffusion layer having a first impurity concentration; at least a second diffusion layer having a first impurity concentration which is lower than the first impurity concentration, and the first and second diffusion layers being of the same conductivity type, wherein a silicide layer is formed over the first diffusion layer, while no silicide layer is formed over the second diffusion layer.

Abstract: A method of encapsulating metal lines (130, 132, 134, 136, 138) by implantation of dopants to form surface regions (131, 133, 135, 137, 139) after the metal lines have been fabricated. The surface regions may act as passivation layers and electromigration inhibitors and so forth.

Abstract: In a thin film forming method and an apparatus A for implementing the method, a deposition chamber 1 provided with a substrate holder 12 and a radical emitting device 2 continuing to the chamber 1 for emitting neutral radicals uniformly to a whole deposition target region of a deposition target substrate S held by the holder 12 are used. Deposition gas plasma PL1 is formed at the vicinity of the substrate S on the holder 12 by supplying a predetermined deposition gas into the chamber 1. Neutral radicals RA are produced by exciting and dissociating a predetermined radical material gas in the radical emitting device 2, and the radicals are uniformly emitted to the deposition target region of the substrate S for forming a predetermined thin film on the substrate S.

Abstract: A silicide process using a pre-anneal amorphization implant prior to silicide anneal. A layer of titanium is deposited and reacted to form titanium silicide (32) and titanium nitride. The titanium nitride is removed and a pre-anneal amorphization implant is performed to enable increased transformation of the silicide (32) from a higher resistivity phase to a lower resistivity phase. A heavy dopant species (40) is used for the pre-anneal amorphization implant such as arsenic, antimony, or germanium. After the implant, the silicide anneal is performed to accomplish the transformation. An advantage of the invention is providing a silicide process having reduced silicide sheet resistance for narrow polysilicon lines.

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); introducing a silicide enhancing substance into the conductive structure (step 304 of FIG. 3); amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure (step 310 of FIG. 3); and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof.

Abstract: The invention comprises methods of depositing silicon oxide material onto a substrate. In but one aspect of the invention, a method of depositing a silicon oxide containing layer on a substrate includes initially forming a layer comprising liquid silicon oxide precursor onto a substrate. After forming the layer, the layer is doped and transformed into a solid doped silicon oxide containing layer on the substrate. In a preferred implementation, the doping is by gas phase doping and the liquid precursor comprises Si(OH)4. In the preferred implementation, the transformation occurs by raising the temperature of the deposited liquid precursor to a first elevated temperature and polymerizing the deposited liquid precursor on the substrate. The temperature is continued to be raised to a second elevated temperature higher than the first elevated temperature and a solid doped silicon oxide containing layer is formed on the substrate.

Abstract: A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.

Abstract: A method of forming electrical contacts includes the step of implanting ions into a contact hole at an angle to create an enlarged plug enhancement region at the bottom of a contact hole. Thus, even if the contact hole is misaligned, over-sized, or over-etched, the enlarged plug enhancement region contains subsequently formed barrier layers and other conductive materials to reduce current leakage into the underlying substrate or into adjacent circuit elements.