Altering Composition Of Conductor Patents (Class 438/658)
  • Patent number: 10978572
    Abstract: Embodiments of the present invention are directed to techniques for forming a self-aligned contact liner using metal-insulator transition materials. The self-aligned contact architecture described herein prevents a short between the gate and the source/drain, even when the self-aligned contact (SAC) cap has eroded to the point where the gate is exposed. In a non-limiting embodiment of the invention, a dielectric cap is formed over a conductive gate. A source or drain region is formed adjacent to the conductive gate. A dielectric liner is formed over the dielectric cap and the source or drain region such that a first portion of the dielectric liner is on a surface of the source or drain region. The dielectric liner includes a metal-insulator transition material. The first portion of the dielectric liner is metalized via germanium oxide sublimation.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10879366
    Abstract: Techniques for reducing the specific contact resistance of metal—semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 29, 2020
    Assignee: Acorn Semi, LLC
    Inventors: Walter A. Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 10822714
    Abstract: A method of growing a crystal in a recess in a substrate on which an insulating film having the recess is formed, includes: forming a first film on the insulating film at a thickness as not to completely fill the recess; etching the first film by an etching gas to remain the first film only in a bottom portion of the recess; annealing the substrate such that the first film in the bottom portion is modified into a crystalline layer; forming a second film on the insulating film and a surface of the crystalline layer at a thickness as not to completely fill the recess; annealing the substrate such that the second film is crystallized from the bottom portion through a solid phase epitaxial growth to form an epitaxial crystal layer; and etching and removing the second film remaining on the substrate by an etching gas.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: November 3, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoichiro Chiba, Daisuke Suzuki, Kazuhide Hasebe
  • Patent number: 10358737
    Abstract: A method includes providing a plurality of particles of an energetic material suspended in a dispersion liquid to an EPD chamber or configuration; applying a voltage difference across a first pair of electrodes to generate a first electric field in the EPD chamber; and depositing at least some of the particles of the energetic material on at least one surface of a substrate, the substrate being one of the electrodes or being coupled to one of the electrodes.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: July 23, 2019
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Kyle Sullivan, Alexander E. Gash, Joshua Kuntz, Marcus A. Worsley
  • Patent number: 9666439
    Abstract: A method of manufacturing a semiconductor device includes forming a seed layer containing a metal element on a substrate by performing a first process and a second process in a time-division manner. The first process supplying and exhausting organic metal-containing gas containing the metal element to the substrate. The second process supplying and exhausting inorganic metal-containing gas containing the metal element to the substrate, and forming a metal-containing nitride film on the substrate on which the seed layer is formed using the seed layer as a seed by performing a third process and a fourth process in a time-division manner. The third process supplying and exhausting the inorganic metal-containing gas to the substrate. The fourth process supplying and exhausting nitrogen-containing gas to the substrate.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: May 30, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Arito Ogawa
  • Patent number: 9595449
    Abstract: Oxidation treatment of a Si1-xGex (0<x<1) substrate forms on the substrate an interfacial layer comprised of silicon oxide and germanium oxide. The presence of germanium oxide in the interfacial layer is deleterious to the quality of the interfacial layer/Si1-xGex conducting channel as evidenced by an increase in charge interface states and a decrease in carrier mobility. Germanium oxide is scavenged from the interfacial layer in a scavenging step comprising heating the interfacial layer/substrate in a hydrogen-containing reducing atmosphere at a temperature of from about 450° C. to about 800° C. to reduce the germanium oxide content of the interfacial layer to not more than about 10% by weight, for example, not more than about 1% by weight, of the weight of the scavenged interfacial layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, ChoongHyun Lee
  • Patent number: 9190480
    Abstract: A semiconductor body has a first surface, a second opposing surface, an edge, an active device region, and an edge termination region. A trench extends from the first surface into the semiconductor body in the edge termination region and includes sidewalls and an insulated electrode. A first conductivity type doped region extends from the first surface into the semiconductor body in the edge termination region and has a planar outer surface along the first surface that adjoins the trench at a corner of the trench sidewall and the first surface and has a side surface extending from the corner along the trench sidewall. A first interconnect contacts the trench electrode. A second interconnect contacts the outer surface and the side surface. A contact couples the first doped region to the trench electrode and has a bottom surface coplanar with the first surface from a contact edge to the corner.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 17, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Li Juin Yip, Oliver Blank
  • Patent number: 9159667
    Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiaoqiang Zhang, O Sung Kwon, Jianghu Yan, Wen-Hu Hung, Roderick Miller, HongLiang Shen
  • Patent number: 9029260
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Chieh Lin, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
  • Patent number: 9012323
    Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 21, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Arito Ogawa, Tsuyoshi Takeda
  • Patent number: 8975182
    Abstract: A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignees: Nissan Motor Co., Ltd., Sumitomo Metal Mining Co., Ltd., Sanken Electric Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Satoshi Tanimoto, Yusuke Zushi, Yoshinori Murakami, Takashi Iseki, Masato Takamori, Shinji Sato, Kohei Matsui
  • Patent number: 8969197
    Abstract: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Takeshi Nogami, Christopher Parks, Tsong-Lin Tai
  • Patent number: 8962466
    Abstract: A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Feng-Min Lee, Erh-Kun Lai, Wei-Chih Chien, Ming-Hsiu Lee, Chih-Chieh Yu
  • Patent number: 8951912
    Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Arito Ogawa, Tsuyoshi Takeda
  • Patent number: 8946667
    Abstract: A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first wiring structure overlies the first dielectric material. The method forms a first electrode material overlying the first wiring structure and a resistive switching material comprising overlying the first electrode material. An active metal material is formed overlying the resistive switching material. The active metal material is configured to form an active metal region in the resistive switching material upon application of a thermal energy characterized by a temperature no less than about 100 Degree Celsius. In a specific embodiment, the method forms a blocking material interposing the active metal material and the resistive switching material to inhibit formation of the active metal region in the resistive switching material during the subsequent processing steps.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 3, 2015
    Assignee: Crossbar, Inc.
    Inventors: Mark Harold Clark, Steven Maxwell, Harry Gee, Natividad Vasquez
  • Patent number: 8937013
    Abstract: A method for easily forming a region with conductivity and high wettability without a step for removing a photocatalytic reaction layer, which is formed over a conductive layer, is proposed. The photocatalytic reaction layer is formed over a photocatalytic conductive layer, and the photocatalytic conductive layer is irradiated with ultraviolet light to form a region with conductivity and higher wettability than the photocatalytic reaction layer on a surface of the photocatalytic conductive layer which is irradiated with ultraviolet light. Note that for the photocatalytic conductive layer, a layer having a photocatalytic property of which resistivity is lower than or equal to 1×10?2 ? cm can be used.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masafumi Morisue
  • Patent number: 8932911
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: January 13, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Torsten Huisinga, Carsten Peters, Andreas Ott, Axel Preusse
  • Patent number: 8918152
    Abstract: Disclosed are devices comprising multiple nanogaps having a separation of less than about 5 nm. Also disclosed are methods for fabricating these devices.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: December 23, 2014
    Assignee: The Trustees Of The University Of Pennsylvania
    Inventors: Douglas R. Strachan, Danvers E. Johnston, Beth S. Guiton, Peter K. Davies, Dawn A. Bonnell, Alan T. Johnson, Jr.
  • Patent number: 8871107
    Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe, Mark Hoinkis, Chun Yan
  • Publication number: 20140295213
    Abstract: The invention relates to a method for functionalizing an electrically conductive substrate, which is not a substrate made of gold, via a layer of chemical compounds, said method comprising the following steps: a step in which the electrically conductive substrate is placed in contact with chemical compounds comprising at least a disulfide terminal group; a step in which the disulfide terminal group of said chemical compounds is electro-oxidized, causing said chemical compounds to form a layer at the surface of the electrically conductive substrate.
    Type: Application
    Filed: October 5, 2012
    Publication date: October 2, 2014
    Applicants: UNIVERSITE JOSEPH FOURIER, Commissariat a l'energie atomique et aux ene alt
    Inventors: Eric Jalaguier, Julien Buckley, Xavier Chevalier, Guy Royal
  • Publication number: 20140264920
    Abstract: Presented herein is a method for electrolessly forming a metal cap in a via opening, comprising bringing a via into contact with metal solution, the via disposed in an opening in a substrate, and forming a metal cap in the opening and in contact with the via, the metal cap formed by an electroless chemical reaction. A metal solution may be applied to the via to form the metal cap. The metal solution may comprises at least cobalt and the cap may comprise at least cobalt, and may optionally further comprise tungsten, and wherein the forming the cap comprises forming the cap to further comprise at least tungsten. The metal solution may further comprise at least hypophosphite or dimethlyaminoborane.
    Type: Application
    Filed: March 25, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Patent number: 8815728
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device uses an aluminum alloy, rather than aluminum, for a metal gate. Therefore, the surface of the high-k metal gate after the CMP is aluminum alloy rather than pure aluminum, which can greatly reduce defects, such as corrosion, pits and damage, in the metal gate and improve reliability of the semiconductor device.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Li Jiang, Mingqi Li, Pulei Zhu
  • Patent number: 8802560
    Abstract: A method for forming a semiconductor interconnect structure includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. A metal layer fills the opening and covers the dielectric layer. The metal layer is planarized so that it is co-planar with a top of the dielectric layer. A treating process is performed on the metal layer to convert a top surface thereof into a metal oxide layer. A copper-containing layer is then formed over the metal oxide layer and the dielectric layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the metal oxide layer and does not etch into the underlying metal layer. A radiation exposure process is thereafter performed on the metal oxide layer to convert it into a non-oxidized metal layer.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20140187039
    Abstract: A method for tuning the effective work function of a gate structure in a semiconductor device is described. The semiconductor device is part of an integrated circuit and the gate structure has a metal layer and a high-k dielectric layer separating the metal layer from an active layer of the semiconductor device. The method includes providing an interconnect structure of the integrated circuit on top of the gate structure, the interconnect structure comprising a layer stack comprising at least a pre-metal dielectric layer comprising a metal filled connecting via connected to the gate structure through the pre-metal dielectric layer, and the interconnect structure having an upper exposed metal portion; and, thereafter, exposing at least a portion of the upper exposed metal portion to a plasma under predetermined exposure conditions, to tune the effective work function of the gate structure.
    Type: Application
    Filed: December 18, 2013
    Publication date: July 3, 2014
    Applicant: IMEC
    Inventors: Thomas Kauerauf, Alessio Spessot, Christian Caillat
  • Patent number: 8741783
    Abstract: A method of cleaning an inside of a processing chamber is provided according to an embodiment of the present disclosure. The method includes supplying a fluorine-based gas and a nitrogen oxide-based gas as the cleaning gas, into the processing chamber heated to a first temperature, and removing a deposit by a thermochemical reaction. The method further includes changing a temperature in the processing chamber to a second temperature higher than the first temperature, and supplying the fluorine-based gas and the nitrogen oxide-based gas as the cleaning gas, and removing extraneous materials, remaining on the surface of the member in the processing chamber, by a thermochemical reaction.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 3, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kenji Kameda, Yuji Urano
  • Patent number: 8716098
    Abstract: A method for forming a non-volatile memory device includes providing a substrate having a surface region, forming a first wiring structure overlying the surface region, depositing a first dielectric material overlying the first wiring structure, forming a via opening in the first dielectric material to expose a portion of the first wiring structure, while maintaining a portion of the first dielectric material, forming a layer of resistive switching material comprising silicon, within the via opening, forming a silver material overlying the layer of resistive switching material and the portion of the first dielectric material, forming a diffusion barrier layer overlying the silver material, and selectively removing a portion of the silver material and a portion of the diffusion barrier layer overlying the portion of the first dielectric material while maintaining a portion of the silver material and a portion of the diffusion barrier material overlying the layer of silicon material.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 6, 2014
    Assignee: Crossbar, Inc.
    Inventors: Scott Brad Herner, Natividad Vasquez
  • Patent number: 8716129
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes the step of forming a silicon dioxide film. The step of forming an electrode includes the steps of forming a metal film containing Al and Ti on the silicon carbide substrate, and heating the metal film. The step of heating the metal film has the steps of increasing temperature of the metal film from a temperature of less than 300° C. to a temperature of not less than 300° C. and not more than 450° C. with a first temperature gradient, holding the metal film within a temperature range of not less than 300° C. and not more than 450° C. with a second temperature gradient, and increasing the temperature of the metal film to a temperature of not less than 500° C. with a third temperature gradient. The second temperature gradient is smaller than the first temperature gradient and the third temperature gradient.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: May 6, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hideto Tamaso
  • Patent number: 8647959
    Abstract: A method of fabricating a semiconductor device includes forming a bottom electrode material layer containing aluminum and copper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Chun-Chen Hsu
  • Patent number: 8633101
    Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: January 21, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masahiro Sugimoto, Akinori Seki, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
  • Publication number: 20130313687
    Abstract: [Aim of Invention] Providing the effective semiconductor miniaturization and its higher-dense fine wiring with the through-hole and the buried via electrode structure of the lower resistivity and higher reliability material at the low cost manufacturing method. [Solution] Preparing the sedimentation layer 57 buried at first the dried-sintered-porous metal material of paste 56 in the through-hole 51 having a insulation layer 54 on the board structure 50, fully covered over the porous area top of the sedimentation layer 57 with the second metal paste and then full-filling the second metal into the porous area of the sedimentation layer 57.
    Type: Application
    Filed: January 14, 2013
    Publication date: November 28, 2013
    Applicant: ZyCube Co., Ltd.
    Inventors: Manabu Bonkohara, Hirofumi Nakamura, Qiwei He
  • Patent number: 8592308
    Abstract: A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Javier Ayala, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 8501600
    Abstract: Methods for depositing germanium-containing layers on silicon-containing layers are provided herein. In some embodiments, a method may include depositing a first layer atop an upper surface of the silicon-containing layer, wherein the first layer comprises predominantly germanium (Ge) and further comprises a lattice adjustment element having a concentration selected to enhance electrical activity of dopant elements, wherein the dopant elements are disposed in at least one of the first layer or in an optional second layer deposited atop of the first layer, wherein the optional second layer, if present, comprises predominantly germanium (Ge). In some embodiments, the second layer is deposited atop the first layer. In some embodiments, the second layer comprises germanium (Ge) and dopant elements.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Errol Sanchez, Yi-Chiau Huang, David K. Carlson
  • Patent number: 8501621
    Abstract: Three-dimensionally spatially localized artificial filament in the active layer of the memristive device formed by means of ion implantation through the top electrode structure provide the means to achieve high repeatability and high reliability of the memristive devices, leading to significantly improved manufacturing yield. The memristive devices fabricated according to the disclosed method of fabrication can be used in data storage, signal processing and sensing applications.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: August 6, 2013
    Assignee: MicroXact, Inc.
    Inventor: Vladimir Kochergin
  • Patent number: 8486759
    Abstract: A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips, each provided on the side face thereof with a part of a connection terminal coupled with a circuit pattern formed on the front face, have been stacked and bonded. Connection terminal portions on the side faces of the respective semiconductor chips are interconnected by a wiring pattern. The connection terminal on the semiconductor chip is led from the front face to the side face and formed by applying spraying of a conductive material in a mist state.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 16, 2013
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventor: Masato Ikeda
  • Publication number: 20130143402
    Abstract: The disclosure provides a method for forming a dense Cu thin film by atomic layer deposition, comprising the following steps of: (A) providing an additive gas; (B) choosing a copper-containing metal-organic complex as a precursor; (C) using a carrier gas to introduce the additive gas into the precursor cell mixing with the precursor; (D) pre-depositing the precursor on the surface of the substrate with a TaNx thin film at a first temperature; (E) removing the excess copper-containing metal-organic complex and the excess additive gas; (F) introducing a reducing gas into the reactive system and annealing at a second temperature to reduce the Cu2O thin film to form a Cu thin film on the substrate and (G) removing the excess reducing gas from the reactive system.
    Type: Application
    Filed: February 15, 2013
    Publication date: June 6, 2013
    Applicant: NANMAT TECHNOLOGY CO., LTD.
    Inventor: Nanmat Technology Co., Ltd.
  • Patent number: 8450208
    Abstract: In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki
  • Patent number: 8450209
    Abstract: A method of forming a non-volatile memory device includes providing a substrate having a surface and forming a first dielectric overlying the surface, forming a first wiring comprising aluminum material over the first dielectric, forming a silicon material over the aluminum material to form an intermix region consuming a portion of the silicon material and aluminum material, annealing to formation a first alloy from the intermix region, forming a p+ impurity polycrystalline silicon over the first alloy material, forming a first wiring structure from at least a portion of the first wiring, forming a resistive switching element comprising an amorphous silicon material formed over the p+ polycrystalline silicon, and forming a second wiring structure comprising at least a metal material over the resistive switching element.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 28, 2013
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Publication number: 20130062768
    Abstract: A method for producing a substrate with a copper or a copper-containing coating is disclosed. The method comprises a first step wherein a first precursor, a second precursor and a substrate are provided. The first precursor is a copper complex that contains no fluorine and the second precursor is selected from a ruthenium complex, a nickel complex, a palladium complex or mixtures thereof. In the second step, a layer is deposited at least on partial regions of a surface of the substrate by using the first precursor and the second precursor by means of atomic layer deposition (ALD). The molar ratio of the first precursor:second precursor used for the ALD extends from 90:10 to 99.99:0.01. The obtained layer contains copper and at least one of ruthenium, nickel and palladium. Finally, a reduction is performed step in which a reducing agent acts on the substrate obtained after depositing the copper-containing layer.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 14, 2013
    Applicants: TECHNISCHE UNIVERSITAET CHEMNITZ, FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Thomas WAECHTLER, Stefan SCHULZ, Thomas GESSNER, Steve MUELLER, André TUCHSCHERER, Heinrich LANG
  • Publication number: 20130065391
    Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 14, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Arito Ogawa, Tsuyoshi Takeda
  • Patent number: 8373069
    Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: February 12, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Daiki Komatsu
  • Publication number: 20130020616
    Abstract: A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.
    Type: Application
    Filed: July 20, 2011
    Publication date: January 24, 2013
    Applicant: International Business Machines Corporation
    Inventors: Javier Ayala, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 8357607
    Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg alloy layer 32 which is formed of Mg and a metal selected from a group consisting of Pt, Mo, and Pd. The Mg alloy layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: January 22, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuaki Oya, Toshiya Yokogawa, Atsushi Yamada, Ryou Kato
  • Publication number: 20130005142
    Abstract: Provided is a method and apparatus for forming a silicon film, which are capable of suppressing generation of a void or seam. The method includes performing a first film-forming process, performing an etching process, performing a doping process, and performing a second film-forming process. In the first film-forming process, a non-doped silicon film that is not doped with an impurity is formed so as to embed a groove of an object. In the etching process, the non-doped silicon film formed via the first film-forming process is etched. In the doping process, the non-doped silicon film etched via the etching process is doped with an impurity. In the second film-forming process, an impurity-doped silicon film is formed so as to embed the silicon film doped via the doping process.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 3, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akinobu Kakimoto, Satoshi Takagi, Kazuhide Hasebe
  • Patent number: 8338291
    Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to create a reentrant profile in the second electrically conductive material layer and to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: December 25, 2012
    Assignee: Eastman Kodak Company
    Inventors: Lee W. Tutt, Shelby F. Nelson
  • Patent number: 8334199
    Abstract: A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes a Zn layer 32 and an Ag layer 34 provided on the Zn layer 32. The Zn layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: December 18, 2012
    Assignee: Panasonic Corporation
    Inventors: Mitsuaki Oya, Toshiya Yokogawa, Atsushi Yamada, Akihiro Isozaki
  • Patent number: 8324099
    Abstract: A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug comprises a first region, a second region, a third region, and a fourth region, wherein the first region is disposed beneath the second region and doped with a first doping concentration, the second region is disposed above the first region and below the third region and is not doped, the third region is disposed above the second region and below the fourth region and is doped with a second doping concentration that is lower than the first doping concentration, and the fourth region is disposed above the third region and is doped with a third doping concentration that is higher than the first doping concentration; and annealing the resulting product formed with the landing
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: December 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyoung Bong Rouh
  • Patent number: 8318594
    Abstract: A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: November 27, 2012
    Assignee: Panasonic Corporation
    Inventors: Mitsuaki Oya, Toshiya Yokogawa, Atsushi Yamada, Akihiro Isozaki
  • Patent number: 8313996
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: November 20, 2012
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Gurtej Sandhu
  • Patent number: 8309993
    Abstract: A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the polysilicon layer and the active region are coupled through a buried contact structure.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: November 13, 2012
    Assignee: Intellectual Ventures II LLC
    Inventors: Woon-Il Choi, Hyung-Sik Kim, Ui-Sik Kim
  • Patent number: 8309448
    Abstract: Provided is a method for forming a buried word line in a semiconductor device. The method includes forming a trench by etching a pad layer and a substrate, forming a conductive layer to fill the trench, planarizing the conductive layer until the pad layer is exposed, performing an etch-back process on the planarized conductive layer, and performing an annealing process in an atmosphere of a nitride-based gas after at least one of the forming of the conductive layer, the planarizing of the conductive layer, and the performing of the etch-back process on the planarized conductive layer.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 13, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Sun-Hwan Hwang, Se-Aug Jang, Kee-Joon Oh, Soon-Young Park