Specified Aspect Ratio Of Conductor Or Viahole Patents (Class 438/668)
  • Patent number: 9034753
    Abstract: A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: May 19, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Till Schloesser, Peter Baars
  • Publication number: 20150123113
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the invention includes: an insulating substrate; a gate line disposed on the insulating substrate and including a gate pad portion; a data line insulated from and crossing the gate line, and including a source electrode and a data pad portion; a drain electrode facing the source electrode; an organic insulating layer disposed on the data line and the drain electrode, and including a first contact hole; a common electrode disposed on the organic insulating layer, and including a second contact hole; a passivation layer disposed on the common electrode, and including a third contact hole; and a pixel electrode disposed on the passivation layer, and being in contact with the drain electrode, in which the third contact hole is disposed to be adjacent to one surface of the first contact hole for improvement of an aperture ratio and a stable electrode connection.
    Type: Application
    Filed: May 19, 2014
    Publication date: May 7, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Seung Hyun PARK, Jun Ho SONG, Jean Ho SONG, Jae Hak LEE
  • Patent number: 9018094
    Abstract: A through via (144) contains a conductor (244, 276) passing through a substrate (140) for connection to an integrated circuit element. The through via consists of two segments (144.1, 144.2) formed from respective different sides (140.1, 140.2) of the substrate and meeting inside the substrate. Each segment is shorter than the entire via, so via formation is facilitated. The second segment is etched after deposition of an etch stop layer (214) into the first segment. Due to the etch stop layer, the first segment's depth does not have to be rigidly controlled. The conductor is formed by separate depositions of conductive material into the via from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the via depth, so the deposition is facilitated. Other embodiments are also provided.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: April 28, 2015
    Assignee: Invensas Corporation
    Inventors: Valentin Kosenko, Sergey Savastiouk
  • Patent number: 9006014
    Abstract: A method for fabricating three dimensional high surface electrodes is described. The methods including the steps: designing the pillars; selecting a material for the formation of the pillars; patterning the material; transferring the pattern to form the pillars; insulating the pillars and providing a metal layer for increased conductivity. Alternative methods for fabrication of the electrodes and fabrication of the electrodes using CMOS are also described.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 14, 2015
    Assignee: California Institute of Technology
    Inventors: Muhammad Mujeeb-U-Rahman, Axel Scherer
  • Patent number: 8987916
    Abstract: A method for increasing metal density around selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and increasing area of a metal layer which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Douglas M. Reber
  • Publication number: 20150076677
    Abstract: The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter, <1:1, preferably 1:1 to 2:1.
    Type: Application
    Filed: April 15, 2013
    Publication date: March 19, 2015
    Applicant: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Daniel Perttu
  • Patent number: 8940581
    Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: January 27, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Choon Kuan Lee, Chin Hui Chong, David J. Corisis
  • Patent number: 8940601
    Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Youichi Yamamoto, Masayuki Tachikawa, Yoshitake Kato
  • Patent number: 8927417
    Abstract: A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Weng Foong Yap
  • Patent number: 8916939
    Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hong Yu, Huang Liu
  • Patent number: 8907496
    Abstract: Circuit structures and methods of fabrication are provided with enhanced electrical connection between, for instance, a first metal level and a contact surface of a conductive structure. Enhanced electrical connection is achieved using a plurality of contact vias which are differently-sized, and disposed over and electrically coupled to the contact surface. The differently-sized contact vias include at least one center region contact via disposed over a center region of the contact surface, and at least one peripheral region contact via disposed over a peripheral region of the contact surface, where the at least one center region contact via is larger than the at least one peripheral region contact via.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: GuoXiang Ning, Xiang Hu, Sarasvathi Thangaraju, Paul Ackmann
  • Patent number: 8900996
    Abstract: A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yu Chen, Home-Been Cheng, Yu-Han Tsai, Ching-Li Yang
  • Patent number: 8896051
    Abstract: According to one embodiment, a semiconductor device includes a lower layer connection object, a stacked body, an insulating film, and a via. The stacked body has a plurality of insulating layers and a plurality of electrode layers alternately stacked on the lower layer connection object. The stacked body has a staircase structure unit. The via connects uppermost electrode layer at each step of the staircase structure unit and the lower layer connection object through the via hole. The via has an upper part provided on and in contact with a top face of the uppermost electrode layer, and a penetrating part provided to be thinner than the upper part inside the insulating film in the via hole. The penetrating part connects the upper part and the lower layer connection object.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nansei
  • Patent number: 8883629
    Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Robert G. Fleck
  • Publication number: 20140273444
    Abstract: A semiconductor device and method of manufacture are provided. The semiconductor device may include a multiple-patterned layer which may include multiple channels defined by multiple masks. A width of a first channel may be smaller than a width of a second channel. A conductor in the first channel may have a conductor width substantially equivalent to a conductor width of a conductor in the second channel. A spacer dielectric on a channel side may be included. The method of manufacture includes establishing a signal conductor layer including channels defined masks where a first channel may have a first width smaller than a second width of a second channel, introducing a spacer dielectric on a channel side, introducing a first conductor in the first channel having a first conductor width, and introducing a second conductor in the second channel having a second conductor width substantially equivalent to the first conductor width.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20140264782
    Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.
    Type: Application
    Filed: May 2, 2013
    Publication date: September 18, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: ZUSING YANG, FANG-HAO HSU, HONG-JI LEE
  • Publication number: 20140246777
    Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 4, 2014
    Applicant: International Business Machines Corporation
    Inventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
  • Publication number: 20140199835
    Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 17, 2014
    Applicant: XINTEC INC.
    Inventors: Yu-Lin YEN, Chien-Hui CHEN, Tsang-Yu LIU, Long-Sheng YEOU
  • Patent number: 8772930
    Abstract: A multilayer microelectronic device package includes one or more vertical electrical contacts. At least one semiconductor material layer is provided having one or more electrical devices fabricated therein. An electrical contact pad can be formed on or in the semiconductor material layer. Another material layer is positioned adjacent to the semiconductor material layer and includes a conductive material stud embedded in or bonded to the layer. A via is formed through at least a portion of the semiconductor material layer and the electrical contact pad and into the adjacent layer conducting material stud. The via is constructed such that the via tip terminates within the conducting material stud, exposing the conducting material. A metallization layer is disposed in the via such that the metallization layer contacts both the electrical contact pad and the conducting material stud exposed by the via tip.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: July 8, 2014
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Pui Chung Simon Law, Dan Yang, Xunqing Shi
  • Patent number: 8772163
    Abstract: A semiconductor processing method that can generate a hole with different diameters, comprising: providing first material and second material different from the first material; and utilizing a etching process to etch the first material and the second material to form a hole through the first material and the second material; wherein the etching process has different etching rates for the first material and the second material such that the hole have different diameters. A semiconductor structure corresponding to the above-mentioned method is also disclosed.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: July 8, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Dennis J. Pretti, Terrence B. McDaniel
  • Patent number: 8728933
    Abstract: A method of kerf formation and treatment for solar cells and semiconductor films and a system therefor are described. A semiconductor film is backed by a first metal layer and topped by a second metal layer. A reference feature is defined on the film. An ultraviolet laser beam is aligned to the reference feature. A kerf is cut along the reference feature, using the ultraviolet laser beam. The beam cuts through the second metal layer, through the film and through the first metal layer. Cutting leaves debris deposited on walls of the kerf. The debris is cleaned off of the walls, using an acid-based solvent. In the case of solar cells, respective first terminals of the solar cells are electrically isolated by the cleaned kerf, and respective negative terminals of the solar cells are electrically isolated by the cleaned kerf.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 20, 2014
    Assignee: Alta Devices, Inc.
    Inventors: Michael Andres, Laila Mattos, Daniel G. Patterson, Gang He
  • Patent number: 8723049
    Abstract: A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: May 13, 2014
    Assignee: Tessera, Inc.
    Inventors: Charles G. Woychik, Kishor Desai, Ilyas Mohammed, Terrence Caskey
  • Patent number: 8722533
    Abstract: A manufacturing method of a semiconductor device includes forming a structure comprising an interlayer dielectric layer on a substrate, an ultra-low-k material layer on the interlayer dielectric layer and a plug. The plug passes through the interlayer dielectric layer and the ultra-low-k material layer, and is formed of a first metal material. The method further includes removing an upper portion of the plug by etching to form a recessed portion, and filling the recessed portion with a second metal material. According to the method, contact-hole photolithography is performed only once, and thus avoids alignment issues that may occur when contact-hole photolithography needs to be performed twice.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Zhongshan Hong
  • Patent number: 8716126
    Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Peter Baars, Frank Feustel
  • Publication number: 20140117563
    Abstract: A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 1, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo
  • Patent number: 8709946
    Abstract: A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: April 29, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Meng-Feng Tsai, Yi-Shiang Chang, Chia-Chi Lin, I-Hsin Chen, Chia-Ming Wu
  • Patent number: 8697574
    Abstract: Through substrate features in semiconductor substrates are described. In one embodiment, the semiconductor device includes a through substrate via disposed in a first region of a semiconductor substrate. A through substrate conductor coil is disposed in a second region of the semiconductor substrate.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: April 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gunther Mackh, Uwe Seidel, Rainer Leuschner
  • Patent number: 8686519
    Abstract: A MEMS accelerometer uses capacitive sensing between two electrode layers. One of the electrode layers has at least four independent electrodes arranged as two pairs of electrodes, with one pair aligned orthogonally to the other such that tilting of the membrane can be detected as well as normal-direction movement of the membrane. In this way, a three axis accelerometer can be formed from a single suspended mass, and by sensing using a set of capacitor electrodes which are all in the same plane. This means the fabrication is simple and is compatible with other MEMS manufacturing processes, such as MEMS microphones.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: April 1, 2014
    Inventors: Geert Langereis, Iris Bominaar-Silkens, Twan Van Lippen
  • Patent number: 8637401
    Abstract: A method is explained that allows for a via to be filled with a dispensed material while the substrate is in continuous movement. A device is described that allows for a via to be filled while the target substrate is in continuous movement. The device consists of a material jetting system, a machine vision system that can detect the optimum trigger point, an electronic control circuit, a feedback mechanism and a web handling provision.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: January 28, 2014
    Inventors: Anthony Nicholas Brady Garvan, III, Christoph Erben, Darren Lochun
  • Patent number: 8617990
    Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Mihir K. Roy
  • Patent number: 8604621
    Abstract: A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
  • Patent number: 8580682
    Abstract: A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Yang, Yung-Chi Lin, Hung-Pin Chang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 8569888
    Abstract: Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Jeffrey P. Gambino, Anthony K. Stamper, Timothy D. Sullivan
  • Patent number: 8557699
    Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: October 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Tsurume, Yoshitaka Dozen
  • Patent number: 8558390
    Abstract: According to one embodiment, provided is a semiconductor device including a lower layer wiring, and an upper layer wiring that is drawn in the same direction as a direction in which the lower layer wiring is drawn. Intermediate wirings include at least a first intermediate wiring and a second intermediate wiring. Conductors include at least a plurality of first conductors connecting between the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting between the upper layer wiring and the second intermediate wiring, and a plurality of third conductors which connect between the first intermediate wiring and the second intermediate wiring, and are less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Wakita, Shigeyuki Hayakawa
  • Patent number: 8552565
    Abstract: A chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located under the lower surface of the substrate, and a dielectric layer located between the conducting pads. A hole is provided in the substrate, which extends from the upper surface towards the lower surface of the substrate. A sidewall or a bottom of the hole exposes a portion of the conducting pads. The upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface. An upper conducting pad has at least an opening or a trench exposing a lower conducting pad of the conducting pads. A conducting layer is disposed in the hole, which electrically contacting at least one of the conducting pads.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 8, 2013
    Inventors: Yu-Lin Yen, Chien-Hui Chen, Tsang-Yu Liu, Long-Sheng Yeou
  • Publication number: 20130258265
    Abstract: An array substrate structure including a first substrate, a plurality of thin film transistors, a first dielectric layer, a second dielectric layer, and a second electrode layer is provided. Each of the thin film transistors has a patterned first electrode layer which is disposed on the first electrode layer and has a first through hole. The second dielectric layer is disposed on the first dielectric layer and has a second through hole. The second through hole is connected to the first through hole, such that the second electrode layer is electrically connected to the first electrode layer via the first through hole and the second through hole.
    Type: Application
    Filed: March 18, 2013
    Publication date: October 3, 2013
    Applicant: INNOLUX CORPORATION
    Inventors: Yu-Tsung Liu, Te-Yu Lee
  • Publication number: 20130228848
    Abstract: According to one embodiment, a semiconductor device includes a lower layer connection object, a stacked body, an insulating film, and a via. The stacked body has a plurality of insulating layers and a plurality of electrode layers alternately stacked on the lower layer connection object. The stacked body has a staircase structure unit. The via connects uppermost electrode layer at each step of the staircase structure unit and the lower layer connection object through the via hole. The via has an upper part provided on and in contact with a top face of the uppermost electrode layer, and a penetrating part provided to be thinner than the upper part inside the insulating film in the via hole. The penetrating part connects the upper part and the lower layer connection object.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki NANSEI
  • Patent number: 8522430
    Abstract: A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.
    Type: Grant
    Filed: July 14, 2012
    Date of Patent: September 3, 2013
    Assignee: International Business Macines Corporation
    Inventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
  • Patent number: 8519538
    Abstract: The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: August 27, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Ching-Hua Chiu, Troy Wu
  • Patent number: 8487439
    Abstract: A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 16, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Tani, Takami Hirai, Shinsuke Yano, Tsutomu Nanataki
  • Patent number: 8455357
    Abstract: A method of plating via hole in a substrate includes providing a substrate having a first side and a second side and a plurality of through substrate via holes; depositing a first seed layer on the first side of the substrate; applying a foil on the first seed layer of the substrate closing the first ends of the plurality of via holes; electro-chemical plating of the second side of the substrate; and removing the foil.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: June 4, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Willem Frederik Adrianus Besling, Freddy Roozeboom, Yann Pierre Roger Lamy
  • Patent number: 8445298
    Abstract: A process includes preparing a base material having a first surface provided with an element generating energy that is used for discharging a liquid and an electrode layer that is connected to the element; forming a hollow on a second surface, which is the surface on the opposite side of the first surface, of the base material, wherein part of the electrode layer serves as the bottom face of the hollow; covering the surface of the base material and the bottom face forming the inner face of the hollow with an insulating film; and partially exposing the electrode layer by removing part of the insulating film covering the bottom face using laser light.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: May 21, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Souta Takeuchi, Masaya Uyama, Hirokazu Komuro
  • Patent number: 8436473
    Abstract: An integrated circuit includes an interconnect structure at least partially disposed in at least one opening of a dielectric layer that is disposed over a substrate. At least one air gap is disposed between the dielectric layer and the interconnect structure. At least one first liner material is disposed under the at least one air gap. At least one second liner material is disposed around the interconnect structure. The at least one first liner material is disposed between the dielectric layer and at least one second liner material.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: May 7, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ping Chen, Chih-Hao Chen
  • Patent number: 8421234
    Abstract: A semiconductor device according to an embodiment of the present invention includes a substrate, isolation layers and active regions formed in the substrate, and arranged alternately along a first direction parallel to a surface of the substrate, an inter layer dielectric formed on the isolation layers and the active regions, and having holes for respective contact plugs on the respective active regions, barrier layers formed in the holes, each of the barrier layers being formed on a top surface of an active region exposed in a hole and on one of two side surfaces of the hole, the two side surfaces of the hole being perpendicular to the first direction, and plug material layers formed on the barrier layers in the holes.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyohito Nishihara
  • Patent number: 8415178
    Abstract: A process includes preparing a base material having a first surface provided with an element generating energy that is used for discharging a liquid and an electrode layer that is connected to the element; forming a hollow on a second surface, which is the surface on the opposite side of the first surface, of the base material, wherein part of the electrode layer serves as the bottom face of the hollow; covering the surface of the base material and the bottom face forming the inner face of the hollow with an insulating film; and partially exposing the electrode layer by removing part of the insulating film covering the bottom face using laser light.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: April 9, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Souta Takeuchi, Masaya Uyama, Hirokazu Komuro
  • Publication number: 20130082401
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 4, 2013
    Applicant: SONY CORPORATION
    Inventor: Masanaga Fukasawa
  • Patent number: 8399352
    Abstract: When forming metal lines of the metal zero level, a reduced bottom width and an increased top width may be achieved by using appropriate patterning regimes, for instance using a spacer structure after forming an upper trench portion with a top width, or forming the lower portion of the trenches and subsequently applying a further mask and etch regime in which the top width is implemented. In this manner, metal lines connecting to self-aligned contact bars may be provided so as to exhibit a bottom width of 20 nm and less, while the top width may allow reliable contact to any vias of the metallization system.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 19, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Peter Baars, Frank Feustel
  • Patent number: 8378496
    Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: February 19, 2013
    Assignee: austriamicrosystems AG
    Inventors: Franz Schrank, Martin Schrems, Jochen Kraft
  • Patent number: 8329582
    Abstract: A semiconductor device comprises insulating layer including damascene patterns and formed over a semiconductor substrate, conductive line formed higher than the insulating layer within the respective damascene patterns, and interference-prevention grooves formed within the damascene patterns between sidewalls of the conductive line and the insulating layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae Kyung Kim