Abstract: A dry etching device which can be used to etch products or used in processes regardless of materials and exhibits an excellent accuracy, and a method for controlling the same. The dry etching device includes: an anode part; a cathode part disposed at an upper side of the anode part and facing the anode part, receiving bi-directional voltage power in which polarity of a voltage alternates between a positive voltage and a negative voltage depending on time, and spaced apart from the anode part; a leveling part disposed in close contact with a surface of the cathode part facing the anode part, and for positioning a work-piece in a flat state; a holding part for holding the work-piece and the leveling part to the surface of the cathode part facing the anode part; and a bi-directional voltage power supplier for applying the bi-directional voltage power to the cathode part.

Abstract: The present invention relates to a dry etching apparatus which can be applied regardless of materials. The dry etching apparatus may include: an anode unit; a cathode unit configured to receive a bidirectional voltage source of which the voltage polarity alternates between a positive voltage and a negative voltage with time, and separated from the anode unit; a positioning unit configured to position a work piece at a surface of the cathode unit, facing the anode unit; and a bidirectional voltage source supply unit configured to apply the bidirectional voltage source to the cathode unit.

Abstract: A low temperature deposited (400° C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.

Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.

Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.

Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.

Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate.

Abstract: A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Abstract: Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Abstract: A method for producing semiconductor components on a substrate including photolithographic patterning steps, in which method, on the substrate, a first layer to be patterned is applied and a second layer serving as a mask layer for the first layer to be patterned is applied, wherein a third layer serving as a mask for the second layer is applied, and wherein at least two photolithographic patterning processes are carried out successively for the second layer, wherein, during one of the patterning processes, after the production of a structure made from a photosensitive layer for the provision of a mask layer for a patterning process at the third layer, positive ramp angles ? are produced at the patterning edges of the third layer, as a result of which the structures remaining free, given a thickness h of the third layer, decrease in size by a value D=2*h/tan ?.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.

Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.

Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.

Abstract: A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

Abstract: A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied.

Abstract: A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Abstract: A structure. The structure includes: a hole layer; a hole layer including a top hole layer surface, wherein the hole layer has a thickness in a first direction that is perpendicular to the hole layer surface; a bottom antireflective coating (BARC) layer on and in direct physical contact with the hole layer at the top hole layer surface; a photoresist layer on and in direct physical contact with the BARC layer, wherein a continuous hole in the first direction extends completely through the photoresist layer, the BARC layer, and the hole layer; and a polymerized hole shrinking region in direct physical contact with the photoresist layer at a lateral surface of the photoresist layer and with the hole layer at the top hole layer surface, wherein the hole shrinking region does not extend below the hole layer surface in a direction from the BARC layer to the hole layer.

Abstract: In high frequency circuits, the switching speed of devices is often limited by the series resistance and capacitance across the input terminals. To reduce the resistance and capacitance, the cross-section of input electrodes is made into a T-shape or inverted L-shape through lithography. The prior art method for the formation of cavities for T-gate or inverted L-gate is achieved through several steps using multiple photomasks. Often, two or even three different photoresists with different sensitivity are required. In one embodiment of the present invention, an optical lithography method for the formation of T-gate or inverted L-gate structures using only one photomask is disclosed. In another embodiment, the structure for the T-gate or inverted L-gate is formed using the same type of photoresist material.

Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.

Abstract: The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.

Abstract: In sophisticated metallization systems, vertical contacts and metal lines may be formed on the basis of a dual inlaid strategy, wherein an edge rounding or corner rounding may be applied to the trench hard mask prior to forming the via openings on the basis of a self-aligned via trench concept. Consequently, self-aligned interconnect structures may be obtained, while at the same time providing superior fill conditions during the deposition of barrier materials and conductive fill materials.

Abstract: A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided.

Abstract: A method for forming a through silicon via (TSV) in a substrate may include forming a dielectric layer on the substrate; forming an opening through the dielectric layer and into the substrate using a single mask over the dielectric layer; expanding the opening in the dielectric layer, undercutting the single mask, to form an expanded upper portion; removing the single mask; and filling the opening, including the expanded upper portion, with a conductor. A resulting structure may include a substrate; a dielectric layer over the substrate; and a self-aligned through silicon via (TSV) extending through the dielectric layer and the substrate.

Abstract: A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied.

Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

Abstract: A semiconductor light emitting device has a light emitting element, a first electrode layer, a second electrode layer, a seed electrode layer and a plated layer. The light emitting element has a nitride-based III-V compound semiconductor on a substrate. The light emitting element having a light extraction surface. The first electrode layer on the light extraction surface. The second electrode layer is provided on a surface opposite to the light extraction surface of the light emitting element. The seed electrode layer is configured to cover the entire surface of the second electrode layer. The plated layer is provided on the seed electrode layer. The light emitting element has a light emitting layer, a first conductive type semiconductor layer, and a second conductive type semiconductor layer.

Abstract: In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.

Abstract: The invention relates to a method of providing a planar substrate with electrical through connections (vias). The method comprises providing a hole in said substrate and a treatment to render the substrate surface exhibiting a lower wettability than the walls inside the hole. The planar substrate is exposed to a molten material with low resistivity, whereby the molten material is drawn into the hole(s). It also relates to a semiconductor wafer as a starting substrate for electronic packaging applications, comprising low resistivity wafer through connections having closely spaced vias.

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Abstract: Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.

Abstract: A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.

Abstract: Provided are a three-dimensional (3D) interconnection structure and a method of manufacturing the same. The 3D interconnection structure includes a wafer that has one side of an inverted V-shape whose middle portion is convex and a lower surface having a U-shaped groove for mounting a circuit, and a first electrode formed to cover a part of the inverted V-shaped one side of the wafer and a part of the U-shaped groove.

Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.

Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.

Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.

Abstract: According to one embodiment, a method is described for manufacturing a semiconductor device. The method can form a conductive layer including tungsten on a foundation layer. The method can form a trench by selectively etching the conductive layer. The trench is shallower than a depth from a surface of the conductive layer to the foundation layer. The method can form a protective film on a side surface and a bottom surface of the conductive layer in the trench using a gas containing bromine. The protective film includes a compound of the tungsten and the bromine. The method can remove the protective film on the bottom surface of the conductive layer. The method can etch a portion of the conductive layer below the trench with the protective film on the side surface of the conductive layer.

Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.

Abstract: A structure and a method for forming the same. The method comprises providing a structure including (a) a hole layer, (b) a BARC (bottom antireflective coating) layer on the top of the hole layer, and (c) a patterned photoresist layer on top of the BARC layer and having a photoresist hole; etching the BARC layer through the photoresist hole to extend the photoresist hole to the hole layer; performing the chemical shrinking process to shrink the extended photoresist hole; and etching the hole layer through the shrunk, extended photoresist hole so as to form a hole in the hole layer.

Abstract: A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios.

Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.

Abstract: A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.

Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.

Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Abstract: Provided are a display substrate, a liquid crystal display (LCD) including the display substrate, and a method of manufacturing the display substrate. The display substrate includes: an insulating substrate; a gate wiring formed on the insulating substrate and extending generally in a first direction; a data wiring which is insulated from the gate wiring, intersects the gate wiring, and which extends generally in a second direction; a pixel electrode formed in a pixel region defined by the gate wiring and the data wiring; and a storage wiring which is formed on the same layer as the gate wiring, is overlapped by the data wiring to be insulated from the data wiring, and which extends generally in the second direction, wherein each of the gate wiring and the storage wiring has a tapered surface oriented generally at an inclination angle of approximately 30 degrees or less with respect to the insulating substrate.

Abstract: A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the multilayered wiring is composed of an alloy having copper as a principal component. The concentration of at least one metallic element contained in the alloy as an added component in vias of the dual damascene wiring is determined according to the differences in the width of the wiring of an upper layer where the vias are connected. Specifically, a larger wiring width in the upper layer corresponds to a higher concentration of at least one metallic element within the connected vias. Accordingly, increases in the resistance of the wiring are minimized, the incidence of stress-induced voids is reduced, and reliability can be improved.

Abstract: The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.

Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.

Abstract: A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than ?200 nm, a conductive layer being present on at least a portion of said surface, (b) filling said recessed feature with a conductive material, and (c) prior to filling said recessed feature with said conductive material, treating said surface with an accelerator.