Utilizing Chemical Vapor Deposition (i.e., Cvd) Patents (Class 438/680)
  • Patent number: 7384833
    Abstract: In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: June 10, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Igor Polishchuk, Krishnaswamy Ramkumar, Sagy Charel Levy
  • Patent number: 7384867
    Abstract: Methods for the deposition of tungsten films are provided. The methods include depositing a nucleation layer by alternatively adsorbing a tungsten precursor and a reducing gas on a substrate, and depositing a bulk layer of tungsten over the nucleation layer.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: June 10, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Ken K. Lai, Jeong Soo Byun, Frederick C. Wu, Ramanujapuran A. Srinivas, Avgerinos Gelatos, Mei Chang, Moris Kori, Ashok K. Sinha, Hua Chung, Hongbin Fang, Alfred W. Mak, Michael X. Yang, Ming Xi
  • Publication number: 20080132069
    Abstract: An apparatus and a method form a thin layer on each of multiple semiconductor substrates. A processing chamber of the apparatus includes a boat in which the semiconductor substrates are arranged in a vertical direction. A vaporizer vaporizes a liquid metal precursor into a metal precursor gas. A buffer receives a source gas from the vaporizer and increases a pressure of the source gas to higher than atmospheric pressure, the source gas including the metal precursor gas. A first supply pipe connects the buffer and the processing chamber, the first supply pipe including a first valve for controlling a mass flow rate of the source gas. A second supply pipe connects the vaporizer and a pump for creating a vacuum inside the processing chamber, the second supply pipe including a second valve for exhausting a dummy gas during an idling operation of the vaporizer.
    Type: Application
    Filed: September 18, 2007
    Publication date: June 5, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Wook LEE, Wan-Goo HWANG, Bu-Cheul LEE, Jeong-Soo SUH, Sung-Il HAN, Seong-Ju CHOI
  • Publication number: 20080124924
    Abstract: Embodiments of the present invention generally relate to methods and apparatuses using supercritical fluids and/or dense fluids to deposit a metal material on the surface of a substrate. In one embodiment, a metal material layer is deposited by applying a supercritical fluid, a dense fluid, or combinations thereof and a metal-containing precursor to the surface of a substrate inside a substrate processing chamber. In another embodiment, a first metal material and a second metal material is sequentially deposited and annealing is performed to form a metal alloy material on the surface of a substrate. In still another embodiment, a copper material layer is deposited by applying a supercritical fluid, a dense fluid, or combinations thereof and a copper containing precursor to the surface of the substrate.
    Type: Application
    Filed: July 18, 2006
    Publication date: May 29, 2008
    Inventor: Mehul Naik
  • Patent number: 7378328
    Abstract: A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: May 27, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-bong Choi, In-kyeong Yoo, Jae-uk Chu
  • Patent number: 7371683
    Abstract: A method for carrying an object to be processed used for a processing apparatus which comprises a plurality of process chambers including a specific process chamber for a process in which the object in process is easily contaminated and a carrying mechanism having two picks. The method includes a plurality of carrying steps wherein the object in process is sequentially carried from one chamber to another among the plurality of process chambers. One of the two picks is used in carrying steps up right before carrying the object into the specific process chamber, and the other pick is used in the step of carrying the object into the specific process chamber and the later carrying steps.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: May 13, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Ishizawa, Eiji Horike
  • Patent number: 7371586
    Abstract: A superconductor and a method for producing the same are provided. The method for producing a superconductor includes the step of forming a superconducting layer on a base layer by performing a film deposition at least three times, wherein the film thickness of a superconducting film in each film deposition is 0.3 ?m or less. In such a case, even when the layer thickness of the superconducting layer is increased, the decrease in the Jc is suppressed and the Ic is increased.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: May 13, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shuji Hahakura, Kazuya Ohmatsu
  • Patent number: 7368381
    Abstract: The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the chamber. The mixture includes a precursor of a desired material within a supercritical fluid. The precursor is relatively reactive under one set of conditions and is relatively non-reactive under another set of conditions. The precursor and supercritical fluid mixture is initially provided in the chamber under the conditions at which the precursor is relatively non-reactive. Subsequently, and while maintaining the supercritical state of the supercritical fluid, the conditions within the reaction chamber are changed to the conditions under which the precursor is relatively reactive. The precursor reacts to form the desired material, and at least some of the desired material forms a film on the substrate.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J Derderian, Cem Basceri
  • Patent number: 7368382
    Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Patent number: 7368368
    Abstract: In one embodiment the present invention is a method of conducting multiple step multiple chamber chemical vapor deposition while avoiding reactant memory in the relevant reaction chambers. The method includes depositing a layer of semiconductor material on a substrate using vapor deposition in a first deposition chamber followed by evacuation of the growth chamber to reduce vapor deposition source gases remaining in the first deposition chamber after the deposition growth and prior to opening the chamber. The substrate is transferred to a second deposition chamber while isolating the first deposition chamber from the second deposition chamber to prevent reactants present in the first chamber from affecting deposition in the second chamber and while maintaining an ambient that minimizes or eliminates growth stop effects. After the transferring step, an additional layer of a different semiconductor material is deposited on the first deposited layer in the second chamber using vapor deposition.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: May 6, 2008
    Assignee: Cree, Inc.
    Inventor: David Todd Emerson
  • Patent number: 7368359
    Abstract: A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking oxygen on the major surface, performing annealing, and then stripping off the mask and the surface protection layer. A silicon dioxide layer (102) has a first tip surface (102a) corresponding to an area where the mask has not existed and having a relatively long distance from the major surface (100a), and a second top surface (102b) corresponding to an area where the mask has existed and having a relatively short distance from the major surface (100a). As this major surface (100a) is polished by a predetermined quantity, a semiconductor substrate is provided in which only a part of a single-crystal silicon substrate is a SOI substrate.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: May 6, 2008
    Assignees: Sony Corporation, Regents of the University of California
    Inventors: Koichiro Kishima, Prakash Koonath
  • Patent number: 7368384
    Abstract: A method of using a film formation apparatus for a semiconductor process includes a step of removing a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus. This step is performed while supplying a cleaning gas containing hydrogen fluoride into the reaction chamber, and forming a first atmosphere within the reaction chamber, which allows water to be present as a liquid film.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: May 6, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Atsushi Endo, Tomonori Fujiwara, Yuichiro Morozumi, Katsushige Harada, Shigeru Nakajima, Dong-Kyun Choi, Haruhiko Furuya, Kazuo Yabe
  • Publication number: 20080099820
    Abstract: A technique to form metallic nanodots in a two-step process involving: (1) reacting a silicon-containing gas precursor (e.g., silane) to form silicon nuclei over a dielectric film layer; and (2) using a metal precursor to form metal nanodots where the metal nanodots use the silicon nuclei from step (1) as nucleation points. Thus, the original silicon nuclei are a core material for a later metallic encapsulation step. Metallic nanodots have applications in devices such as flash memory transistors.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 1, 2008
    Applicant: ATMEL CORPORATION
    Inventors: Romain Coppard, Sylvie Bodnar
  • Publication number: 20080102613
    Abstract: Metallic-compound films are formed by plasma-enhanced atomic layer deposition (PEALD). According to preferred methods, film or thin film composition is controlled by selecting plasma parameters to tune the oxidation state of a metal (or plurality of metals) in the film. In some embodiments, plasma parameters are selected to achieve metal-rich metallic-compound films. The metallic-compound films can be components of gate stacks, such as gate electrodes. Plasma parameters can be selected to achieve a gate stack with a predetermined work function.
    Type: Application
    Filed: November 1, 2006
    Publication date: May 1, 2008
    Inventor: Kai-Erik Elers
  • Patent number: 7365014
    Abstract: We have reduced the critical dimension bias for reticle fabrication. Pattern transfer to the radiation-blocking layer of the reticle substrate essentially depends upon use of a hard mask to which the pattern is transferred from a photoresist. The photoresist pull back which occurs during pattern transfer to the hard mask is minimalized. In addition, a hard mask material having anti-reflective properties which are matched to the reflective characteristics of the radiation-blocking layer enables a reduction in critical dimension size and an improvement in the pattern feature integrity in the hard mask itself. An anti-reflective hard mask layer left on the radiation-blocking layer provides functionality when the reticle is used in a semiconductor device manufacturing process.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 29, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Christopher Dennis Bencher, Melvin Warren Montgomery, Alexander Buxbaum, Yung-Hee Yvette Lee, Jian Ding, Gilad Almogy, Wendy H. Yeh
  • Patent number: 7361595
    Abstract: A semiconductor substrate is placed in a predetermined processing vessel, and oxygen gas activated by, e.g. conversion into a plasma is supplied onto an insulating film. The surfaces of an interlevel insulating film and insulating film are exposed to the activated oxygen gas. After that, a transition metal film, e.g. a ruthenium film, is formed by CVD.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: April 22, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Hideaki Yamasaki, Susumu Arima, Yumiko Kawano
  • Patent number: 7358191
    Abstract: According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: April 15, 2008
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Brad Davis, James Xie, Kashmir Sahota
  • Patent number: 7358197
    Abstract: The method for avoiding polysilicon film over etch abnormal includes cleaning a semiconductor substrate. A dielectric layer is formed on the substrate. Subsequently, a first silicon source gas at a first flow rate is next performed injecting into a reaction chamber to form a first polysilicon film over the dielectric layer. Successively, a second silicon source gas at a second flow rate is performed injecting into the reaction chamber to form a second polysilicon film over the first polysilicon film, wherein the second silicon source gas having a different growth rate than the first silicon source gas. A patterned photoresist layer is then formed on the second polysilicon film. After the patterned photoresist layer is formed, a dry etching process by way of using the patterned photoresist layer as a etching mask is performed to etch through in turn the second polysilicon film and the first polysilicon film till exposing to the dielectric layer. Finally, the photoresist layer is removed.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: April 15, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Bruce Han, Jen-Tsung Lin, Kuo-Ping Huang
  • Patent number: 7358187
    Abstract: The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height (205), a catalyst layer (201) is introduced into the trenches (106) that are to be filled, a reaction layer (202) is deposited catalytically in the trenches (106) that are to be filled, the catalytically deposited reaction layer (202) is densified in the trenches (106) that are to be filled, and the introduction of the catalyst layer (201) and the catalytic deposition of the reaction layer (202) are repeated until the trenches (106) that are to be filled have been filled to the predetermined filling height (205).
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: April 15, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Hecht, Stefan Jakschik, Uwe Schröder
  • Patent number: 7354873
    Abstract: A method for forming an insulation film having filling property on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma CVD processing; and forming an insulation film constituted by Si, O, H, and optionally C or N on a substrate by plasma reaction using a combination of low-frequency RF power and high-frequency RF power in the reaction space. The plasma reaction is activated while controlling the flow of the reaction gas to lengthen a residence time, Rt, of the reaction gas in the reaction space.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: April 8, 2008
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Nobuo Matsuki, Seijiro Umemoto
  • Publication number: 20080081470
    Abstract: A method for forming a strained SiN film and a semiconductor device containing the strained SiN film. The method includes exposing the substrate to a gas including a silicon precursor. The substrate is exposed to a gas including a first nitrogen precursor configured to react with the silicon precursor with a first reactivity characteristic. The substrate is also exposed to a gas including a second nitrogen precursor configured to react with the silicon precursor with a second reactivity characteristic different than the first reactivity characteristic such that a property of the SiN film formed on the substrate changes to provide a strained SiN film. According to another embodiment, the substrate is exposed to a gas pulse containing a silicon precursor and first and second nitrogen precursors, wherein the ratio of the first and second precursors is varied during the exposure.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Robert D. Clark
  • Patent number: 7351668
    Abstract: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding or oxynitriding gas, and a third process gas containing a carbon hydride gas. This method alternately includes first to fourth steps. The first step performs supply of the first and third process gases to the field while stopping supply of the second process gas to the process field. The second step stops supply of the first to third process gases to the field. The third step performs supply of the second process gas to the field while stopping supply of the first and third process gases to the field. The fourth step stops supply of the first to third process gases to the field.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: April 1, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Pao-Hwa Chou, Kazuhide Hasebe
  • Patent number: 7344982
    Abstract: A chemical vapor deposition reaction system converts a reactant precursor, which includes the metal Ruthenium, to a vapor during a chemical reaction in order to deposit the metal on a semiconductor wafer. The reactant precursor is Bis(2,2,6,6-tetramethyl-3,5-heptanedionato)(1,5-cyclooctadiene)Ru. An energy source provides energy to the reaction chamber to induce the chemical reaction. A controllable metering system alternatively supplies the precursor and oxygen to the reaction chamber. The precursor is supplied into the reaction chamber during a first phase and the oxygen is supplied into the reaction chamber during a second phase, which is non-overlapping with the first phase. A first pump/valve provides the precursor to the reaction chamber, and a second pump/valve provides the oxygen to the reaction chamber, each in response to a controller. The Ruthenium is selectively deposited on oxide sites patterned on a surface of the semiconductor wafer.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: March 18, 2008
    Assignee: Arizona Board of Regents, acting for and on behalf of Arizona State University
    Inventors: Jaydeb Goswami, Sandwip Kumar Dey
  • Patent number: 7344974
    Abstract: A method for forming a metallization contact in a semiconductor device includes the steps of: (a) forming an insulating layer on a semiconductor substrate including an active device region; (b) forming a contact hole to expose a portion of the active device region by etching a portion of the insulating layer; (c) forming a CVD TiN layer on the insulating layer and inside the contact hole; (d) forming a PVD TiN layer on the CVD TiN layer using ionized metal plasma sputtering; and (e) forming a metal layer on the PVD TiN layer.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: March 18, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jung Joo Kim
  • Patent number: 7344983
    Abstract: A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: March 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Sadanand V. Deshpande, Ying Li, Kevin E. Mello, Renee T. Mo, Wesley C. Natzle, Kirk D. Peterson, Robert J. Purtell
  • Patent number: 7338901
    Abstract: A method for forming a thin film on a substrate layer by layer using plasma enhanced atomic layer deposition is described. The method comprises using a low power reduction step for at least one cycle in order to substantially avoid partial layer film growth, followed by using a high power reduction step for each cycle thereafter in order to increase deposition rate.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: March 4, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Tadahiro Ishizaka
  • Patent number: 7338887
    Abstract: A method that controls the distribution of plasma generated in a vacuum chamber, for example, as part of a plasma thin film deposition or plasma etching process. For thin film deposition, the method serves to minimize variations in film thickness caused by the variations of the film deposition conditions. The vacuum chamber includes a high-frequency-wave electrode connected to a high-frequency electric power supply and an earth electrode connected to ground potential. High frequency-electric power is fed to the high-frequency-wave electrode and peak-to peak voltages are measured at multiple measuring points on one of the two electrodes. The distribution of the plasma is controlled by adjusting the chamber pressure to minimize the differences between the measured peak-to-peak voltages.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: March 4, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Makoto Shimosawa
  • Patent number: 7338900
    Abstract: A method for forming a tungsten nitride film including a first material gas supply step of supplying a first material gas composed of a tungsten compound gas, a reduction step of supplying a reducing gas, a second material gas supply step of supplying a second material gas composed of a tungsten compound gas, and a nitridation step of supplying a nitriding gas. Since a step of depositing tungsten on a substrate 5, and a step of forming tungsten nitride are performed separately, by varying the flow rate of each gas, the pressure when each gas is supplied, and the supply time, or the number of times each step is performed and the order in which the steps are performed, the quantity of tungsten deposited and the quantity of tungsten nitride formed can be controlled easily.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: March 4, 2008
    Assignee: Ulvac Inc.
    Inventors: Eiichi Mizuno, Narishi Gonohe, Masamichi Harada, Nobuyuki Kato
  • Publication number: 20080048345
    Abstract: A semiconductor device that allows an image sensor (in an upper area of a SiP semiconductor device) to exchange signals with a device in a lower area of a SiP semiconductor device. A semiconductor device includes at least one of: A semiconductor substrate having a photodiode area and a transistor area. A PMD (Pre Metal Dielectric) layer formed on and/or over the semiconductor substrate. At least one metal layers formed on and/or over the PMD layer. A first penetrating electrode penetrating the PMD layer and the at least one metal layers. A second penetrating electrode penetrating the semiconductor substrate and connected to the first penetrating electrode.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 28, 2008
    Inventor: Jae-Won Han
  • Patent number: 7332425
    Abstract: The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 110. RF plasma etching of the barrier material 200 that is deposited in the opening 140 occurs simultaneously with conducting the physical vapor deposition of the barrier material 200.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: February 19, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Asad M. Haider, Alfred J. Griffin, Jr., Kelly J. Taylor
  • Publication number: 20080038920
    Abstract: A chemical vapor deposition reaction system converts a reactant precursor, which includes the metal Ruthenium, to a vapor during a chemical reaction in order to deposit the metal on a semiconductor wafer. The reactant precursor is Bis(2,2,6,6-tetramethyl-3,5-heptanedionato)(1,5-cyclooctadiene)Ru. An energy source provides energy to the reaction chamber to induce the chemical reaction. A controllable metering system alternatively supplies the precursor and oxygen to the reaction chamber. The precursor is supplied into the reaction chamber during a first phase and the oxygen is supplied into the reaction chamber during a second phase, which is non-overlapping with the first phase. A first pump/valve provides the precursor to the reaction chamber, and a second pump/valve provides the oxygen to the reaction chamber, each in response to a controller. The Ruthenium is selectively deposited on oxide sites patterned on a surface of the semiconductor wafer.
    Type: Application
    Filed: November 23, 2004
    Publication date: February 14, 2008
    Inventors: Jaydeb Goswami, Sandwip Kumar Dey
  • Patent number: 7329947
    Abstract: When a two-division structure heat treatment jig for semiconductor substrate that includes a silicon first jig that comes into direct contact with a semiconductor substrate that is heat treated and supports the semiconductor substrate, and a second jig (holder) that holds the first jig and is mounted on a heat treatment boat is adopted as a heat treatment boat of a vertical heat treatment furnace, the stress concentrated during the heat treatment on a particular portion of the semiconductor substrate can be reduced; in the case of a semiconductor substrate large in the tare stress and having an outer shape of 300 mm being heat treated, or even in the case of the heat treatment being carried out under very high temperature conditions, the slips can be suppressed from occurring. The present invention can be widely applied as a stable heat treatment method of semiconductor substrates.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: February 12, 2008
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Naoshi Adachi, Kazushi Yoshida, Yoshiro Aoki
  • Publication number: 20080032502
    Abstract: A semiconductor processing apparatus comprises a pyrophoric source vessel within an enclosure, the vessel containing a pyrophoric material. An air intake labyrinth extends away from the enclosure and has an inlet and an outlet. The inlet is in fluid communication with an exterior of the enclosure, and the outlet is in fluid communication with an interior of the enclosure. The labyrinth defines a tortuous path between the inlet and the outlet. In order to thermally isolate the enclosure, it can be surrounded by an air gap of at least 10 mm separating the enclosure from other components of the processing apparatus, to prevent damage to such other components. The thermal isolation can also be achieved by forming the enclosure from double walls with a 10 mm gap therebetween. The pyrophoric enclosure can have a separate exhaust duct and/or scrubber than those of a semiconductor processing reactor associated with the enclosure.
    Type: Application
    Filed: March 1, 2007
    Publication date: February 7, 2008
    Applicant: ASM AMERICA, INC.
    Inventors: Charles A. Baskin, Timothy Provencher, Mike Manasco, Dae-Youn Kim
  • Patent number: 7326656
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Brian S. Doyle, Jack Kavalleros, Mark Doczy, Uday Shah, Robert S. Chau
  • Publication number: 20080026577
    Abstract: Organometallic compounds containing a phosphoamidinate ligand are provided. Such compounds are particularly suitable for use as vapor deposition precursors. Also provided are methods of depositing thin films, such as by ALD and CVD, using such compounds.
    Type: Application
    Filed: October 4, 2006
    Publication date: January 31, 2008
    Applicant: Rohm and Haas Electronic Materials LLC
    Inventors: Deodatta Vinayak Shenai-Khatkhate, Qing Min Wang
  • Publication number: 20080026575
    Abstract: A dispenser system for use in atomic beam assisted metal organic chemical vapor deposition is provided as well as a method of depositing an ultra-thin film using the same. The inventive dispenser system includes an atomic source having an unimpeded line of site to a substrate and an annular metal organic chemical vapor deposition showerhead having a plurality of nozzles for delivering a precursor to the substrate. In accordance with the present invention, each of the nozzles present on the showerhead is angled to provide precursor beam trajectories that crossover and are non-intercepting.
    Type: Application
    Filed: July 28, 2006
    Publication date: January 31, 2008
    Applicant: International Business Machines Corporation
    Inventors: Supratik Guha, Fenton R. McFeely, John J. Yurkas
  • Publication number: 20080026576
    Abstract: Certain organometallic compounds in the form of imino complexes are provided. Such complexes are particularly suitable for use as vapor deposition precursors. Also provided are methods of depositing thin films, such as by ALD and CVD, using such compounds.
    Type: Application
    Filed: September 29, 2006
    Publication date: January 31, 2008
    Applicant: Rohm and Haas Electronic Materials LLC
    Inventors: Deodatta Vinayak Shenai-Khatkhate, Qing Min Wang
  • Patent number: 7323411
    Abstract: In one embodiment, a selective tungsten deposition process includes the steps of pre-flowing silane into a deposition chamber, pumping down the chamber, and then selectively depositing tungsten on a silicon surface. The silane pre-flow helps minimize silicon consumption, while the pump down helps prevent loss of tungsten selectivity to silicon.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: January 29, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventor: Alain Blosse
  • Patent number: 7323412
    Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: January 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7314790
    Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: January 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
  • Patent number: 7311942
    Abstract: A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Cem Basceri, Donald L. Westmoreland
  • Patent number: 7312163
    Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: December 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7306956
    Abstract: A variable temperature and/or reactant dose atomic layer deposition (VTD-ALD) process modulates ALD reactor conditions (e.g., temperature, flow rates, etc.) during growth of a film (e.g., metallic) on a wafer to produce different film properties a different film depths.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: December 11, 2007
    Assignee: Intel Corporation
    Inventor: Ronald John Kuse
  • Patent number: 7303991
    Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: December 4, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Patent number: 7300859
    Abstract: A plasma is produced in a treatment space (58) by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes (54,56) separated by a dielectric material (64), a precursor material is introduced into the treatment space to coat a substrate film or web (14) by vapor deposition or atomized spraying at atmospheric pressure. The deposited precursor is cured by electron-beam, infrared-light, visible-light, or ultraviolet-light radiation, as most appropriate for the particular material being deposited. Additional plasma post-treatment may be used to enhance the properties of the resulting coated products.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: November 27, 2007
    Assignee: Sigma Laboratories of Arizona, LLC
    Inventors: Michael G. Mikhael, Angelo Yializis, Richard E. Ellwanger
  • Patent number: 7300873
    Abstract: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more homoleptic and/or heteroleptic precursor compounds that include, for example, guanidinate, phosphoguanidinate, isoureate, thioisoureate, and/or selenoisoureate ligands using a vapor deposition process is provided.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: November 27, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Publication number: 20070269982
    Abstract: Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use of a reaction inhibitor that selectively varies a deposition rate along a surface. One specific method includes atomic layer deposition. One method shown provides high step coverage over features such as trenches in trench plate capacitors. Also shown are methods and devices to provide uniform batch reactor layer thicknesses. Also shown are methods for forming alloy layers with high control over composition. Also shown are methods to selectively control growth rate to provide growth only on selected surfaces.
    Type: Application
    Filed: May 18, 2006
    Publication date: November 22, 2007
    Inventors: M. Noel Rocklein, F. Daniel Gealy
  • Patent number: 7297558
    Abstract: A W plug (24) is formed and a W oxidation preventing barrier metal film (25) is formed thereon. After that, an SiON film (27) thinner than the W oxidation preventing barrier metal film (25) is formed and Ar sputter etching is performed on the SiON film (27). As a result, the shape of the surface of the SiON film (27) becomes gentler and deep trenches disappear. Next, an SiON film (28) is formed on the whole surface. A voidless W oxidation preventing insulating film (29) is composed of the SiON (28) film and the SiON film (27).
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: November 20, 2007
    Assignee: Fujitsu Limited
    Inventors: Yasutaka Ozaki, Tatsuya Yokota, Nobutaka Ohyagi
  • Patent number: 7297634
    Abstract: Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a charge collecting region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting of charge carriers of one polarity type from the first conductive region, through the filter, and through the second conductive region to the charge collecting region while blocking the transport of charge carriers of an opposite polarity from the second conductive region to the first conductive region.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: November 20, 2007
    Assignee: Marvell World Trade Ltd.
    Inventor: Chih-Hsin Wang
  • Patent number: 7299104
    Abstract: Shock waves occurring when opening a gate valve between two vacuum chambers and peeling of particles by a viscous force taking place when a gas is supplied into a vacuum chamber are necessary to be suppressed by the apparatus and method of the invention, whereby contamination of a substrate by particles is suppressed. If one vacuum chamber is a substrate processing chamber for performing a vacuum process on the substrate and the other chamber is a transfer chamber having a substrate transfer device therein, the gate valve is opened when inner pressures of both the vacuum chambers are less than 66.5 Pa and higher one thereof is less than twice a lower one thereof. Preferably, a purge gas for peeling of particles is supplied, before supplying the purge gas for pressure control, into the substrate processing chamber with a flow rate greater than that of the purge gas for pressure control.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: November 20, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Kazuyuki Tezuka, Hiroshi Koizumi, Tsuyoshi Moriya, Hiroyuki Nakayama