Utilizing Chemical Vapor Deposition (i.e., Cvd) Patents (Class 438/680)
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Publication number: 20100151681Abstract: Titanium silicon nitride (TiSiN) films are formed in a cyclic chemical vapor deposition process. In some embodiments, the TiSiN films are formed in a batch reactor using TiCl4, NH3 and SiH4 as precursors. Substrates are provided in a deposition chamber of the batch reactor. In each deposition cycle, a TiN layer is formed on the substrates by flowing TiCl4 into the deposition chamber simultaneously with NH3. The deposition chamber is subsequently flushed with NH3. to prepare the TiN layer for silicon incorporation. SiH4 is subsequently flowed into the deposition chamber. Silicon from the SiH4 is incorporated into the TiN layers to form TiSiN. Exposing the TiN layers to NH3 before the silicon precursor has been found to facilitate efficient silicon incorporation into the TiN layers to form TiSiN.Type: ApplicationFiled: December 11, 2008Publication date: June 17, 2010Applicant: ASM INTERNATIONAL N.V.Inventors: Martin A. Knapp, Guido Probst
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Publication number: 20100151680Abstract: A substrate carrier is used in an in-line fabrication such as Plasma Enhanced Chemical Vapor Deposition (PECVD) for application of thin film on substrates. The carrier is in thermal communication with the substrate and thereby provides heat sinking. The carrier further permits movement of the substrate past a deposition apparatus at a deposition station.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: OPTISOLAR INC.Inventors: Shulin Wang, Gautam Ganguly, Marvin Keshner, Erik G. Vaaler, James Harroun, Paul McClelland
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Patent number: 7737458Abstract: A light emitting device having a straight-line shape is provided with: a pair of first and second electrodes each having a straight-line shape which face each other; and a phosphor layer having a straight-line shape provided so as to be sandwiched between the pair of electrodes, wherein at least one of the pair of first and second electrodes is a transparent electrode, at least one buffer layer is provided so as to be sandwiched between the first or second electrode and the phosphor layer, and the buffer layer makes the height of a potential barrier between the electrode and the phosphor layer which sandwich the buffer layer lower than the height of a Schottky barrier when the electrode and the phosphor layer are brought into direct contact.Type: GrantFiled: February 25, 2008Date of Patent: June 15, 2010Assignee: Panasonic CorporationInventors: Reiko Taniguchi, Masayuki Ono, Shogo Nasu, Eiichi Satoh, Toshiyuki Aoyama, Kenji Hasegawa, Masaru Odagiri
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Patent number: 7737034Abstract: A support section (28) for supporting a wafer (1) is convexly formed in the center of a receiving section (26) of a support groove (25) of a boat 21. At the time of boat loading of the boat (21), in which wafers (1) respectively received by the supporting sections (28) are aligned, from a standby chamber (33) to a processing chamber (14), the pressure in the standby chamber (33) and processing chamber (14) is set to 200 pascals or more, and 3000 pascals or less. By supporting the wafer upwards from the receiving section with use of the support section, even if peeling of the film on the wafer occurs from a large frictional force between the supported surface of the wafer and the support section under a reduced pressure, the particles from the peeling are caught by the receiving section and therefore particles are prevented from adhering to the IC fabrication surface of the wafer directly below the receiving section.Type: GrantFiled: June 26, 2003Date of Patent: June 15, 2010Assignee: Hitachi Kokusai Electric Inc.Inventors: Takashi Ozaki, Kenichi Suzaki
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Patent number: 7736963Abstract: In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.Type: GrantFiled: July 5, 2005Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Woong Lee, Young-Sub You, Hun-Hyeoung Leam, Yong-Woo Hyung, Jai-Dong Lee, Ki-Su Na, Jung-Hwan Kim
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Patent number: 7737024Abstract: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.Type: GrantFiled: April 27, 2006Date of Patent: June 15, 2010Assignee: Micron Technology, Inc.Inventors: Wing-Cheong Gilbert Lai, Gurtei Singh Sandhu
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Patent number: 7737035Abstract: An apparatus and method for sealing and unsealing a chemical deposition apparatus in a chemical deposition process chamber includes a microvolume that has dual sealing elements at its periphery. One seal, the outer seal, is used to seal the inside of the microvolume from the main process chamber. The second (inner) seal is used to seal the inside of the microvolume from a vacuum source. The apparatus and process of the present invention has several advantages for enhanced chamber performance.Type: GrantFiled: October 3, 2006Date of Patent: June 15, 2010Assignee: Novellus Systems, Inc.Inventors: Gary Lind, Colin F. Smith, William Johanson, Thomas M. Pratt, John Mazzocco
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Publication number: 20100140775Abstract: Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a circuit layer, a metal interconnection layer, and a deep via. The circuit layer is formed on a semiconductor substrate. The metal interconnection layer is formed on the circuit layer. The metal interconnection layer comprises a metal interconnection connected to the circuit layer. The deep via penetrates through the semiconductor substrate and the metal interconnection layer. The deep via comprises a laser-annealed crystalline silicon.Type: ApplicationFiled: December 3, 2009Publication date: June 10, 2010Inventor: Oh Jin Jung
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Publication number: 20100144145Abstract: When a step is delayed, an operator can be rapidly informed of the delay. A substrate processing apparatus comprises a process system configured to process a substrate, a control unit configured to control the process system for performing a plurality of steps, and a manipulation unit configured to monitor progresses of the steps. While the control unit waits for completion of a predetermined one of the steps after the control unit controls the process system to start the predetermined step, if a time elapsing from the start of the predetermined step exceeds an allowable time previously allocated to each of the steps, the control unit transmits an alarm message to the manipulation unit so as to report that the allowable time is exceeded.Type: ApplicationFiled: December 4, 2009Publication date: June 10, 2010Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventors: Satoru TAKAHATA, Yukio OZAKI, Reizo NUNOZAWA
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Patent number: 7732307Abstract: A modified TDEAT (tetrakisdiethylamino titanium) based MOCVD precursor for deposition of thin amorphous TiN:Si diffusion barrier layers. The TDEAT is doped with 10 at % Si using TDMAS (trisdimethlyaminosilane); the two liquids are found to form a stable solution when mixed together. Deposition occurs via pyrolysis of the vaporised precursor and NH3 on a heated substrate surface. Experimental results show that we have modified the precursor in such a way to reduce gas phase component of the deposition when compared to the unmodified TDEAT-NH3 reaction. Deposition temperatures were the range of 250-450° C. and under a range of process conditions the modified precursor shows improvements in coating conformality, a reduction in resistivity and an amorphous structure, as shown by TEM and XRD analysis. SIMS and scanning AES have shown that the film is essentially stoichiometric in Ti:N ratio and contains low levels of C (˜0.4 at %) and trace levels of incorporated Si (0.01<Si<0.5 at %).Type: GrantFiled: June 3, 2005Date of Patent: June 8, 2010Assignee: Aviza Technology LimitedInventors: Stephen Robert Burgess, Andrew Price, Nicholas Rimmer, John MacNeil
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Patent number: 7732304Abstract: A method of manufacturing a semiconductor device according to embodiments includes forming an interlayer dielectric film with a damascene pattern over a semiconductor substrate having a lower metal wire. A seed layer may be formed over the interlayer dielectric film including the damascene pattern. Impurities generated during the formation of the seed layer be removed through an annealing process using H2. A copper wire may then be formed by filling the damascene pattern.Type: GrantFiled: June 24, 2008Date of Patent: June 8, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Young-Seok Jeong
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Patent number: 7732325Abstract: In one embodiment, a method for depositing materials on a substrate is provided which includes forming a titanium nitride barrier layer on the substrate by sequentially exposing the substrate to a titanium precursor containing a titanium organic compound and a nitrogen plasma formed from a mixture of nitrogen gas and hydrogen gas. In another embodiment, the method includes exposing the substrate to the deposition gas containing the titanium organic compound to form a titanium-containing layer on the substrate, and exposing the titanium-containing layer disposed on the substrate to a nitrogen plasma formed from a mixture of nitrogen gas and hydrogen gas. The method further provides depositing a conductive material containing tungsten or copper over the substrate during a vapor deposition process. In some examples, the titanium organic compound may contain methylamido or ethylamido, such as tetrakis(dimethylamido)titanium, tetrakis(diethylamido)titanium, or derivatives thereof.Type: GrantFiled: January 5, 2009Date of Patent: June 8, 2010Assignee: Applied Materials, Inc.Inventors: Michael X. Yang, Toshio Itoh, Ming Xi
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Publication number: 20100133594Abstract: A semiconductor structure including a substrate, a gate dielectric layer, a gate, a source region and a drain region is provided. The gate dielectric layer is disposed on the substrate. At least one recess is disposed in the substrate. The gate is disposed on the gate dielectric layer and in the recess. The source and drain regions are respectively disposed in the substrate beside the gate.Type: ApplicationFiled: December 1, 2008Publication date: June 3, 2010Applicant: UNITED MICROELECTRONICS CORP.Inventor: Hung-Sung Lin
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Publication number: 20100136773Abstract: A semiconductor device manufacturing method comprises the steps of loading a substrate into a processing chamber, mounting the substrate on a support tool in the processing chamber, processing the substrate mounted on the support tool by supplying process gas into the processing chamber, purging the interior of the processing chamber after the substrate processing step, and unloading the processed substrate from the processing chamber after the step of purging the interior of the processing chamber, wherein in the step of purging the interior of the processing chamber, exhaust is performed toward above the substrate and toward below the substrate in the processing chamber, and the exhaust rate toward above the substrate is set larger than the exhaust rate toward below the substrate.Type: ApplicationFiled: August 4, 2006Publication date: June 3, 2010Inventors: Naonori Akae, Masahiro Yonebayashi, Tsukasa Kamakura, Yoshiro Hirose
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Patent number: 7727780Abstract: A semiconductor manufacturing apparatus and substrate processing method includes a step of acquiring a measurement value based on a first detecting and a second detecting section and determining a first difference of measurement values between the first detecting section and the second detecting section, comparing between a previously stored second difference between measurement values concerning the first detecting section and the second detecting section, calculating a correction value for a pressure in a cooling-gas passage provided between a process chamber and a heating device depending upon the first difference when the first difference is different from the second difference, and correcting the pressure value based on the pressure correction value, and a step of processing the substrate by flowing a cooling gas through the cooling-gas passage while heating the process chamber, and placing the heating device and the cooling device under a control section depending upon a pressure value corrected.Type: GrantFiled: January 23, 2008Date of Patent: June 1, 2010Assignee: Hitachi Kokusai Electric Inc.Inventors: Masashi Sugishita, Masaaki Ueno, Akira Hayashida
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Publication number: 20100130009Abstract: Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device, in which shape variations of discharge electrodes can be early detected so as to prevent a film having anon-uniform thickness from being formed on a substrate. The substrate processing apparatus includes a process chamber configured to stack a plurality of substrates therein, a gas supply unit configured to supply gas to an inside of the process chamber, at least one pair of electrodes installed in the process chamber and configured to receive high-frequency power to generate plasma that excites the gas supplied to the inside of the process chamber, and a monitoring system configured to monitor a shape variation of the electrodes.Type: ApplicationFiled: November 13, 2009Publication date: May 27, 2010Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventor: Nobuo ISHIMARU
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Patent number: 7723245Abstract: The ability to control a concentration ratio of a metal and silicon in a metal silicate film is improved, allowing a high-quality semiconductor device to be manufactured. A step is provided for supplying a first raw material, which contains a metal atom, and a second raw material, which contains a silicon atom and a nitrogen atom, into a processing chamber (4); and forming on a substrate (30) a metal silicate film containing the metal atom and silicon atom. A raw material supply ratio of the first and second raw materials is controlled in the step of forming a metal silicate film, thereby controlling a concentration ratio of the metal and silicon in the resulting metal silicate film.Type: GrantFiled: November 29, 2005Date of Patent: May 25, 2010Assignee: Hitachi Kokusai Electric Inc.Inventors: Atsushi Sano, Sadayoshi Horii, Hideharu Itatani, Katsuhiko Yamamoto
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Patent number: 7713874Abstract: Methods for performing periodic plasma annealing during atomic layer deposition are provided along with structures produced by such methods. The methods include contacting a substrate with a vapor-phase pulse of a metal source chemical and one or more plasma-excited reducing species for a period of time. Periodically, the substrate is contacted with a vapor phase pulse of one or more plasma-excited reducing species for a longer period of time. The steps are repeated until a metal thin film of a desired thickness is formed over the substrate.Type: GrantFiled: May 2, 2007Date of Patent: May 11, 2010Assignee: ASM America, Inc.Inventor: Robert B. Milligan
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Patent number: 7713868Abstract: A method for forming a strained metal nitride film and a semiconductor device containing the strained metal nitride film. The method includes exposing a substrate to a gas containing a metal precursor, exposing the substrate to a gas containing a nitrogen precursor activated by a plasma source at a first level of plasma power and configured to react with the metal precursor with a first reactivity characteristic, and exposing the substrate to a gas containing the nitrogen precursor activated by the plasma source at a second level of plasma power different from the first level and configured to react with the metal precursor with a second reactivity characteristic such that a property of the metal nitride film formed on the substrate changes to provide the strained metal nitride film.Type: GrantFiled: March 30, 2007Date of Patent: May 11, 2010Assignee: Tokyo Electron LimitedInventor: Robert D. Clark
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Publication number: 20100112814Abstract: The present invention relates generally to the field of semiconductor device manufacturing and more specifically to the manufacture and certification of semiconductor processing equipment. Systems and methods are described that establish a baseline contamination levels at each stage of the manufacture, assembly, testing, and installation of a process chamber.Type: ApplicationFiled: September 5, 2007Publication date: May 6, 2010Inventor: Sowmya Krishnan
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Publication number: 20100110607Abstract: A fabrication method which forms vertical capacitors in a substrate. The method is preferably an all-dry process, comprising forming a through-substrate via hole in the substrate, depositing a first conductive material layer into the via hole using atomic layer deposition (ALD) such that it is electrically continuous across the length of the via hole, depositing an electrically insulating, continuous and substantially conformal isolation material layer over the first conductive layer using ALD, and depositing a second conductive material layer over the isolation material layer using ALD such that it is electrically continuous across the length of the via hole. The layers are arranged such that they form a vertical capacitor. The present method may be successfully practiced at temperatures of less than 200° C., thereby avoiding damage to circuitry residing on the substrate that might otherwise occur.Type: ApplicationFiled: November 5, 2008Publication date: May 6, 2010Inventors: Jeffrey F. DeNatale, Philip A. Stupar, Alexandros P. Papavasiliou, Robert L. Borwick, III
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Publication number: 20100112805Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.Type: ApplicationFiled: January 7, 2010Publication date: May 6, 2010Applicant: Renesas Technology Corp.Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
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Patent number: 7709383Abstract: A film forming method comprising forming a liquid coating film on a substrate by supplying a liquid containing a coating type thin film forming substance and a solvent onto the substrate, substantially converging a variation in film thickness of the coating film, making the coating film stand by in an atmosphere including moisture under a predetermined condition after the substantial-convergence, the predetermined condition being such that a product of a time for which the coating film is exposed to the atmosphere and a water content per unit volume in an atmosphere in the vicinity of a surface of the coating film is made to be greater than or equal to a predetermined value, and forming a solid thin film on the substrate after the stand-by, the thin film being formed by carrying out an elimination of the solvent in the coating film and heat treatment for generating an irreversible reaction to the coating type thin film forming substance in the coating film.Type: GrantFiled: January 14, 2005Date of Patent: May 4, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hirokazu Kato, Tomoyuki Takeishi, Shinichi Ito
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Patent number: 7709385Abstract: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten-containing layer by sequentially exposing a substrate to a processing gas and a tungsten-containing gas during an atomic layer deposition process, wherein the processing gas comprises a boron-containing gas and a nitrogen-containing gas, and forming a tungsten bulk layer over the tungsten-containing layer by exposing the substrate to a deposition gas comprising the tungsten-containing gas and a reactive precursor gas during a chemical vapor deposition process. In one example, the tungsten-containing layer and the tungsten bulk layer are deposited within the same processing chamber.Type: GrantFiled: December 16, 2008Date of Patent: May 4, 2010Assignee: Applied Materials, Inc.Inventors: Ming Xi, Ashok Sinha, Moris Kori, Alfred W. Mak, Xinliang Lu, Ken Kaung Lai, Karl A. Littau
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Patent number: 7709384Abstract: Tantalum precursors useful in depositing tantalum nitride or tantalum oxides materials on substrates, by processes such as chemical vapor deposition and atomic layer deposition. The precursors are useful in forming tantalum-based diffusion barrier layers on microelectronic device structures featuring copper metallization and/or ferroelectric thin films.Type: GrantFiled: May 12, 2008Date of Patent: May 4, 2010Assignee: Advanced Technology Materials, Inc.Inventors: Tianniu Chen, Chongying Xu, Thomas H. Baum
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Patent number: 7709337Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.Type: GrantFiled: March 21, 2008Date of Patent: May 4, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiro Jinbo, Hironobu Shoji, Hideto Ohnuma, Shunpei Yamazaki
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Patent number: 7709398Abstract: The invention relates to a method and device for depositing at least one layer, particularly a semiconductor layer, onto at least one substrate, which is situated inside a process chamber of a reactor while being supported by a substrate holder. The layer is comprised of at least two material components provided in a fixed stoichiometric ratio, which are each introduced into the reactor in the form of a first and a second reaction gas, and a portion of the decomposition products form the layer, whereby the supply of the first reaction gas, which has a low thermal activation energy, determines the growth rate of the layer, and the second reaction gas, which has a high thermal activation energy, is supplied in excess and is preconditioned, in particular, by an independent supply of energy. The first reaction gas flows in a direction toward the substrate holder through a multitude of openings, which are distributed over a surface of a gas inlet element, said surface being located opposite the substrate holder.Type: GrantFiled: October 31, 2005Date of Patent: May 4, 2010Assignee: Aixtron AGInventors: Gerhard Karl Strauch, Johannes Kaeppeler, Markus Reinhold, Bernd Schulte
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Patent number: 7704858Abstract: A method for forming a nickel silicide layer on a MOS device with a low carbon content comprises providing a substrate within an ALD reactor and performing an ALD process cycle to form a nickel layer on the substrate, wherein the ALD process cycle comprises pulsing a nickel precursor into the reactor, purging the reactor after the nickel precursor, pulsing a mixture of hydrogen and silane into the reactor, and purging the reactor after the hydrogen and silane pulse. The ALD process cycle can be repeated until the nickel layer reaches a desired thickness. The silane used in the ALD process functions as a getterer for the advantageous carbon, resulting in a nickel layer that has a low carbon content. The nickel layer may then be annealed to form a nickel silicide layer with a low carbon content.Type: GrantFiled: March 29, 2007Date of Patent: April 27, 2010Assignee: Intel CorporationInventors: Michael L. McSwiney, Matthew V. Metz
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Patent number: 7704886Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.Type: GrantFiled: February 14, 2008Date of Patent: April 27, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Lin Su, Shing-Chyang Pan, Cheng-Lin Huang, Ching-Hua Hsieh
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Patent number: 7700486Abstract: A method for seasoning a chamber and depositing a low dielectric constant layer on a substrate in the chamber is provided. In one aspect, the method includes seasoning the chamber with a first mixture comprising one or more organosilicon compounds and one or more oxidizing gases and depositing a low dielectric constant layer on a substrate in the chamber from a second mixture comprising one or more organosilicon compounds and one or more oxidizing gases, wherein a ratio of the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the first mixture is lower than the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the second mixture.Type: GrantFiled: June 16, 2006Date of Patent: April 20, 2010Assignee: Applied Materials, Inc.Inventors: Sohyun Park, Wen H. Zhu, Tzu-Fang Huang, Li-Qun Xia, Hichem M'Saad
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Publication number: 20100093170Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.Type: ApplicationFiled: December 22, 2009Publication date: April 15, 2010Inventors: Moris Kori, Alfred W. Mak, Jeong Soo Byun, Lawrence Chung-Lai Lei, Hua Chung
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Publication number: 20100087063Abstract: The present invention describes nano-scale fabrication technique used to create a sub-micron wide gap across the center conductor of a coplanar waveguide transmission line configured in a fixed-fixed beam arrangement, resulting in a pair of opposing cantilever beams that comprise an electro-mechanical switch. Accordingly, a nanometer-scale mechanical switch with very high switching speed and low actuation voltage has been developed. This switch is intended primarily for application in the RF/microwave/wireless industry.Type: ApplicationFiled: November 7, 2008Publication date: April 8, 2010Applicant: UNIVERSITY OF SOUTH FLORIDAInventors: Thomas Weller, Thomas Ketterl
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Publication number: 20100087064Abstract: The present inventors have found that a wafer process of VLSI (Very Large Scale Integration) has the following problem, that is, generation of foreign matters due to moisture from a wafer as a result of degassing when a barrier metal film or a first-level metal interconnect layer is formed by sputtering as a preliminary step for the formation of a tungsten plug in a pre-metal step. To overcome the problem, the present invention provides a manufacturing method of a semiconductor integrated circuit device including, in a plasma process, in-situ monitoring of moisture in a processing chamber by receiving an electromagnetic wave generated from plasma.Type: ApplicationFiled: September 9, 2009Publication date: April 8, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazuyuki FUJII, Toshihiko MINAMI, Hideaki KANAZAWA
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Patent number: 7693597Abstract: A substrate processing method for removing a resist film from a substrate having the resist film formed thereon comprises maintaining the inner region of the chamber at a prescribed temperature by putting a substrate in a chamber, denaturing the resist film by supplying ozone and a water vapor in such a manner that ozone is supplied into the chamber while a water vapor is supplied into the chamber at a prescribed flow rate, the amount of ozone relative to the amount of the water vapor being adjusted such that the dew formation within the chamber is prevented, and processing the substrate with a prescribed liquid material so as to remove the denatured resist film from the substrate.Type: GrantFiled: October 5, 2005Date of Patent: April 6, 2010Assignee: Tokyo Electron LimitedInventors: Mitsunori Nakamori, Tadashi Iino, Noritaka Uchida, Takehiko Orii
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Patent number: 7691749Abstract: Methods for depositing a tungsten nitride layer are described. The methods form a tungsten nitride layer using a carefully controlled deposition technique such as pulsed nucleation layer (PNL). Initially, a tungsten layer is formed on a substrate surface. The tungsten layer is then exposed to a nitriding agent to form a tungsten nitride layer. Methods of forming relatively thick layers of involve repeated cycles of contact with reducing agent, tungsten precursor and nitriding agent. In some cases, the cycle may also include contact with a dopant precursor such as phosphine or arsine.Type: GrantFiled: December 16, 2005Date of Patent: April 6, 2010Assignee: Novellus Systems, Inc.Inventors: Karl B. Levy, Junghwan Sung, Kaihan A. Ashtiani, James A. Fair, Joshua Collins, Juwen Gao
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Patent number: 7691696Abstract: Hemi-spherical structure and method for fabricating the same. A device includes discrete pillar regions on a substrate, and a pattern layer on the discrete support structures and the substrate. The pattern layer has hemi-spherical film regions on the discrete support structures respectively, and planarized portions on the substrate between the hemi-spherical film regions. Each of the hemi-spherical film regions in a position corresponding to each of the support structures serves as a hemi-spherical structure.Type: GrantFiled: March 13, 2008Date of Patent: April 6, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chyi Liu, Chi-Hsin Lo
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Publication number: 20100078651Abstract: Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials.Type: ApplicationFiled: January 22, 2008Publication date: April 1, 2010Inventors: Christopher John Howard Wort, Geoffrey Alan Scarsbrook, Ian Friel, Richard Stuart Balmer
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Publication number: 20100078601Abstract: Methods and compositions for depositing rare earth metal-containing layers are described herein. In general, the disclosed methods deposit the precursor compounds comprising rare earth-containing compounds using vapor deposition methods such as chemical vapor deposition or atomic layer deposition. In certain embodiments, the disclosed precursor compounds include a cyclopentadienyl ligand having at least one aliphatic group as a substituent.Type: ApplicationFiled: March 30, 2009Publication date: April 1, 2010Applicant: American Air Liquide, Inc.Inventors: Venkateswara R. PALLEM, Benjamin J. Feist, Nathan Stafford, Christian Dussarrat
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Patent number: 7687398Abstract: Nickel silicide is formed on the basis of a gaseous precursor, such as nickel tetra carbonyl, wherein the equilibrium of the decomposition of this gas may be controlled to obtain a highly selective nickel silicide formation rate. Moreover, any etch step for removing excess nickel may be avoided, since only minute amounts of nickel may form on exposed surfaces, which may then be effectively removed by correspondingly shifting the equilibrium. Consequently, reduced process complexity, enhanced controllability and enhanced tool lifetime may be obtained.Type: GrantFiled: April 25, 2006Date of Patent: March 30, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Christof Streck, Volker Kahlert, Alexander Hanke
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Patent number: 7682973Abstract: A method of forming a Carbon NanoTube (CNT) structure and a method of manufacturing a Field Emission Device (FED) using the method of forming a CNT structure includes: forming an electrode on a substrate, forming a buffer layer on the electrode, forming a catalyst layer in a particle shape on the buffer layer, etching the buffer layer exposed through the catalyst layer, and growing CNTs from the catalyst layer formed on the etched buffer layer.Type: GrantFiled: January 23, 2007Date of Patent: March 23, 2010Assignee: Samsung SDI Co., Ltd.Inventors: Ha-Jin Kim, In-Taek Han, Young-Chul Choi, Kwang-Seok Jeong
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Publication number: 20100065971Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming an identification mark on a portion of a backside of an individual die of a wafer by utilizing laser assisted CVD, wherein the formation of the identification mark is localized to a focal spot of the laser.Type: ApplicationFiled: September 17, 2008Publication date: March 18, 2010Inventors: Eric Li, Sergei Voronov
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Publication number: 20100065803Abstract: Provided is a resistance variable non-volatile memory device using a trap-controlled Space Charge Limited Current (SCLC), and a manufacturing method thereof. The memory device includes a bottom electrode; an inter-electrode dielectric thin film diffusion prevention film formed on the bottom electrode; a dielectric thin film formed on the inter-electrode dielectric thin film diffusion prevention film and having a plurality of layers with different charge trap densities; and a top electrode formed on the dielectric thin film.Type: ApplicationFiled: November 28, 2007Publication date: March 18, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Sung-Yool Choi, Min-Ki Ryu, Hu-Young Jeong
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Patent number: 7678698Abstract: A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.Type: GrantFiled: May 4, 2007Date of Patent: March 16, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Xiangzheng Bo, Tien Ying Luo, Kurt H. Junker, Paul A. Grudowski, Venkat R. Kolagunta
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Patent number: 7674700Abstract: Disclosed are an apparatus and a method for manufacturing a semiconductor device. The apparatus comprises a transfer chamber for transferring a substrate, a first process chamber connected to the transfer chamber configured to form a TiSiN layer on the substrate, a second process chamber connected to the transfer chamber configured to form a tantalum layer on the TiSiN layer, and a third process chamber connected to the transfer chamber configured to form a copper seed layer on the tantalum layer. After forming the TiSiN layer, a portion of the TiSiN layer in contact with the lower metal interconnection is etched, the tantalum layer is formed on the TiSiN layer in contact with the exposed lower metal interconnection, the copper seed layer is formed on the tantalum layer, and then the copper interconnection is formed on the copper seed layer. In this way, the copper interconnection can be efficiently formed.Type: GrantFiled: August 24, 2007Date of Patent: March 9, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Han Choon Lee
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Patent number: 7674713Abstract: A process for coating a substrate at atmospheric pressure comprises the steps of vaporizing a controlled mass of semiconductor material at substantially atmospheric pressure within a heated inert gas stream, to create a fluid mixture having a temperature above the condensation temperature of the semiconductor material, directing the fluid mixture at substantially atmospheric pressure onto the substrate having a temperature below the condensation temperature of the semiconductor material, and depositing a layer of the semiconductor material onto a surface of the substrate.Type: GrantFiled: August 2, 2005Date of Patent: March 9, 2010Assignee: Calyxo GmbHInventors: Norman W. Johnston, Kenneth R. Kormanyos, Nicholas A. Reiter
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Publication number: 20100055806Abstract: A compact large density memory piezoactuated storage device and process for its fabrication provides an integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure that features an integrated large density array of nanotips made of wear-resistant conductive ultrananocrystalline diamond (UNCD) in which the tips are actuated via a piezoelectric thin film integrated with the UNCD tips. The tips of the special piezoactuated storage device effectively contact an underlying metal layer (top electrode) deposited on a polarizable ferroelectric layer that is grown on top of another metal layer (bottom electrode) to form a ferroelectric capacitor. Information is imprinted in the ferroelectric layer by the polarization induced by the application of a voltage pulse between the top and bottom electrodes through the conductive UNCD tips.Type: ApplicationFiled: September 10, 2009Publication date: March 4, 2010Inventor: Orlando H. Auciello
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Publication number: 20100055904Abstract: Methods of producing low resistivity tungsten bulk layers having lower roughness and higher reflectivity are provided. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. The methods involve CVD deposition of tungsten in the presence of alternating nitrogen gas pulses, such that alternating portions of the film are deposited by CVD in the absence of nitrogen and in the presence of nitrogen. According to various embodiments, between 20-90% of the total film thickness is deposited by CVD in the presence of nitrogen.Type: ApplicationFiled: August 29, 2008Publication date: March 4, 2010Applicant: Novellus Systems Inc.Inventors: Feng CHEN, Raashina Humayun, Abhishek Manohar
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Patent number: 7666762Abstract: A method for fabricating a semiconductor device is provided. A nickel layer is deposited on a semiconductor substrate and plasma-processed. Rapid thermal processing is performed on the plasma-processed nickel layer to form a nickel silicide layer. The portion of the nickel layer that has not reacted with silicon is then removed.Type: GrantFiled: September 28, 2007Date of Patent: February 23, 2010Assignee: Dongbu Hitek Co., Ltd.Inventors: Dong Ki Jeon, Han Choon Lee
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Patent number: 7666792Abstract: The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.Type: GrantFiled: February 22, 2008Date of Patent: February 23, 2010Assignee: Nanya Technology Corp.Inventors: Chung-Yen Chou, Hai-Han Hung, Teng-Wang Huang, Shin-Yu Nieh
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Publication number: 20100032842Abstract: A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N2 gas flow to the nitrogen plasma, resulting in a Ti:N stoichiometry between 1:2.1 to 1:2.3. TiN films thicker than 40 nanometers without cracks are attained by the disclosed process.Type: ApplicationFiled: August 7, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory Charles HERDT, Joseph W. BUCKFELLER